DE3886571D1 - EPROM-Speicherzelle mit zwei symmetrischen Halbzellen und mit getrennten schwebenden Gittern. - Google Patents

EPROM-Speicherzelle mit zwei symmetrischen Halbzellen und mit getrennten schwebenden Gittern.

Info

Publication number
DE3886571D1
DE3886571D1 DE88200420T DE3886571T DE3886571D1 DE 3886571 D1 DE3886571 D1 DE 3886571D1 DE 88200420 T DE88200420 T DE 88200420T DE 3886571 T DE3886571 T DE 3886571T DE 3886571 D1 DE3886571 D1 DE 3886571D1
Authority
DE
Germany
Prior art keywords
memory cell
eprom memory
half cells
symmetrical half
separate floating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88200420T
Other languages
English (en)
Other versions
DE3886571T2 (de
Inventor
Giuseppe Corda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of DE3886571D1 publication Critical patent/DE3886571D1/de
Application granted granted Critical
Publication of DE3886571T2 publication Critical patent/DE3886571T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE88200420T 1987-03-12 1988-03-04 EPROM-Speicherzelle mit zwei symmetrischen Halbzellen und mit getrennten schwebenden Gittern. Expired - Fee Related DE3886571T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8719656A IT1215380B (it) 1987-03-12 1987-03-12 Cella di memoria eprom a due semicelle simmetriche con gate flottante separata.

Publications (2)

Publication Number Publication Date
DE3886571D1 true DE3886571D1 (de) 1994-02-10
DE3886571T2 DE3886571T2 (de) 1994-04-28

Family

ID=11160124

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88200420T Expired - Fee Related DE3886571T2 (de) 1987-03-12 1988-03-04 EPROM-Speicherzelle mit zwei symmetrischen Halbzellen und mit getrennten schwebenden Gittern.

Country Status (5)

Country Link
US (1) US4896295A (de)
EP (1) EP0282137B1 (de)
JP (1) JP2673529B2 (de)
DE (1) DE3886571T2 (de)
IT (1) IT1215380B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1217403B (it) * 1988-04-12 1990-03-22 Sgs Thomson Microelectronics Matrice di memoria a tovaglia con celle eprom sfalsate
US5238855A (en) * 1988-11-10 1993-08-24 Texas Instruments Incorporated Cross-point contact-free array with a high-density floating-gate structure
US5051796A (en) * 1988-11-10 1991-09-24 Texas Instruments Incorporated Cross-point contact-free array with a high-density floating-gate structure
IT1229131B (it) * 1989-03-09 1991-07-22 Sgs Thomson Microelectronics Matrice di memoria eprom con struttura a tovaglia e procedimento per la sua fabbricazione.
FR2663147A1 (fr) * 1990-06-12 1991-12-13 Sgs Thomson Microelectronics Memoire programmable a double transistor a grille flottante.
JP2685966B2 (ja) * 1990-06-22 1997-12-08 株式会社東芝 不揮発性半導体記憶装置
US5291045A (en) * 1991-03-29 1994-03-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device using a differential cell in a memory cell
JP2848211B2 (ja) * 1993-10-08 1999-01-20 日本電気株式会社 不揮発性半導体記憶装置
US6329245B1 (en) * 1999-12-20 2001-12-11 Chartered Semiconductor Manufacturing Ltd. Flash memory array structure with reduced bit-line pitch
US7973557B2 (en) * 2008-05-02 2011-07-05 Texas Instruments Incorporated IC having programmable digital logic cells
JP5522296B2 (ja) * 2013-06-03 2014-06-18 凸版印刷株式会社 不揮発性半導体記憶装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4377818A (en) * 1978-11-02 1983-03-22 Texas Instruments Incorporated High density electrically programmable ROM
JPS5728364A (en) * 1980-07-28 1982-02-16 Fujitsu Ltd Semiconductor memory device
JPS5961189A (ja) * 1982-09-15 1984-04-07 ナシヨナル・セミコンダクタ−・コ−ポレ−シヨン 高密度型ｅｐｒｏｍメモリ−・アレ−
US4546454A (en) * 1982-11-05 1985-10-08 Seeq Technology, Inc. Non-volatile memory cell fuse element
US4639893A (en) * 1984-05-15 1987-01-27 Wafer Scale Integration, Inc. Self-aligned split gate EPROM
IT1213241B (it) * 1984-11-07 1989-12-14 Ates Componenti Elettron Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura.
US4597060A (en) * 1985-05-01 1986-06-24 Texas Instruments Incorporated EPROM array and method for fabricating
US4774202A (en) * 1985-11-07 1988-09-27 Sprague Electric Company Memory device with interconnected polysilicon layers and method for making

Also Published As

Publication number Publication date
IT1215380B (it) 1990-02-08
EP0282137A2 (de) 1988-09-14
EP0282137B1 (de) 1993-12-29
JP2673529B2 (ja) 1997-11-05
DE3886571T2 (de) 1994-04-28
JPS63249376A (ja) 1988-10-17
US4896295A (en) 1990-01-23
EP0282137A3 (en) 1990-03-14
IT8719656A0 (it) 1987-03-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee