IT1217403B - Matrice di memoria a tovaglia con celle eprom sfalsate - Google Patents

Matrice di memoria a tovaglia con celle eprom sfalsate

Info

Publication number
IT1217403B
IT1217403B IT20169/88A IT2016988A IT1217403B IT 1217403 B IT1217403 B IT 1217403B IT 20169/88 A IT20169/88 A IT 20169/88A IT 2016988 A IT2016988 A IT 2016988A IT 1217403 B IT1217403 B IT 1217403B
Authority
IT
Italy
Prior art keywords
tablecloth
staggered
memory matrix
eprom cells
eprom
Prior art date
Application number
IT20169/88A
Other languages
English (en)
Other versions
IT8820169A0 (it
Inventor
Stefano Mazzali
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT20169/88A priority Critical patent/IT1217403B/it
Publication of IT8820169A0 publication Critical patent/IT8820169A0/it
Priority to EP89200702A priority patent/EP0337529B1/en
Priority to DE89200702T priority patent/DE68909285T2/de
Priority to US07/326,809 priority patent/US5005060A/en
Priority to JP1084919A priority patent/JPH0775249B2/ja
Application granted granted Critical
Publication of IT1217403B publication Critical patent/IT1217403B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
IT20169/88A 1988-04-12 1988-04-12 Matrice di memoria a tovaglia con celle eprom sfalsate IT1217403B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT20169/88A IT1217403B (it) 1988-04-12 1988-04-12 Matrice di memoria a tovaglia con celle eprom sfalsate
EP89200702A EP0337529B1 (en) 1988-04-12 1989-03-20 Tablecloth memory matrix with staggered eprom cells
DE89200702T DE68909285T2 (de) 1988-04-12 1989-03-20 Tafeltuchspeichermatrix mit schachbrettförmiger EPROM-Zellenanordnung.
US07/326,809 US5005060A (en) 1988-04-12 1989-03-21 Tablecloth memory matrix with staggered EPROM cells
JP1084919A JPH0775249B2 (ja) 1988-04-12 1989-04-05 スタッガー配列のｅｐｒｏｍセルを備えたテーブルクロス形メモリマトリックス

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT20169/88A IT1217403B (it) 1988-04-12 1988-04-12 Matrice di memoria a tovaglia con celle eprom sfalsate

Publications (2)

Publication Number Publication Date
IT8820169A0 IT8820169A0 (it) 1988-04-12
IT1217403B true IT1217403B (it) 1990-03-22

Family

ID=11164374

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20169/88A IT1217403B (it) 1988-04-12 1988-04-12 Matrice di memoria a tovaglia con celle eprom sfalsate

Country Status (5)

Country Link
US (1) US5005060A (it)
EP (1) EP0337529B1 (it)
JP (1) JPH0775249B2 (it)
DE (1) DE68909285T2 (it)
IT (1) IT1217403B (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1235690B (it) * 1989-04-07 1992-09-21 Sgs Thomson Microelectronics Procedimento di fabbricazione per una matrice di celle eprom organizzate a tovaglia.
JP2565213B2 (ja) * 1989-10-27 1996-12-18 ソニー株式会社 読み出し専用メモリ装置
JPH088316B2 (ja) * 1990-01-31 1996-01-29 株式会社東芝 紫外線消去型不揮発性半導体メモリ装置
KR940004609B1 (ko) * 1991-09-04 1994-05-25 삼성전자 주식회사 마스크 리드 온리 메모리
US7132751B2 (en) * 2004-06-22 2006-11-07 Intel Corporation Memory cell using silicon carbide
JP2010021492A (ja) * 2008-07-14 2010-01-28 Toshiba Corp 不揮発性半導体記憶装置およびその制御方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4207585A (en) * 1976-07-01 1980-06-10 Texas Instruments Incorporated Silicon gate MOS ROM
US4377818A (en) * 1978-11-02 1983-03-22 Texas Instruments Incorporated High density electrically programmable ROM
US4326331A (en) * 1979-09-17 1982-04-27 Texas Instruments Incorporated High coupling ratio electrically programmable ROM
US4281397A (en) * 1979-10-29 1981-07-28 Texas Instruments Incorporated Virtual ground MOS EPROM or ROM matrix
US4493057A (en) * 1980-01-07 1985-01-08 Texas Instruments Incorporated Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like
IT1213241B (it) * 1984-11-07 1989-12-14 Ates Componenti Elettron Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura.
IT1215380B (it) * 1987-03-12 1990-02-08 Sgs Microelettronica Spa Cella di memoria eprom a due semicelle simmetriche con gate flottante separata.

Also Published As

Publication number Publication date
EP0337529A2 (en) 1989-10-18
EP0337529B1 (en) 1993-09-22
DE68909285T2 (de) 1994-05-05
JPH0212869A (ja) 1990-01-17
DE68909285D1 (de) 1993-10-28
IT8820169A0 (it) 1988-04-12
EP0337529A3 (en) 1990-01-31
JPH0775249B2 (ja) 1995-08-09
US5005060A (en) 1991-04-02

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970429