IT8919778A0 - Matrice a tovaglia di celle di memoria eprom con aletta asimmetrica. - Google Patents

Matrice a tovaglia di celle di memoria eprom con aletta asimmetrica.

Info

Publication number
IT8919778A0
IT8919778A0 IT8919778A IT1977889A IT8919778A0 IT 8919778 A0 IT8919778 A0 IT 8919778A0 IT 8919778 A IT8919778 A IT 8919778A IT 1977889 A IT1977889 A IT 1977889A IT 8919778 A0 IT8919778 A0 IT 8919778A0
Authority
IT
Italy
Prior art keywords
tablecloth
matrix
memory cells
eprom memory
asymmetric flap
Prior art date
Application number
IT8919778A
Other languages
English (en)
Other versions
IT1228721B (it
Inventor
Stefano Mazzali
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8919778A priority Critical patent/IT1228721B/it
Publication of IT8919778A0 publication Critical patent/IT8919778A0/it
Priority to DE69014356T priority patent/DE69014356T2/de
Priority to EP90200509A priority patent/EP0387935B1/en
Priority to JP2060155A priority patent/JP2520756B2/ja
Application granted granted Critical
Publication of IT1228721B publication Critical patent/IT1228721B/it
Priority to US07/753,028 priority patent/US5196914A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
IT8919778A 1989-03-15 1989-03-15 Matrice a tovaglia di celle di memoria eprom con aletta asimmetrica. IT1228721B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8919778A IT1228721B (it) 1989-03-15 1989-03-15 Matrice a tovaglia di celle di memoria eprom con aletta asimmetrica.
DE69014356T DE69014356T2 (de) 1989-03-15 1990-03-05 Tischtuchmatrix von EPROM-Speicherzellen mit einer asymmetrischen Leitplatte.
EP90200509A EP0387935B1 (en) 1989-03-15 1990-03-05 Table cloth matrix of EPROM memory cells with an asymmetrical fin
JP2060155A JP2520756B2 (ja) 1989-03-15 1990-03-13 非対称フインを有するｅｐｒｏｍメモリセルのテ―ブルクロス型マトリックス
US07/753,028 US5196914A (en) 1989-03-15 1991-08-29 Table cloth matrix of EPROM memory cells with an asymmetrical fin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8919778A IT1228721B (it) 1989-03-15 1989-03-15 Matrice a tovaglia di celle di memoria eprom con aletta asimmetrica.

Publications (2)

Publication Number Publication Date
IT8919778A0 true IT8919778A0 (it) 1989-03-15
IT1228721B IT1228721B (it) 1991-07-03

Family

ID=11161141

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8919778A IT1228721B (it) 1989-03-15 1989-03-15 Matrice a tovaglia di celle di memoria eprom con aletta asimmetrica.

Country Status (4)

Country Link
EP (1) EP0387935B1 (it)
JP (1) JP2520756B2 (it)
DE (1) DE69014356T2 (it)
IT (1) IT1228721B (it)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258466A (en) * 1978-11-02 1981-03-31 Texas Instruments Incorporated High density electrically programmable ROM

Also Published As

Publication number Publication date
EP0387935B1 (en) 1994-11-30
EP0387935A1 (en) 1990-09-19
JPH02292861A (ja) 1990-12-04
JP2520756B2 (ja) 1996-07-31
DE69014356T2 (de) 1995-07-20
IT1228721B (it) 1991-07-03
DE69014356D1 (de) 1995-01-12

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970329