IT8719656A0 - Cella di memoria eprom a due semicelle simmetriche con gate flottante separata. - Google Patents

Cella di memoria eprom a due semicelle simmetriche con gate flottante separata.

Info

Publication number
IT8719656A0
IT8719656A0 IT8719656A IT1965687A IT8719656A0 IT 8719656 A0 IT8719656 A0 IT 8719656A0 IT 8719656 A IT8719656 A IT 8719656A IT 1965687 A IT1965687 A IT 1965687A IT 8719656 A0 IT8719656 A0 IT 8719656A0
Authority
IT
Italy
Prior art keywords
cells
memory cell
floating gate
eprom memory
separate floating
Prior art date
Application number
IT8719656A
Other languages
English (en)
Other versions
IT1215380B (it
Inventor
Giuseppe Corda
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT8719656A priority Critical patent/IT1215380B/it
Publication of IT8719656A0 publication Critical patent/IT8719656A0/it
Priority to DE88200420T priority patent/DE3886571T2/de
Priority to EP88200420A priority patent/EP0282137B1/en
Priority to JP5650188A priority patent/JP2673529B2/ja
Priority to US07/167,986 priority patent/US4896295A/en
Application granted granted Critical
Publication of IT1215380B publication Critical patent/IT1215380B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
IT8719656A 1987-03-12 1987-03-12 Cella di memoria eprom a due semicelle simmetriche con gate flottante separata. IT1215380B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8719656A IT1215380B (it) 1987-03-12 1987-03-12 Cella di memoria eprom a due semicelle simmetriche con gate flottante separata.
DE88200420T DE3886571T2 (de) 1987-03-12 1988-03-04 EPROM-Speicherzelle mit zwei symmetrischen Halbzellen und mit getrennten schwebenden Gittern.
EP88200420A EP0282137B1 (en) 1987-03-12 1988-03-04 EPROM memory cell with two symmetrical half-cells and separate floating gates
JP5650188A JP2673529B2 (ja) 1987-03-12 1988-03-11 Ｅｐｒｏｍメモリセルマトリックス
US07/167,986 US4896295A (en) 1987-03-12 1988-03-14 Eprom memory cell with two symmetrical half-cells and separate floating gates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8719656A IT1215380B (it) 1987-03-12 1987-03-12 Cella di memoria eprom a due semicelle simmetriche con gate flottante separata.

Publications (2)

Publication Number Publication Date
IT8719656A0 true IT8719656A0 (it) 1987-03-12
IT1215380B IT1215380B (it) 1990-02-08

Family

ID=11160124

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8719656A IT1215380B (it) 1987-03-12 1987-03-12 Cella di memoria eprom a due semicelle simmetriche con gate flottante separata.

Country Status (5)

Country Link
US (1) US4896295A (it)
EP (1) EP0282137B1 (it)
JP (1) JP2673529B2 (it)
DE (1) DE3886571T2 (it)
IT (1) IT1215380B (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1217403B (it) * 1988-04-12 1990-03-22 Sgs Thomson Microelectronics Matrice di memoria a tovaglia con celle eprom sfalsate
US5238855A (en) * 1988-11-10 1993-08-24 Texas Instruments Incorporated Cross-point contact-free array with a high-density floating-gate structure
US5051796A (en) * 1988-11-10 1991-09-24 Texas Instruments Incorporated Cross-point contact-free array with a high-density floating-gate structure
IT1229131B (it) * 1989-03-09 1991-07-22 Sgs Thomson Microelectronics Matrice di memoria eprom con struttura a tovaglia e procedimento per la sua fabbricazione.
FR2663147A1 (fr) * 1990-06-12 1991-12-13 Sgs Thomson Microelectronics Memoire programmable a double transistor a grille flottante.
JP2685966B2 (ja) * 1990-06-22 1997-12-08 株式会社東芝 不揮発性半導体記憶装置
US5291045A (en) * 1991-03-29 1994-03-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device using a differential cell in a memory cell
JP2848211B2 (ja) * 1993-10-08 1999-01-20 日本電気株式会社 不揮発性半導体記憶装置
US6329245B1 (en) * 1999-12-20 2001-12-11 Chartered Semiconductor Manufacturing Ltd. Flash memory array structure with reduced bit-line pitch
US7973557B2 (en) * 2008-05-02 2011-07-05 Texas Instruments Incorporated IC having programmable digital logic cells
JP5522296B2 (ja) * 2013-06-03 2014-06-18 凸版印刷株式会社 不揮発性半導体記憶装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4377818A (en) * 1978-11-02 1983-03-22 Texas Instruments Incorporated High density electrically programmable ROM
JPS5728364A (en) * 1980-07-28 1982-02-16 Fujitsu Ltd Semiconductor memory device
JPS5961189A (ja) * 1982-09-15 1984-04-07 ナシヨナル・セミコンダクタ−・コ−ポレ−シヨン 高密度型ｅｐｒｏｍメモリ−・アレ−
US4546454A (en) * 1982-11-05 1985-10-08 Seeq Technology, Inc. Non-volatile memory cell fuse element
US4639893A (en) * 1984-05-15 1987-01-27 Wafer Scale Integration, Inc. Self-aligned split gate EPROM
IT1213241B (it) * 1984-11-07 1989-12-14 Ates Componenti Elettron Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura.
US4597060A (en) * 1985-05-01 1986-06-24 Texas Instruments Incorporated EPROM array and method for fabricating
US4774202A (en) * 1985-11-07 1988-09-27 Sprague Electric Company Memory device with interconnected polysilicon layers and method for making

Also Published As

Publication number Publication date
US4896295A (en) 1990-01-23
DE3886571D1 (de) 1994-02-10
DE3886571T2 (de) 1994-04-28
JPS63249376A (ja) 1988-10-17
JP2673529B2 (ja) 1997-11-05
EP0282137A2 (en) 1988-09-14
EP0282137A3 (en) 1990-03-14
EP0282137B1 (en) 1993-12-29
IT1215380B (it) 1990-02-08

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970329