GB2236881B - Improved synapse cell employing dual gate transistor structure - Google Patents

Improved synapse cell employing dual gate transistor structure

Info

Publication number
GB2236881B
GB2236881B GB9011972A GB9011972A GB2236881B GB 2236881 B GB2236881 B GB 2236881B GB 9011972 A GB9011972 A GB 9011972A GB 9011972 A GB9011972 A GB 9011972A GB 2236881 B GB2236881 B GB 2236881B
Authority
GB
United Kingdom
Prior art keywords
gate transistor
transistor structure
dual gate
cell employing
employing dual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9011972A
Other versions
GB9011972D0 (en
GB2236881A (en
Inventor
Simon M Tam
Mark A Holler
Hernan A Castro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/419,685 external-priority patent/US4961002A/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB9011972D0 publication Critical patent/GB9011972D0/en
Publication of GB2236881A publication Critical patent/GB2236881A/en
Application granted granted Critical
Publication of GB2236881B publication Critical patent/GB2236881B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Data Mining & Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Computational Linguistics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Neurology (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
GB9011972A 1989-10-11 1990-05-29 Improved synapse cell employing dual gate transistor structure Expired - Fee Related GB2236881B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/419,685 US4961002A (en) 1989-07-13 1989-10-11 Synapse cell employing dual gate transistor structure

Publications (3)

Publication Number Publication Date
GB9011972D0 GB9011972D0 (en) 1990-07-18
GB2236881A GB2236881A (en) 1991-04-17
GB2236881B true GB2236881B (en) 1994-01-12

Family

ID=23663314

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9011972A Expired - Fee Related GB2236881B (en) 1989-10-11 1990-05-29 Improved synapse cell employing dual gate transistor structure

Country Status (3)

Country Link
JP (1) JPH03174679A (en)
DE (1) DE4032178A1 (en)
GB (1) GB2236881B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212541A (en) * 1991-04-18 1993-05-18 National Semiconductor Corporation Contactless, 5v, high speed eprom/flash eprom array utilizing cells programmed using source side injection
US7657496B2 (en) * 2006-06-26 2010-02-02 Saffron Technology, Inc. Nonlinear associative memories using linear arrays of associative memory cells, and methods of operating same
JP6833873B2 (en) * 2016-05-17 2021-02-24 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． Deep learning neural network classifier using non-volatile memory array
US11087207B2 (en) * 2018-03-14 2021-08-10 Silicon Storage Technology, Inc. Decoders for analog neural memory in deep learning artificial neural network
US11270763B2 (en) * 2019-01-18 2022-03-08 Silicon Storage Technology, Inc. Neural network classifier using array of three-gate non-volatile memory cells
EP3918532B1 (en) * 2019-01-29 2023-01-25 Silicon Storage Technology, Inc. Neural network classifier using array of four-gate non-volatile memory cells

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0138439A2 (en) * 1983-09-28 1985-04-24 Kabushiki Kaisha Toshiba Electrically erasable programable nonvolatile semiconductor memory device having dual-control gate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0138439A2 (en) * 1983-09-28 1985-04-24 Kabushiki Kaisha Toshiba Electrically erasable programable nonvolatile semiconductor memory device having dual-control gate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE Transactions on Electronic Devices, Vol ED-32(9), Sept 1985, pp 1776-1780; K Hieda et al. *

Also Published As

Publication number Publication date
DE4032178A1 (en) 1991-04-18
GB9011972D0 (en) 1990-07-18
GB2236881A (en) 1991-04-17
JPH03174679A (en) 1991-07-29

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20080529