IT1213241B - Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura. - Google Patents

Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura.

Info

Publication number
IT1213241B
IT1213241B IT8423479A IT2347984A IT1213241B IT 1213241 B IT1213241 B IT 1213241B IT 8423479 A IT8423479 A IT 8423479A IT 2347984 A IT2347984 A IT 2347984A IT 1213241 B IT1213241 B IT 1213241B
Authority
IT
Italy
Prior art keywords
symetric
mos
writing method
eprom memory
memory matrix
Prior art date
Application number
IT8423479A
Other languages
English (en)
Other versions
IT8423479A0 (it
Inventor
Giuseppe Corda
Andrea Ravaglia
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Priority to IT8423479A priority Critical patent/IT1213241B/it
Publication of IT8423479A0 publication Critical patent/IT8423479A0/it
Priority to US06/783,650 priority patent/US4792925A/en
Priority to GB08526482A priority patent/GB2166591B/en
Priority to DE3539234A priority patent/DE3539234C2/de
Priority to FR8516513A priority patent/FR2572836B1/fr
Priority to JP24815385A priority patent/JP2523275B2/ja
Priority to NL8503054A priority patent/NL193296C/nl
Application granted granted Critical
Publication of IT1213241B publication Critical patent/IT1213241B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
IT8423479A 1984-11-07 1984-11-07 Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura. IT1213241B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT8423479A IT1213241B (it) 1984-11-07 1984-11-07 Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura.
US06/783,650 US4792925A (en) 1984-11-07 1985-10-03 Eprom memory matrix with symmetrical elementary MOS cells and writing method therefor
GB08526482A GB2166591B (en) 1984-11-07 1985-10-28 Eprom memory matrix
DE3539234A DE3539234C2 (de) 1984-11-07 1985-11-05 EPROM Speichermatrix mit symmetrischen Elementar-MOS-Zellen und Verfahren zum Einschreiben in den Speicher
FR8516513A FR2572836B1 (fr) 1984-11-07 1985-11-07 Matrice de memoire morte electriquement programmable a cellules elementaires metal-oxyde-semi-conducteur symetriques et procede d'ecriture de cette matrice
JP24815385A JP2523275B2 (ja) 1984-11-07 1985-11-07 Ｅｐｒｏｍメモリマトリクス及びそれへの書込み方法
NL8503054A NL193296C (nl) 1984-11-07 1985-11-07 EPROM-geheugenmatrix met symmetrische elementaire MOS-cellen.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8423479A IT1213241B (it) 1984-11-07 1984-11-07 Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura.

Publications (2)

Publication Number Publication Date
IT8423479A0 IT8423479A0 (it) 1984-11-07
IT1213241B true IT1213241B (it) 1989-12-14

Family

ID=11207465

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8423479A IT1213241B (it) 1984-11-07 1984-11-07 Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura.

Country Status (7)

Country Link
US (1) US4792925A (it)
JP (1) JP2523275B2 (it)
DE (1) DE3539234C2 (it)
FR (1) FR2572836B1 (it)
GB (1) GB2166591B (it)
IT (1) IT1213241B (it)
NL (1) NL193296C (it)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1215380B (it) * 1987-03-12 1990-02-08 Sgs Microelettronica Spa Cella di memoria eprom a due semicelle simmetriche con gate flottante separata.
IT1217403B (it) * 1988-04-12 1990-03-22 Sgs Thomson Microelectronics Matrice di memoria a tovaglia con celle eprom sfalsate
IT1226556B (it) * 1988-07-29 1991-01-24 Sgs Thomson Microelectronics Matrice a tovaglia di celle di memoria eprom singolarmente accessibili mediante decodifica tradizionale.
IT1227989B (it) * 1988-12-05 1991-05-20 Sgs Thomson Microelectronics Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione
US5296396A (en) * 1988-12-05 1994-03-22 Sgs-Thomson Microelectronics S.R.L. Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture
IT1229131B (it) * 1989-03-09 1991-07-22 Sgs Thomson Microelectronics Matrice di memoria eprom con struttura a tovaglia e procedimento per la sua fabbricazione.
IT1235690B (it) * 1989-04-07 1992-09-21 Sgs Thomson Microelectronics Procedimento di fabbricazione per una matrice di celle eprom organizzate a tovaglia.
IT1229168B (it) * 1989-04-10 1991-07-22 Sgs Thomson Microelecyronics S Cella di memoria uprom con struttura compatibile con la fabbricazione di matrici di celle eprom a tovaglia con linee di source e drain autoallineate, e processo per la sua fabbricazione
IT1236601B (it) * 1989-12-22 1993-03-18 Sgs Thomson Microelectronics Dispositivo a semiconduttore integrato di tipo eprom con connessioni metalliche di source e procedimento per la sua fabbricazione.
US5122985A (en) * 1990-04-16 1992-06-16 Giovani Santin Circuit and method for erasing eeprom memory arrays to prevent over-erased cells
JP3002309B2 (ja) * 1990-11-13 2000-01-24 ウエハスケール インテグレーション， インコーポレイテッド 高速ｅｐｒｏｍアレイ
US5289423A (en) * 1990-11-16 1994-02-22 Sgs-Thomson Microelectronics S.R.L. Bank erasable, flash-EPROM memory
IT1247655B (it) * 1990-11-29 1994-12-28 Sgs Thomson Microelettronics Memoria flash eprom cancellabile per blocchi di celle mediante interruzione delle linee di connessione source e collegamenti attraverso linee ortogonali ausiliarie di interconnessione source in metal 1 ed incroci in poly 2 per la continuita' delle bit lines
IT1247654B (it) * 1990-11-16 1994-12-28 Sgs Thomson Microelectronics Memoria flash eprom cancellabile per gruppi di celle mediante doppia mmetal
US5618742A (en) * 1992-01-22 1997-04-08 Macronix Internatioal, Ltd. Method of making flash EPROM with conductive sidewall spacer contacting floating gate
DE69231356T2 (de) * 1992-01-22 2000-12-28 Macronix International Co. Ltd., Hsinchu Nichtflüchtige Speicherzelle und Anordnungsarchitektur
US5526307A (en) * 1992-01-22 1996-06-11 Macronix International Co., Ltd. Flash EPROM integrated circuit architecture
JP3474614B2 (ja) * 1993-12-14 2003-12-08 マクロニクス インターナショナル カンパニイ リミテッド 不揮発性半導体メモリ装置及びその動作方法
EP0830684B1 (en) * 1995-06-07 2004-08-25 Macronix International Co., Ltd. Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width
EP0957521A1 (en) 1998-05-11 1999-11-17 STMicroelectronics S.r.l. Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process
KR20010085722A (ko) * 2000-02-29 2001-09-07 추후제출 반도체 물질상에서의 선택적인 레이저 어닐
JP2007220218A (ja) * 2006-02-17 2007-08-30 Fujitsu Ltd 半導体記憶装置およびその制御方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151021A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM
US4258466A (en) * 1978-11-02 1981-03-31 Texas Instruments Incorporated High density electrically programmable ROM
US4282446A (en) * 1979-10-01 1981-08-04 Texas Instruments Incorporated High density floating gate EPROM programmable by charge storage
US4384349A (en) * 1979-10-01 1983-05-17 Texas Instruments Incorporated High density electrically erasable floating gate dual-injection programmable memory device
JPS56108259A (en) * 1980-02-01 1981-08-27 Hitachi Ltd Semiconductor memory device
JPS5771587A (en) * 1980-10-22 1982-05-04 Toshiba Corp Semiconductor storing device
JPS57186289A (en) * 1981-05-13 1982-11-16 Hitachi Ltd Semiconductor memory
JPS57196627A (en) * 1981-05-29 1982-12-02 Hitachi Ltd Electronic circuit device
US4594689A (en) * 1984-09-04 1986-06-10 Motorola, Inc. Circuit for equalizing bit lines in a ROM

Also Published As

Publication number Publication date
GB2166591A (en) 1986-05-08
GB8526482D0 (en) 1985-12-04
NL193296B (nl) 1999-01-04
JPS61120474A (ja) 1986-06-07
JP2523275B2 (ja) 1996-08-07
GB2166591B (en) 1988-02-17
IT8423479A0 (it) 1984-11-07
NL193296C (nl) 1999-05-06
US4792925A (en) 1988-12-20
DE3539234A1 (de) 1986-05-07
NL8503054A (nl) 1986-06-02
FR2572836A1 (fr) 1986-05-09
DE3539234C2 (de) 1998-01-22
FR2572836B1 (fr) 1993-09-17

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129