DE3586493D1 - Nichtfluechtige halbleiterspeicheranordnung. - Google Patents

Nichtfluechtige halbleiterspeicheranordnung.

Info

Publication number
DE3586493D1
DE3586493D1 DE8585116579T DE3586493T DE3586493D1 DE 3586493 D1 DE3586493 D1 DE 3586493D1 DE 8585116579 T DE8585116579 T DE 8585116579T DE 3586493 T DE3586493 T DE 3586493T DE 3586493 D1 DE3586493 D1 DE 3586493D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
volatile semiconductor
memory arrangement
arrangement
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585116579T
Other languages
English (en)
Other versions
DE3586493T2 (de
Inventor
Hiroyuki Kobatake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3586493D1 publication Critical patent/DE3586493D1/de
Publication of DE3586493T2 publication Critical patent/DE3586493T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
DE8585116579T 1984-12-28 1985-12-27 Nichtfluechtige halbleiterspeicheranordnung. Expired - Fee Related DE3586493T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27743684 1984-12-28

Publications (2)

Publication Number Publication Date
DE3586493D1 true DE3586493D1 (de) 1992-09-17
DE3586493T2 DE3586493T2 (de) 1993-01-14

Family

ID=17583534

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585116579T Expired - Fee Related DE3586493T2 (de) 1984-12-28 1985-12-27 Nichtfluechtige halbleiterspeicheranordnung.

Country Status (4)

Country Link
US (1) US4924438A (de)
EP (1) EP0189594B1 (de)
JP (1) JPH0762960B2 (de)
DE (1) DE3586493T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5296396A (en) * 1988-12-05 1994-03-22 Sgs-Thomson Microelectronics S.R.L. Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture
IT1227989B (it) * 1988-12-05 1991-05-20 Sgs Thomson Microelectronics Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione
US5097444A (en) * 1989-11-29 1992-03-17 Rohm Corporation Tunnel EEPROM with overerase protection
JP2595781B2 (ja) * 1990-07-13 1997-04-02 日本電気株式会社 半導体記憶装置
JP3020355B2 (ja) * 1992-08-03 2000-03-15 シャープ株式会社 不揮発性メモリ及びその書き込み方法
KR950013342B1 (ko) * 1992-10-06 1995-11-02 삼성전자주식회사 반도체 메모리장치의 결함구제회로
KR960014973B1 (ko) * 1992-12-28 1996-10-23 삼성전자 주식회사 반도체 메모리장치
US5506816A (en) * 1994-09-06 1996-04-09 Nvx Corporation Memory cell array having compact word line arrangement
US8064255B2 (en) * 2007-12-31 2011-11-22 Cypress Semiconductor Corporation Architecture of a nvDRAM array and its sense regime
US8059458B2 (en) * 2007-12-31 2011-11-15 Cypress Semiconductor Corporation 3T high density nvDRAM cell
TWI634743B (zh) * 2017-08-18 2018-09-01 瑞昱半導體股份有限公司 可降低寄生電容大小變化程度的開關電路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909808A (en) * 1974-12-23 1975-09-30 Ibm Minimum pitch mosfet decoder circuit configuration
GB2049327B (en) * 1979-05-14 1983-03-30 Fairchild Camera Instr Co Memory read voltage circuitry for adapting eproms to circuits employing substrate bias voltage
JPS5831677B2 (ja) * 1979-11-26 1983-07-07 富士通株式会社 半導体記億装置
US4533934A (en) * 1980-10-02 1985-08-06 Westinghouse Electric Corp. Device structures for high density integrated circuits
GB2094086B (en) * 1981-03-03 1985-08-14 Tokyo Shibaura Electric Co Non-volatile semiconductor memory system
JPS57192067A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Erasable and programmable read only memory unit
US4511811A (en) * 1982-02-08 1985-04-16 Seeq Technology, Inc. Charge pump for providing programming voltage to the word lines in a semiconductor memory array
JPS5952497A (ja) * 1982-09-17 1984-03-27 Nec Corp デコ−ダ回路
JPS60143500A (ja) * 1983-12-29 1985-07-29 Fujitsu Ltd プログラマブル半導体記憶装置

Also Published As

Publication number Publication date
EP0189594A3 (en) 1988-12-07
JPH0762960B2 (ja) 1995-07-05
DE3586493T2 (de) 1993-01-14
US4924438A (en) 1990-05-08
EP0189594B1 (de) 1992-08-12
JPS61267997A (ja) 1986-11-27
EP0189594A2 (de) 1986-08-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee