IT1213228B - Metodo di scrittura per matrice di celle di memoria non volatile di tipo merged. - Google Patents

Metodo di scrittura per matrice di celle di memoria non volatile di tipo merged.

Info

Publication number
IT1213228B
IT1213228B IT8423281A IT2328184A IT1213228B IT 1213228 B IT1213228 B IT 1213228B IT 8423281 A IT8423281 A IT 8423281A IT 2328184 A IT2328184 A IT 2328184A IT 1213228 B IT1213228 B IT 1213228B
Authority
IT
Italy
Prior art keywords
memory cell
volatile memory
writing method
cell matrix
merged non
Prior art date
Application number
IT8423281A
Other languages
English (en)
Other versions
IT8423281A0 (it
Inventor
Andrea Ravaglia
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Priority to IT8423281A priority Critical patent/IT1213228B/it
Publication of IT8423281A0 publication Critical patent/IT8423281A0/it
Priority to GB08524039A priority patent/GB2166019B/en
Priority to NL8502731A priority patent/NL8502731A/nl
Priority to DE19853537046 priority patent/DE3537046A1/de
Priority to JP60234659A priority patent/JPS6199997A/ja
Priority to FR858515758A priority patent/FR2572212B1/fr
Application granted granted Critical
Publication of IT1213228B publication Critical patent/IT1213228B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
IT8423281A 1984-10-23 1984-10-23 Metodo di scrittura per matrice di celle di memoria non volatile di tipo merged. IT1213228B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT8423281A IT1213228B (it) 1984-10-23 1984-10-23 Metodo di scrittura per matrice di celle di memoria non volatile di tipo merged.
GB08524039A GB2166019B (en) 1984-10-23 1985-09-30 Merged nonvolatile memory cell matrix writing method
NL8502731A NL8502731A (nl) 1984-10-23 1985-10-07 Werkwijze voor het registreren van een niet-vluchtige versmolten geheugencelmatrix.
DE19853537046 DE3537046A1 (de) 1984-10-23 1985-10-17 Schreibverfahren fuer eine matrix aus fusionierten nichtfluechtigen speicherzellen
JP60234659A JPS6199997A (ja) 1984-10-23 1985-10-22 併合型不揮発性メモリセルマトリツクの書込み方法
FR858515758A FR2572212B1 (fr) 1984-10-23 1985-10-23 Procede d'ecriture pour matrices de cellules de memoire permanente de type " merged " (ou fusionne)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8423281A IT1213228B (it) 1984-10-23 1984-10-23 Metodo di scrittura per matrice di celle di memoria non volatile di tipo merged.

Publications (2)

Publication Number Publication Date
IT8423281A0 IT8423281A0 (it) 1984-10-23
IT1213228B true IT1213228B (it) 1989-12-14

Family

ID=11205614

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8423281A IT1213228B (it) 1984-10-23 1984-10-23 Metodo di scrittura per matrice di celle di memoria non volatile di tipo merged.

Country Status (6)

Country Link
JP (1) JPS6199997A (it)
DE (1) DE3537046A1 (it)
FR (1) FR2572212B1 (it)
GB (1) GB2166019B (it)
IT (1) IT1213228B (it)
NL (1) NL8502731A (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783766A (en) * 1986-05-30 1988-11-08 Seeq Technology, Inc. Block electrically erasable EEPROM
JPH0770233B2 (ja) * 1987-07-15 1995-07-31 三菱電機株式会社 不揮発性半導体記憶装置の書込および消去方法
JPS6439694A (en) * 1987-08-05 1989-02-09 Mitsubishi Electric Corp Non-volatile semiconductor memory device
JPH01289170A (ja) * 1988-05-16 1989-11-21 Toshiba Corp 不揮発性半導体記憶装置
JP2732070B2 (ja) * 1988-07-12 1998-03-25 三菱電機株式会社 不揮発性半導体記憶装置の書込み方法
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4377857A (en) * 1980-11-18 1983-03-22 Fairchild Camera & Instrument Electrically erasable programmable read-only memory
DE3279855D1 (en) * 1981-12-29 1989-09-07 Fujitsu Ltd Nonvolatile semiconductor memory circuit

Also Published As

Publication number Publication date
GB2166019B (en) 1988-06-02
IT8423281A0 (it) 1984-10-23
FR2572212B1 (fr) 1989-05-19
DE3537046A1 (de) 1986-04-24
GB2166019A (en) 1986-04-23
FR2572212A1 (fr) 1986-04-25
JPS6199997A (ja) 1986-05-19
NL8502731A (nl) 1986-05-16
GB8524039D0 (en) 1985-11-06

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Effective date: 19971030