JPS6439694A - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device

Info

Publication number
JPS6439694A
JPS6439694A JP19682587A JP19682587A JPS6439694A JP S6439694 A JPS6439694 A JP S6439694A JP 19682587 A JP19682587 A JP 19682587A JP 19682587 A JP19682587 A JP 19682587A JP S6439694 A JPS6439694 A JP S6439694A
Authority
JP
Japan
Prior art keywords
erasure
write
voltage
memory cell
floating gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19682587A
Other languages
Japanese (ja)
Inventor
Takeshi Nakayama
Kazuo Kobayashi
Yasushi Terada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP19682587A priority Critical patent/JPS6439694A/en
Priority to US07/156,431 priority patent/US4903236A/en
Publication of JPS6439694A publication Critical patent/JPS6439694A/en
Pending legal-status Critical Current

Links

Landscapes

  • Read Only Memory (AREA)

Abstract

PURPOSE:To operate a device only by an internal power source without necessitating an external high voltage, to miniaturize the device, and to lower cost, by performing an erasure and write operation by utilizing a tunnel phenomenon by providing an erasure and write voltage impression means. CONSTITUTION:In a memory cell array 20, a plural memory cells MC are arranged in a matrix shape. Plural bit lines BL and word lines WL are arranged intersecting orthogonally, and the memory cell MC is arranged on respective intersection. The erasure operation is performed in such a way that an erasing state can be obtained by applying a prescribed voltage between the bit line and the word line, generating the tunnel phenomenon between the drain areas of all memory cells and floating gates, and injecting electrons in the floating gates. The write operation is performed in such a way that a write state can be obtained by generating the tunnel phenomenon by applying a voltage between the bit line and the word line of only a selected one memory cell, and extracting the electrons in the floating gates. Thus, it is possible to miniaturize the device, to lower the cost, and to increase the number of times of the erasure and the write.
JP19682587A 1987-07-15 1987-08-05 Non-volatile semiconductor memory device Pending JPS6439694A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP19682587A JPS6439694A (en) 1987-08-05 1987-08-05 Non-volatile semiconductor memory device
US07/156,431 US4903236A (en) 1987-07-15 1988-02-16 Nonvolatile semiconductor memory device and a writing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19682587A JPS6439694A (en) 1987-08-05 1987-08-05 Non-volatile semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS6439694A true JPS6439694A (en) 1989-02-09

Family

ID=16364291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19682587A Pending JPS6439694A (en) 1987-07-15 1987-08-05 Non-volatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS6439694A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005560A1 (en) * 1990-09-25 1992-04-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
KR100495634B1 (en) * 1997-09-02 2005-09-02 소니 가부시끼 가이샤 Nonvolatile semiconductor memory device and its writing and erasing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115691A (en) * 1981-12-28 1983-07-09 ヒユ−ズ・エアクラフト・カンパニ− Programmable read only memory cell electrically erasable with single transistor
JPS6199997A (en) * 1984-10-23 1986-05-19 エツセジーエツセ　ミクロエレツトロニカ Writing for merged type non-volatile memory matrix

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115691A (en) * 1981-12-28 1983-07-09 ヒユ−ズ・エアクラフト・カンパニ− Programmable read only memory cell electrically erasable with single transistor
JPS6199997A (en) * 1984-10-23 1986-05-19 エツセジーエツセ　ミクロエレツトロニカ Writing for merged type non-volatile memory matrix

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005560A1 (en) * 1990-09-25 1992-04-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
KR100495634B1 (en) * 1997-09-02 2005-09-02 소니 가부시끼 가이샤 Nonvolatile semiconductor memory device and its writing and erasing method

Similar Documents

Publication Publication Date Title
US5717635A (en) High density EEPROM for solid state file
KR900006318B1 (en) Gate array intergrated circuit device and method thereof for various bit-word construstions
KR950006867A (en) Independent Array Ground for Flash EPIROM Arrays with Page Erase Structures
TW275715B (en) Non-volatile sidewall memory cell method of fabricating same
EP0052566A3 (en) Electrically erasable programmable read-only memory
EP0318952A3 (en) Semiconductor memory device having a function of simultaneously clearing part of memory date
US4336603A (en) Three terminal electrically erasable programmable read only memory
JPS648593A (en) Semiconductor storage device
TW329519B (en) The non-volatile semiconductor memory device
TW328179B (en) Non-volatile semiconductor memory device
TW347537B (en) Method of programming and reading data in a nonvolatile semiconductor memory device and circuit therefor
JPS6432494A (en) Non-volatile semiconductor storage device
EP0083194A3 (en) Electrically erasable programmable read only memory cell having a single transistor
TW335549B (en) Nand-type flash memory device and driving method thereof
Onoda et al. A novel cell structure suitable for a 3 volt operation, sector erase flash memory
JPS6425394A (en) Nonvolatile semiconductor memory device
EP0361972A3 (en) Non-volatile semiconductor memory device with nand type memory cell arrays
EP0337433A3 (en) Cell array pattern layout of semiconductor memory device
RU2000125741A (en) PAGE Erase Mode in the Flash Memory Matrix
KR960006048A (en) Semiconductor Nonvolatile Memory
TW343336B (en) Semiconductor memory with different block sizes and requiring erasing operation
EP0306990A3 (en) Semiconductor memory device with dummy cell array
JPH0869696A (en) Semiconductor storage
JPS6439694A (en) Non-volatile semiconductor memory device
TW342499B (en) A data writing circuit for a nonvolatile semiconductor memory