DE69014356D1 - Tischtuchmatrix von EPROM-Speicherzellen mit einer asymmetrischen Leitplatte. - Google Patents

Tischtuchmatrix von EPROM-Speicherzellen mit einer asymmetrischen Leitplatte.

Info

Publication number
DE69014356D1
DE69014356D1 DE69014356T DE69014356T DE69014356D1 DE 69014356 D1 DE69014356 D1 DE 69014356D1 DE 69014356 T DE69014356 T DE 69014356T DE 69014356 T DE69014356 T DE 69014356T DE 69014356 D1 DE69014356 D1 DE 69014356D1
Authority
DE
Germany
Prior art keywords
tablecloth
matrix
guide plate
memory cells
eprom memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69014356T
Other languages
English (en)
Other versions
DE69014356T2 (de
Inventor
Stefano Mazzali
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Application granted granted Critical
Publication of DE69014356D1 publication Critical patent/DE69014356D1/de
Publication of DE69014356T2 publication Critical patent/DE69014356T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • H01L29/7884Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885Hot carrier injection from the channel
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE69014356T 1989-03-15 1990-03-05 Tischtuchmatrix von EPROM-Speicherzellen mit einer asymmetrischen Leitplatte. Expired - Fee Related DE69014356T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8919778A IT1228721B (it) 1989-03-15 1989-03-15 Matrice a tovaglia di celle di memoria eprom con aletta asimmetrica.

Publications (2)

Publication Number Publication Date
DE69014356D1 true DE69014356D1 (de) 1995-01-12
DE69014356T2 DE69014356T2 (de) 1995-07-20

Family

ID=11161141

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69014356T Expired - Fee Related DE69014356T2 (de) 1989-03-15 1990-03-05 Tischtuchmatrix von EPROM-Speicherzellen mit einer asymmetrischen Leitplatte.

Country Status (4)

Country Link
EP (1) EP0387935B1 (de)
JP (1) JP2520756B2 (de)
DE (1) DE69014356T2 (de)
IT (1) IT1228721B (de)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258466A (en) * 1978-11-02 1981-03-31 Texas Instruments Incorporated High density electrically programmable ROM

Also Published As

Publication number Publication date
EP0387935B1 (de) 1994-11-30
JPH02292861A (ja) 1990-12-04
JP2520756B2 (ja) 1996-07-31
DE69014356T2 (de) 1995-07-20
IT1228721B (it) 1991-07-03
EP0387935A1 (de) 1990-09-19
IT8919778A0 (it) 1989-03-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee