DE68921018D1 - EPROM mit 2 Zellen pro bit. - Google Patents

EPROM mit 2 Zellen pro bit.

Info

Publication number
DE68921018D1
DE68921018D1 DE68921018T DE68921018T DE68921018D1 DE 68921018 D1 DE68921018 D1 DE 68921018D1 DE 68921018 T DE68921018 T DE 68921018T DE 68921018 T DE68921018 T DE 68921018T DE 68921018 D1 DE68921018 D1 DE 68921018D1
Authority
DE
Germany
Prior art keywords
eprom
cells per
per bit
bit
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68921018T
Other languages
English (en)
Other versions
DE68921018T2 (de
Inventor
Shigeru Atsumi
Sumio Tanaka
Junichi Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE68921018D1 publication Critical patent/DE68921018D1/de
Application granted granted Critical
Publication of DE68921018T2 publication Critical patent/DE68921018T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE68921018T 1988-04-13 1989-04-11 EPROM mit 2 Zellen pro bit. Expired - Fee Related DE68921018T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9107388A JP2537264B2 (ja) 1988-04-13 1988-04-13 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE68921018D1 true DE68921018D1 (de) 1995-03-23
DE68921018T2 DE68921018T2 (de) 1995-07-06

Family

ID=14016328

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68921018T Expired - Fee Related DE68921018T2 (de) 1988-04-13 1989-04-11 EPROM mit 2 Zellen pro bit.

Country Status (5)

Country Link
US (1) US4970691A (de)
EP (1) EP0337393B1 (de)
JP (1) JP2537264B2 (de)
KR (1) KR920010001B1 (de)
DE (1) DE68921018T2 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2601903B2 (ja) * 1989-04-25 1997-04-23 株式会社東芝 半導体記憶装置
US5237534A (en) * 1989-04-27 1993-08-17 Kabushiki Kaisha Toshiba Data sense circuit for a semiconductor nonvolatile memory device
JPH0679440B2 (ja) * 1990-03-22 1994-10-05 株式会社東芝 不揮発性半導体記憶装置
US5291045A (en) * 1991-03-29 1994-03-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device using a differential cell in a memory cell
US5497475A (en) * 1993-02-05 1996-03-05 National Semiconductor Corporation Configurable integrated circuit having true and shadow EPROM registers
DE69326154T2 (de) * 1993-11-30 2000-02-24 Stmicroelectronics S.R.L., Agrate Brianza Integrierte Schaltung für die Programmierung einer Speicherzelle eines nicht flüchtigen Speicherregisters
US5486785A (en) * 1994-09-30 1996-01-23 Mitsubishi Semiconductor America, Inc. CMOS level shifter with feedforward control to prevent latching in a wrong logic state
GB9423032D0 (en) * 1994-11-15 1995-01-04 Sgs Thomson Microelectronics Bit line sensing in a memory array
US6330186B2 (en) * 1996-02-19 2001-12-11 Citizen Watch Co, Ltd. Non-volatile semiconductor memory device having electrically programable memory matrix array
US5819305A (en) * 1996-08-23 1998-10-06 Motorola, Inc. Method and apparatus for configuring operating modes in a memory
US5907855A (en) * 1996-10-15 1999-05-25 Micron Technology, Inc. Apparatus and method for reducing programming cycles for multistate memory system
US6728825B1 (en) 1996-10-15 2004-04-27 Micron Technology, Inc. Apparatus and method for reducing programming cycles for multistate memory system
US6493269B1 (en) * 2001-05-31 2002-12-10 Sandisk Corporation Dual cell reading and writing technique
US6788574B1 (en) 2001-12-06 2004-09-07 Virage Logic Corporation Electrically-alterable non-volatile memory cell
US7130213B1 (en) * 2001-12-06 2006-10-31 Virage Logic Corporation Methods and apparatuses for a dual-polarity non-volatile memory cell
US6842375B1 (en) 2001-12-06 2005-01-11 Virage Logic Corporation Methods and apparatuses for maintaining information stored in a non-volatile memory cell
US6850446B1 (en) 2001-12-06 2005-02-01 Virage Logic Corporation Memory cell sensing with low noise generation
US6992938B1 (en) 2001-12-06 2006-01-31 Virage Logic Corporation Methods and apparatuses for test circuitry for a dual-polarity non-volatile memory cell
US7400522B2 (en) 2003-03-18 2008-07-15 Kabushiki Kaisha Toshiba Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation
US7778062B2 (en) 2003-03-18 2010-08-17 Kabushiki Kaisha Toshiba Resistance change memory device
US7394680B2 (en) 2003-03-18 2008-07-01 Kabushiki Kaisha Toshiba Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode
JP4377817B2 (ja) 2003-03-18 2009-12-02 株式会社東芝 プログラマブル抵抗メモリ装置
JP4278438B2 (ja) * 2003-05-27 2009-06-17 三洋電機株式会社 不揮発性半導体記憶装置及びその制御方法
KR100617419B1 (ko) 2003-12-19 2006-08-30 오티스 엘리베이터 컴파니 저소음 체인이상감지장치
JP2005209311A (ja) * 2004-01-26 2005-08-04 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP4860160B2 (ja) * 2004-02-10 2012-01-25 株式会社半導体エネルギー研究所 半導体装置
JP4467371B2 (ja) 2004-07-14 2010-05-26 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の置換情報の設定方法
JP5311784B2 (ja) 2006-10-11 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
JP2008210467A (ja) * 2007-02-27 2008-09-11 Nec Electronics Corp 不揮発性半導体メモリ及びそのテスト方法
JP4504397B2 (ja) * 2007-05-29 2010-07-14 株式会社東芝 半導体記憶装置
US7692951B2 (en) 2007-06-12 2010-04-06 Kabushiki Kaisha Toshiba Resistance change memory device with a variable resistance element formed of a first and a second composite compound
DE102007030842B4 (de) * 2007-07-03 2015-05-21 Austriamicrosystems Ag Speicheranordnung und Verfahren zum Speichern
JP2009199675A (ja) 2008-02-22 2009-09-03 Seiko Instruments Inc 不揮発性半導体記憶装置
JP2009272028A (ja) * 2008-04-07 2009-11-19 Renesas Technology Corp 半導体集積回路およびその動作方法
JP2010187047A (ja) 2009-02-10 2010-08-26 Renesas Electronics Corp テスト回路、及びテスト方法
JP2010211894A (ja) 2009-03-12 2010-09-24 Renesas Electronics Corp 差動センスアンプ
JP5333302B2 (ja) * 2010-03-12 2013-11-06 セイコーエプソン株式会社 不揮発性記憶装置、集積回路装置及び電子機器
JP6400547B2 (ja) * 2015-09-14 2018-10-03 東芝メモリ株式会社 メモリデバイス
US10090027B2 (en) * 2016-05-25 2018-10-02 Ememory Technology Inc. Memory system with low read power

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4543500A (en) * 1978-09-22 1985-09-24 Texas Instruments Incorporated High performance dynamic sense amplifier voltage boost for row address lines
JPS59132492A (ja) * 1982-12-22 1984-07-30 Fujitsu Ltd 半導体記憶装置
US4612630A (en) * 1984-07-27 1986-09-16 Harris Corporation EEPROM margin testing design
JPS61222093A (ja) * 1985-03-28 1986-10-02 Toshiba Corp 不揮発性半導体記憶装置
JPS62222498A (ja) * 1986-03-10 1987-09-30 Fujitsu Ltd 消去及び書き込み可能な読み出し専用メモリ

Also Published As

Publication number Publication date
US4970691A (en) 1990-11-13
KR900017273A (ko) 1990-11-15
JPH01263997A (ja) 1989-10-20
EP0337393A2 (de) 1989-10-18
KR920010001B1 (ko) 1992-11-10
EP0337393A3 (de) 1992-03-11
JP2537264B2 (ja) 1996-09-25
EP0337393B1 (de) 1995-02-08
DE68921018T2 (de) 1995-07-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee