IT1228864B - Processo di planarizzazione per matrici di celle di memoria eprom a tovaglia e semitovaglia. - Google Patents

Processo di planarizzazione per matrici di celle di memoria eprom a tovaglia e semitovaglia.

Info

Publication number
IT1228864B
IT1228864B IT8919884A IT1988489A IT1228864B IT 1228864 B IT1228864 B IT 1228864B IT 8919884 A IT8919884 A IT 8919884A IT 1988489 A IT1988489 A IT 1988489A IT 1228864 B IT1228864 B IT 1228864B
Authority
IT
Italy
Prior art keywords
tablecloth
semi
memory cell
planarization process
eprom memory
Prior art date
Application number
IT8919884A
Other languages
English (en)
Other versions
IT8919884A0 (it
Inventor
Luisa Masini
Mario Sali
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8919884A priority Critical patent/IT1228864B/it
Publication of IT8919884A0 publication Critical patent/IT8919884A0/it
Priority to EP19900200555 priority patent/EP0389028A3/en
Priority to JP2068500A priority patent/JPH02292862A/ja
Application granted granted Critical
Publication of IT1228864B publication Critical patent/IT1228864B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT8919884A 1989-03-23 1989-03-23 Processo di planarizzazione per matrici di celle di memoria eprom a tovaglia e semitovaglia. IT1228864B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT8919884A IT1228864B (it) 1989-03-23 1989-03-23 Processo di planarizzazione per matrici di celle di memoria eprom a tovaglia e semitovaglia.
EP19900200555 EP0389028A3 (en) 1989-03-23 1990-03-09 Planarization process for eprom memory cell matrices with a table cloth and a half table cloth structure
JP2068500A JPH02292862A (ja) 1989-03-23 1990-03-20 テーブルクロス型および半テーブルクロス型構造を有するｅｐｒｏｍメモリセルマトリックスの平坦化方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8919884A IT1228864B (it) 1989-03-23 1989-03-23 Processo di planarizzazione per matrici di celle di memoria eprom a tovaglia e semitovaglia.

Publications (2)

Publication Number Publication Date
IT8919884A0 IT8919884A0 (it) 1989-03-23
IT1228864B true IT1228864B (it) 1991-07-05

Family

ID=11162055

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8919884A IT1228864B (it) 1989-03-23 1989-03-23 Processo di planarizzazione per matrici di celle di memoria eprom a tovaglia e semitovaglia.

Country Status (3)

Country Link
EP (1) EP0389028A3 (it)
JP (1) JPH02292862A (it)
IT (1) IT1228864B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0851470A1 (en) * 1996-12-24 1998-07-01 STMicroelectronics S.r.l. Process for deposing a stratified dielectric for enhancing the planarity of semiconductor electronic devices

Also Published As

Publication number Publication date
EP0389028A2 (en) 1990-09-26
IT8919884A0 (it) 1989-03-23
JPH02292862A (ja) 1990-12-04
EP0389028A3 (en) 1990-10-31

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970329