IT8822848A0 - Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione - Google Patents

Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione

Info

Publication number
IT8822848A0
IT8822848A0 IT8822848A IT2284888A IT8822848A0 IT 8822848 A0 IT8822848 A0 IT 8822848A0 IT 8822848 A IT8822848 A IT 8822848A IT 2284888 A IT2284888 A IT 2284888A IT 8822848 A0 IT8822848 A0 IT 8822848A0
Authority
IT
Italy
Prior art keywords
manufacturing
memory cell
eprom memory
cell matrix
improved capacitive
Prior art date
Application number
IT8822848A
Other languages
English (en)
Other versions
IT1227989B (it
Inventor
Orio Bellezza
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8822848A priority Critical patent/IT1227989B/it
Publication of IT8822848A0 publication Critical patent/IT8822848A0/it
Priority to EP89202987A priority patent/EP0372614B1/en
Priority to DE68923067T priority patent/DE68923067T2/de
Priority to JP1313555A priority patent/JP2696411B2/ja
Application granted granted Critical
Publication of IT1227989B publication Critical patent/IT1227989B/it
Priority to US07/759,203 priority patent/US5160986A/en
Priority to US07/929,418 priority patent/US5296396A/en
Priority to US08/191,667 priority patent/US5475250A/en
Priority to US08/521,469 priority patent/US5723351A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
IT8822848A 1988-12-05 1988-12-05 Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione IT1227989B (it)

Priority Applications (8)

Application Number Priority Date Filing Date Title
IT8822848A IT1227989B (it) 1988-12-05 1988-12-05 Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione
EP89202987A EP0372614B1 (en) 1988-12-05 1989-11-24 Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture
DE68923067T DE68923067T2 (de) 1988-12-05 1989-11-24 EPROM-Speichermatrix mit netzartiger Struktur, mit verbessertem kapazitiven Verhalten und Verfahren zu deren Herstellung.
JP1313555A JP2696411B2 (ja) 1988-12-05 1989-12-04 Ｅｐｒｏｍ記憶セルのマトリックス構造を製造する方法
US07/759,203 US5160986A (en) 1988-12-05 1991-09-11 Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture
US07/929,418 US5296396A (en) 1988-12-05 1992-08-14 Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture
US08/191,667 US5475250A (en) 1988-12-05 1994-02-04 Matrix of EPROM memory cells with a tablecloth structure having an improved capacitive ratio and a process for its manufacture
US08/521,469 US5723351A (en) 1988-12-05 1995-08-30 Method of making matrix of EPROM memory cell with a tablecloth structure having an improved capacitative ratio

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8822848A IT1227989B (it) 1988-12-05 1988-12-05 Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione

Publications (2)

Publication Number Publication Date
IT8822848A0 true IT8822848A0 (it) 1988-12-05
IT1227989B IT1227989B (it) 1991-05-20

Family

ID=11201126

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8822848A IT1227989B (it) 1988-12-05 1988-12-05 Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione

Country Status (5)

Country Link
US (1) US5160986A (it)
EP (1) EP0372614B1 (it)
JP (1) JP2696411B2 (it)
DE (1) DE68923067T2 (it)
IT (1) IT1227989B (it)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1236601B (it) * 1989-12-22 1993-03-18 Sgs Thomson Microelectronics Dispositivo a semiconduttore integrato di tipo eprom con connessioni metalliche di source e procedimento per la sua fabbricazione.
US5364806A (en) * 1991-08-29 1994-11-15 Hyundai Electronics Industries Co., Ltd. Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell
KR950002948B1 (ko) * 1991-10-10 1995-03-28 삼성전자 주식회사 반도체 장치의 금속층간 절연막 형성방법
US5470772A (en) * 1991-11-06 1995-11-28 Intel Corporation Silicidation method for contactless EPROM related devices
US5272117A (en) * 1992-12-07 1993-12-21 Motorola, Inc. Method for planarizing a layer of material
US5427967A (en) * 1993-03-11 1995-06-27 National Semiconductor Corporation Technique for making memory cells in a way which suppresses electrically conductive stringers
TW299475B (it) * 1993-03-30 1997-03-01 Siemens Ag
US5543343A (en) * 1993-12-22 1996-08-06 Sgs-Thomson Microelectronics, Inc. Method fabricating an integrated circuit
US5650960A (en) * 1994-05-18 1997-07-22 United Microelectronics Corporation Polysilicon programming memory cell
EP0957521A1 (en) 1998-05-11 1999-11-17 STMicroelectronics S.r.l. Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process
US6936883B2 (en) * 2003-04-07 2005-08-30 Silicon Storage Technology, Inc. Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation
US7190018B2 (en) 2003-04-07 2007-03-13 Silicon Storage Technology, Inc. Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation
TW200601461A (en) * 2004-03-09 2006-01-01 Silicon Storage Tech Inc Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation
US20070166903A1 (en) * 2006-01-17 2007-07-19 Bohumil Lojek Semiconductor structures formed by stepperless manufacturing
US20070166971A1 (en) * 2006-01-17 2007-07-19 Atmel Corporation Manufacturing of silicon structures smaller than optical resolution limits

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519851A (en) * 1978-07-31 1980-02-12 Hitachi Ltd Manufacture of non-volatile memories
US4258466A (en) * 1978-11-02 1981-03-31 Texas Instruments Incorporated High density electrically programmable ROM
US4422092A (en) * 1979-09-17 1983-12-20 Texas Instruments Incorporated High coupling ratio electrically programmable ROM
US4334347A (en) * 1979-10-19 1982-06-15 Rca Corporation Method of forming an improved gate member for a gate injected floating gate memory device
US4253106A (en) * 1979-10-19 1981-02-24 Rca Corporation Gate injected floating gate memory device
US4387447A (en) * 1980-02-04 1983-06-07 Texas Instruments Incorporated Column and ground select sequence in electrically programmable memory
JPS5743470A (en) * 1980-08-29 1982-03-11 Fujitsu Ltd Semiconductor device
JPS5836508B2 (ja) * 1980-12-25 1983-08-09 富士通株式会社 半導体装置の製造方法
US4437174A (en) * 1981-01-19 1984-03-13 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4423491A (en) * 1981-11-23 1983-12-27 Fairchild Camera & Instrument Corp. Self-refreshing memory cell
US4490900A (en) * 1982-01-29 1985-01-01 Seeq Technology, Inc. Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein
IT1213241B (it) * 1984-11-07 1989-12-14 Ates Componenti Elettron Matrice di memoria eprom con celle elementari simmetriche mos e suo metodo di scrittura.
US4698787A (en) * 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
JPH0762960B2 (ja) * 1984-12-28 1995-07-05 日本電気株式会社 半導体回路
JPS61222159A (ja) * 1985-01-30 1986-10-02 テキサス　インスツルメンツ　インコ−ポレイテツド 電気的にプログラム可能なメモリ・セル
US4597060A (en) * 1985-05-01 1986-06-24 Texas Instruments Incorporated EPROM array and method for fabricating
JPS62163376A (ja) * 1986-01-14 1987-07-20 Fujitsu Ltd 半導体記憶装置の製造方法
US4855800A (en) * 1986-03-27 1989-08-08 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling
US4749443A (en) * 1986-12-04 1988-06-07 Texas Instruments Incorporated Sidewall oxide to reduce filaments
JPS63160097A (ja) * 1986-12-24 1988-07-02 Toshiba Corp 半導体不揮発性メモリ
US4829351A (en) * 1987-03-16 1989-05-09 Motorola, Inc. Polysilicon pattern for a floating gate memory
US4905062A (en) * 1987-11-19 1990-02-27 Texas Instruments Incorporated Planar famos transistor with trench isolation
JPH0247868A (ja) * 1988-08-10 1990-02-16 Fujitsu Ltd 不揮発性半導体記憶装置
US5023680A (en) * 1988-11-10 1991-06-11 Texas Instruments Incorporated Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates
EP0368097A3 (en) * 1988-11-10 1992-04-29 Texas Instruments Incorporated A cross-point contact-free floating-gate memory array with silicided buried bitlines

Also Published As

Publication number Publication date
EP0372614B1 (en) 1995-06-14
IT1227989B (it) 1991-05-20
JP2696411B2 (ja) 1998-01-14
DE68923067D1 (de) 1995-07-20
US5160986A (en) 1992-11-03
DE68923067T2 (de) 1996-02-22
EP0372614A1 (en) 1990-06-13
JPH02213163A (ja) 1990-08-24

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961227