TW200601461A - Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation - Google Patents

Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation

Info

Publication number
TW200601461A
TW200601461A TW094105237A TW94105237A TW200601461A TW 200601461 A TW200601461 A TW 200601461A TW 094105237 A TW094105237 A TW 094105237A TW 94105237 A TW94105237 A TW 94105237A TW 200601461 A TW200601461 A TW 200601461A
Authority
TW
Taiwan
Prior art keywords
trench
source
floating gate
array
drain
Prior art date
Application number
TW094105237A
Other languages
Chinese (zh)
Inventor
Da-Na Lee
Bo-My Chen
Sohrab Kianian
Original Assignee
Silicon Storage Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/797,296 external-priority patent/US7307308B2/en
Application filed by Silicon Storage Tech Inc filed Critical Silicon Storage Tech Inc
Publication of TW200601461A publication Critical patent/TW200601461A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate. An independently controllable control gate is also in the trench, insulated from the floating gate and is capacitively coupled thereto. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode or from the floating gate to the source/drain region at the bottom wall of the trench. The source, drain and control gates are all substantially parallel to one another, with the gate electrode substantially perpendicular to the source/drain/control gates. The source/drain lines are buried in the substrate, creating a virtual ground array.
TW094105237A 2004-03-09 2005-02-22 Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation TW200601461A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/797,296 US7307308B2 (en) 2003-04-07 2004-03-09 Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation

Publications (1)

Publication Number Publication Date
TW200601461A true TW200601461A (en) 2006-01-01

Family

ID=35085603

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094105237A TW200601461A (en) 2004-03-09 2005-02-22 Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation

Country Status (4)

Country Link
JP (1) JP2005260235A (en)
KR (1) KR20060043534A (en)
CN (1) CN1691336A (en)
TW (1) TW200601461A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9293204B2 (en) * 2013-04-16 2016-03-22 Silicon Storage Technology, Inc. Non-volatile memory cell with self aligned floating and erase gates, and method of making same
CN110010606B (en) * 2018-01-05 2023-04-07 硅存储技术公司 Dual bit non-volatile memory cell with floating gate in substrate trench

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
IT1227989B (en) * 1988-12-05 1991-05-20 Sgs Thomson Microelectronics EPROM MEMORY CELL MATRIX WITH TABLECLOTH STRUCTURE WITH IMPROVED CAPACITIVE RATIO AND PROCESS FOR ITS MANUFACTURE
EP0740854B1 (en) * 1991-08-29 2003-04-23 Hyundai Electronics Industries Co., Ltd. A self-aligned dual-bit split gate (dsg) flash eeprom cell
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
JPH05211338A (en) * 1991-10-09 1993-08-20 Mitsubishi Electric Corp Non-volatile semiconductor device
JP3403877B2 (en) * 1995-10-25 2003-05-06 三菱電機株式会社 Semiconductor memory device and manufacturing method thereof
US5963806A (en) * 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
US6952034B2 (en) * 2002-04-05 2005-10-04 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried source line and floating gate

Also Published As

Publication number Publication date
CN1691336A (en) 2005-11-02
JP2005260235A (en) 2005-09-22
KR20060043534A (en) 2006-05-15

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