CN1691336A - Buried bit line non-volatile floating gate memory cell, and array thereof, and method of formation - Google Patents
Buried bit line non-volatile floating gate memory cell, and array thereof, and method of formation Download PDFInfo
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- CN1691336A CN1691336A CNA2005100550905A CN200510055090A CN1691336A CN 1691336 A CN1691336 A CN 1691336A CN A2005100550905 A CNA2005100550905 A CN A2005100550905A CN 200510055090 A CN200510055090 A CN 200510055090A CN 1691336 A CN1691336 A CN 1691336A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
Abstract
A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate. An independently controllable control gate is also in the trench, insulated from the floating gate and is capacitively coupled thereto. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode or from the floating gate to the source/drain region at the bottom wall of the trench. The source, drain and control gates are all substantially parallel to one another, with the gate electrode substantially perpendicular to the source/drain/control gates.
Description
The sequence number that among the application is submission on April 7th, 2003 is 10/409,407 the part continuation application of awaiting the reply and applying for, described disclosing all is included in herein.
Technical field
The present invention relates to buried bit line read/the program nonvolatile memory cell, it utilizes floating gate to come stored charge, and floating gate is in groove.More particularly, the present invention relates to such nonvolatile memory cell, that is, it has the independent controllable control gate (also in groove) that capacitive is coupled to floating gate, and relates to this cellular array and manufacture method.
Background technology
The floating gate that utilization forms on the plane surface of Semiconductor substrate comes that the reading of stored charge/the program nonvolatile memory cell is in the industry cycle well-known.For example see United States Patent (USP) 5,029,130 and 6,426,896.Usually, the memory cell of each these type all is formed on the horizontal plane of Semiconductor substrate, and involves to inject to the floating gate programming and by polycrystalline by hot electron and eliminate electronics to polycrystalline Fowler-Nordheim tunnel effect from floating gate.Floating gate or stored charge or stored charge not.Be stored in electric charge on the floating gate and controlling the conduction of electric charge in the transistor planar raceway groove.Owing to integrated scale along with semiconducter process increases, just need to improve the density of sort memory spare.
But the increase along with to the demand of the memory that improves density just needs to improve the density of this unit on Semiconductor substrate.
Summary of the invention
In the present invention, make nonvolatile memory cell on the single-crystal semiconductor material basically of first conduction type, described semi-conducting material has the surface on plane basically, and groove is arranged in material surface.Groove has sidewall and diapire.The first area that is different from second conduction type of first conduction type is arranged in the material along plane surface.The second area of second conduction type is arranged in along the material of groove diapire.Channel region has first that is used for conduct charges and the second portion that connects described first area and second area.First is along the surface of contiguous first area, and second portion is along the sidewall in adjacent second zone territory.A kind of medium is on channel region.Floating gate is arranged in groove, and is on the described medium, spaced apart with the second portion of channel region.First grid electrode is on the medium, and is spaced apart with the first of channel region.Second gate electrode is in the groove, and capacitive is coupled to floating gate.
The invention still further relates to the array of above-mentioned nonvolatile memory cell and the method for making nonvolatile memory cell and array.
Description of drawings
Figure 1A is the top view of Semiconductor substrate of first step that is used for the formation isolated area of the inventive method.
Figure 1B is the structural section figure of 1B-1B intercepting along the line, and each initial manufacture step of the present invention is shown.
Fig. 1 C is the top view of described structure, and the next step of Figure 1B structure processing is shown, and forms isolated area in this step.
Fig. 1 D is along the structural section figure of Fig. 1 C center line 1D-1D intercepting, is illustrated in the isolated groove that forms in the described structure.
Fig. 1 E is the sectional view of structure described in Fig. 1 D, and the formation of material spacing block in the isolated groove is described.
Fig. 1 F is the sectional view of structure described in Fig. 1 E, and the final structure of isolated area is shown.
Fig. 2 A-2R is the structural section figure along Fig. 1 F center line 2A-2A intercepting, is illustrated in each step of processing semiconductor structure in the forming process of non-volatile memory array of floating gate memory cell of the present invention successively.
Fig. 3 is the circuit diagram of the signal of memory cell array of the present invention.
Embodiment
Method of the present invention be shown in Figure 1A to 1F and 2A to 2R, they illustrate each procedure of processing of making memory array of the present invention.This method is from substrate 10, and substrate is the P type preferably, and is that industry is known.The thickness of each layer of the following stated depends on design rule and processing technology generative process.Described herein is about 0.10 micron technology.But the professional and technical personnel should understand the present invention and be not limited to any concrete processing technology generative process, also is not limited to any concrete numerical value of any technological parameter of the following stated.
The formation of isolated area
Figure 1A is illustrated in the known shallow trench isolation of formation isolated area on the substrate from (STI) method to 1F.Consult Figure 1A, the top view of Semiconductor substrate shown in the figure 10 (or semiconductor well), substrate is the P type preferably, and is that industry is known.First and second layer materials 12 and 14 are formed (for example, growth or deposit) on substrate.For example, ground floor 12 can be silicon dioxide (is called later on " oxide "), with any known technology for example oxidation or oxide deposition (as chemical vapor deposition or CVD) be formed on the substrate 10, its thickness is about 60-150 dust ().The second layer 14 can be silicon nitride (is called later on " nitride "), preferably is formed on the oxide skin(coating) 12 by CVD, and its thickness is about 1000-2000 .Figure 1B illustrates the sectional view of resulting structures.
After forming for first and second layer 12/14, the photo-induced corrosion resistant material 16 that is fit to is coated on the nitride layer 14, and carries out masking steps, optionally remove along Y or row to some zone (band 18) in photo-induced corrosion resistant material, shown in Fig. 1 C.In the place of having removed photo-induced corrosion resistant material 16, with the etching technique (being anisotropic nitride and oxide etching technology) of standard nitride layer 14 and the oxide skin(coating) 12 that exposes in the band 18 etched away, in structure, form groove 20.Distance W between the adjacent ribbons 18 may diminish to the minimum lithographic feature of used technology.With silicon etch process groove 20 is extended downwardly in the silicon substrate 10 then, the degree of depth is about 500-4000 , shown in Fig. 1 D.Do not remove the place of photoresist 16, maintain nitride layer 14 and oxide skin(coating) 12.Resulting structures shown in Fig. 1 D has formed the active area 22 that interlocks with isolated area 24 now.
Described structure is further processed, remove residual photoresist 16.Then, with isolated material for example silicon dioxide be formed in first groove 20, method is the oxide skin(coating) of first deposit one bed thickness, then get rid of the oxide skin(coating) the oxide blocks 26 in first groove 20, shown in Fig. 1 E by chemical mechanical polishing or CMP etching (with nitride layer 14 as etching stopping layer).Get rid of remaining nitride and oxide skin(coating) 14/12 with the nitride/oxide etch process then, stay the sti oxide piece 26 that extends along isolated area 24, shown in Fig. 1 F.
Above-mentioned STI partition method is the method for optimizing that forms isolated area 24.But well-known selective oxidation silicon (LOCOS) isolation method (for example recessed LOCOS cushions LOCOS more, etc.) all can be used, and this moment, groove 20 can not extend in the substrate, and isolated material can be formed on the substrate surface in the belt-like zone 18.Figure 1A illustrates the memory cell array zone of substrate to 1F, and wherein each array storage unit is formed on by in the isolated area 24 separated active areas 22.Should be pointed out that substrate 10 also comprises at least one external zones, wherein form control circuit, be used for driving the memory cell that in the memory cell array district, forms.Best, also in above-mentioned same STI or LOCOS technical process, in external zones, form spacing block 26.
The formation of memory cell
Proceed to process as follows to the structure shown in Fig. 1 F.Fig. 2 A illustrates the sectional view of the structure of active area 22 from the visual angle (along the line 2A-2A of Fig. 1 C and 1F) that is orthogonal with Fig. 1 F to 2Q.
At first insulating barrier 30 (preferably oxide) is formed on the substrate 10, shown in Fig. 2 A.Can mix this moment to active area 22 parts of substrate 10, so that with respect to the cell array part of the independent better control store device of external zones.This doping often is called the Vt injection or the unit trap injects, and is in the industry cycle well-known.In this injection period, with photic resist layer protection external zones, that is, the photoresist layer is deposited on the total, only get rid of described photoresist floor then from the memory cell array district of substrate.
Secondly, the thick layer of hard mask material 32 (for example ∽ 3500 are thick) of formation such as nitride on oxide skin(coating) 30.Form a plurality of second parallel grooves 34 in nitride layer 32, method is: apply photoresist (sheltering) material on nitride layer 32, carry out masking steps then, get rid of photo-induced corrosion resistant material from selected parallel belt-like zone.Utilize anisotropic nitride etching (method) to get rid of the expose portion of nitride layer 32 in the belt-like zone, stay second groove 34 and extend downwards and expose oxide skin(coating) 30.After getting rid of photoresist, utilize anisotropic oxide etch (method) to get rid of the expose portion of oxide skin(coating) 30, second groove 34 is extended downwardly into substrate 10.Utilize then the anisotropic silicon etch process with second groove 34 in each active area 22 to downward Shen (for example, the downward degree of depth is that an about characteristic size is dark, is that about 0.15um is dark during for example with 0.15um technology) in substrate 10.Perhaps, also can after being formed in substrate and 10, get rid of groove 34 photoresist.The active area 22 of gained is shown in Fig. 2 B.
Silicon (described silicon forms the bottom and the lower wall of second groove 34) along the exposure in second groove 34 forms (preferably utilizing thermal oxidation technology) insulation material layer 36 (for example ∽ 70 are thick to 120 ) then.Then with polysilicon thick-layer 38 (hereinafter referred to as " polycrystalline ") be formed on this structure, fill up second groove 34.Polycrystal layer 38 can inject or by on-the-spot technology mix (for example n+) by ion.Gained active area 22 is shown in Fig. 2 C.
Utilize polycrystalline etch process (for example utilizing the CMP technology of nitride layer 32) to get rid of polycrystal layer 38, but still stay except the piece 40 of the polysilicon 38 in second groove 34 as etching stopping layer.Utilize controlled polycrystalline etching to reduce the height of polycrystalline piece 40 then, the top of polycrystalline piece 40 is positioned on the substrate surface, but under the top of the STI of isolated area 24 piece 26, shown in Fig. 2 D.
Carry out the etching of another time polycrystalline then, (contiguous second trenched side-wall) forms sloping portion 42 at polycrystalline piece 40 tops.Form nitride separate layer 44 then along second trenched side-wall and on the sloping portion 42 of polycrystalline piece 40.Separate layer 44 to be formed on industry well-known, relate to a kind of material of deposit on structure outline, then material is removed from the horizontal surface of described structure with anisotropic etching process, and unaffected basically at vertical orientated the above material of surface of structure.Separate layer 44 can be formed by any dielectric material, for example oxide, nitride etc.In the present embodiment, the method that forms separate layer 44 is: deposition of nitride layer on total, then use anisotropic etching process, and for example well-known reactive ion etching (RIE) is got rid of the nitride layer of the institute's deposit outside the divide layer 44.The active area 22 of gained is shown in Fig. 2 E.The formation that should be pointed out that nitride separate layer 44 is chosen wantonly, because separate layer 4 is the acutancees that are used for strengthening by the sloping portion 42 formed ends of polycrystalline piece 40.So Fig. 2 F-2R illustrates all the other procedure of processings that do not have optional nitride separate layer 44.
Carry out thermal oxidation subsequently, make the upper surface oxidation (forming oxide skin(coating) 46 thereon) of the exposure of polycrystalline piece 40, shown in Fig. 2 F.Form divided oxide interlayer 48 (being shown in Fig. 2 G) along the sidewall of second groove 34 then, method is a deposited oxide (for example about 350 are thick) structurally, then carries out anisotropic oxide etch.Described oxide etching is also got rid of the core of oxide skin(coating) 46 in each second groove 34.Gained active area 22 is shown in Fig. 2 G.
Carry out the etching of anisotropy polycrystalline then, get rid of not core, in each second groove 34, stay a pair of relative polycrystalline piece 40 by the polycrystalline piece of divided oxide interlayer 48 protections.Shown in Fig. 2 H.Utilize insulation deposit and the dark etching of anisotropy (etch back) technology exposed side in second groove 34 to form insulating barrier 50 (being shown in Fig. 2 I) then along polycrystalline piece 40a, insulating material can be any insulating material (for example, ONO-oxide/nitride/oxide, or other high dielectric material).Best, described insulating material is an oxide, and oxide deposition/etch process also can be thickeied divided oxide interlayer 48 like this, and causes getting rid of expose portion at the oxide skin(coating) 36 of each second groove, 34 bottom so that expose substrate 10, shown in Fig. 2 J.In addition, when removing the oxide skin(coating) 36 of each groove 34 bottom, described technology has also been removed the oxide among the STI between the adjacent column of active area 22 in the groove 34.
On the whole surface of described structure, carry out suitable ion then and inject (and possible annealing), so that the exposure substrate in second groove, 34 bottoms partly forms first (source) district 52.Source region 52 and 34 autoregistrations of second groove and formation is row continuously, and described continuous row is substantially perpendicular to the row of active area 22 and has second conduction type (for example N type) that is different from substrate first conduction type (for example P type).Described ion pair oxide skin(coating) 32 does not have remarkable influence.Gained active area 22 is shown in Fig. 2 K.
Carry out the oxidation depositing step then, fill up the bottom of each groove 34 with oxide skin(coating) 35, the thickness of oxide skin(coating) 35 is at least about 100 , but must not be thicker than the height of the floating gate-polycrystalline piece 40 that be about to form, the capacitive coupling take place so that make between the control gate 54 of deposit soon and formation and the polycrystalline piece 40.Carry out the polycrystalline deposition step after this, then carry out polycrystalline CMP etching (utilizing nitride layer 32), utilize polycrystalline piece 54 to fill second groove 34, shown in Fig. 2 L as etching stopping layer.Like this, polycrystalline 54 has been filled each groove 34 in the continuous row.Then carry out nitride etch, get rid of nitride layer 32, and expose the upper limb of polycrystalline piece 40.Use thermal oxidation subsequently, oxide deposition, or the two, in the upper limb formation tunnel oxide 56 of polycrystalline piece 40.Described oxide forms step and also forms oxide skin(coating) 58 on the end face of the exposure of polycrystalline piece 54, and may thicken the oxide skin(coating) 30 on the substrate 10.The Vt that can choose wantonly at external zones this moment by shielding active area 22 injects.Gained active area 22 is shown in Fig. 2 M and 2N.
Near formation nitride separate layer 70 structure shown in Fig. 2 N then.The method that realizes this point is: deposit silicon nitride 70 on total, anisotropically etch away the nitride that forms separate layer 70 again.Resulting structures is shown in Figure 20.
Injection occurs on the total.Specifically, the zone between nitride separate layer 70 forms drain region 72.Injecting energy is enough to extend under the isolation oxide.Like this, drain region 72 is continuous on the direction of whole row.Resulting structures is shown in Fig. 2 P.
Remove nitride separate layer 70, resulting structures is shown in Fig. 2 Q.
At last, utilize the polycrystalline deposition step structurally to form polycrystal layer 62 (about 500 are thick).Carry out photoresist deposit and masking steps subsequently, form many polycrystal layers 62, they are spaced apart from each other and each is on an active area 22.Gained active area 22 is shown in Fig. 2 R.Each polycrystal layer 62 plays the word line of storage array.
Shown in Fig. 2 R, technical process of the present invention has formed memory cell array, each memory cell 15 be between source region 52 and the drain region 72 (professional and technical personnel should be understood that term " source " and " leakage " when work, can exchange).The non plane channel district is connecting source/drain region 52/72, and channel region has two parts: first and second portion.The first of channel region is along a sidewall of one of each groove 34, and the contiguous first source region 52a.The second portion of channel region is along the plane surface of substrate 10, and between groove 34 and drain region 72.Dielectric layer is on channel region.On the first of channel region dielectric layer 36a.It on the second portion of channel region dielectric layer 30.Floating gate 40a on layer 36a, and in the first of channel region, the contiguous first source region 52a.The gate electrode 62 that is formed by polycrystal layer 62 is on the dielectric layer 30 and on the second portion at channel region.Control gate 54 and source region 52 insulation, and capacitive is coupled to floating gate 40a.Each floating gate 40 is substantially perpendicular to gate electrode 62 and perpendicular to the surface of substrate 10.At last, each source region for example source region 52a and related control gate 54a thereof is shared by the consecutive storage unit 15 of same active area 22 1 sides, and the drain region is shared by the consecutive storage unit 15 of opposite side.
All floating gates 40 all place groove 34, each floating gate 40 in the face of the part channel region and with its insulation.In addition, each floating gate 40 comprises a top, it extend on the substrate surface and terminate in the face of gate electrode 62 and with an edge of its insulation in, thereby provide path for Fowler-Nordheim tunnel effect by oxide skin(coating) 56.Each control gate 54 along floating gate 44 extend and with its insulation (by oxide skin(coating) 50 insulation), the voltage coupling that is used for strengthening between them.
As for a plurality of memory cell 15 that form array, its interconnection is as follows.In same row, i.e. memory cell 15 in same active area 22, the word line 62 that forms each memory cell 15 gate electrode extends to each memory cell 15 on the Y direction.For with the memory cell 15 of (promptly crossing active area 22 and STI 26) in the delegation, source line 52 and related control gate 54 extend to each in these memory cell 15 continuously on directions X.In addition, thread cast-off 72 extends to each in these memory cell 15 continuously on directions X.At last, as seen by above-mentioned, the memory cell 15 in the adjacent lines is at shared same source region 52 of a side and same related control gate 54, in the shared same drain region 72 of opposite side.Each memory cell has four terminals that independence is controlled: word line 62, control gate 54 and drain region/source region 72/52.
The professional and technical personnel should be understood that line 52a, 52b, 52c etc. are embedding diffusing lines, and must be connected to these lines outside memory cell array.A kind of approach is to utilize polycrystalline piece 54, is similar to control gate 54, outer embedding diffusing lines 52a, the 52b of then array, 52c etc. but polycrystalline piece 54 is electrically connected.And the polycrystalline piece 54 that connects array outer embedding diffusing lines 52a, 52b, 52c etc. must not be electrically connected with the independent control gate 54 in the array.And line 72a, 72b, 72c etc. also are embedding diffusing lines, and must provide and being connected of these lines.So memory cell 15 arrays are virtual earth arrays.
The work of memory cell
The work of the memory cell 15 shown in Fig. 2 R will be described below.
Wipe
But two kinds of method eraseable memory units 15 are arranged.At first, memory cell 15 can be by adding 0 volt and add 0 volt wipe on source region 52 leaking on 72.Owing to identical voltage is added to source/drain regions 52/72, does not just have charge-conduction in the channel region.About-8 negative voltage to-15 volts is added on the control gate 54.At last with little positive voltage (for approximately+2 to+4 volts) be added on the word line 62.Because control gate the last 54 capacitive is coupled to floating gate 40, floating gate 40 just has high negative voltage.This has caused the big voltage difference between floating gate 40 and the word line 62.The electronics Be Controlled grid 54 that are stored on the floating gate 40 repel, and the positive voltage that is added on the word line 62 attracts, and by the Fowler-Nordheim tunnel effect, electronics leaves floating gate 40, and the oxide 56 that passes through tunnel arrives word line 62.This polycrystalline that is used to wipe is at United States Patent (USP) 5,029 to the mechanism of the tunnel effect of polycrystalline, proposes in 130, and its content all is included in this paper as a reference.
The second method of eraseable memory unit 15 is to add 0 volt to leaking 72, and add+2 to+5 volts little positive electricity is pressed onto source region 52.About-8 negative voltage to-15 volts is added on the control gate 54.At last 0 volt or about 0 to-2 volt little negative voltage are added on the word line 62.Because word line 62 is not the positive voltage that adds, so channel region can conducting.And, because control gate the last 54 capacitive is coupled to floating gate 40, so floating gate 40 will have negative low-voltage.This causes the big voltage difference between floating gate 40 and the source region 52.The electronics Be Controlled grid 54 that are stored on the floating gate 40 repel, and the positive voltage that is added on the source region 52 attracts, and by the Fowler-Nordheim tunnel effect, electronics leaves floating gate 40, passes oxide 35, to source region 52.
Programming
The programming of memory cell 15 can followingly be carried out.Source region 52 is remained on+positive voltage between 3 to+5 volts.Control gate 54 remains on+positive voltage between 8 to+10 volts.Word line 62 remains on the positive voltage of 1-3 volt.Drain region 72 keeps ground voltage.Because control gate the last 54 capacitive is coupled to floating gate 40, thus on the control gate 54+8 to+10 volts positive voltage makes floating gate 40 have high positive potential, and it is enough to the first in communication channel district.The positive voltage of 1-3 volt is enough to the second portion in communication channel district on the word line 62.So electronics 72 traverses into source region 52 from the drain region in channel region.But, turning to the node of channel region of groove 34 from plane surface with 90 degree basically at channel region, electronics will stand the unexpected rising of voltage because of the positive voltage of floating gate 40.This causes the electronics heat tunnel to be injected on the floating gate 40.It is at United States Patent (USP) 5,029 that this heat tunnel electronics that is used to programme injects mechanism, proposes in 130, and its content all is included in this paper as a reference.
Read
Reading of memory cell 15 can followingly be carried out.Source region 52 is remained on ground voltage.Control gate 54 remains on positive voltage Vdd.Word line 62 remains on positive voltage Vdd, and described voltage generally is enough to the second portion in communication channel district.Drain region 72 remains on little positive voltage, for example+1.0 volt.If to floating gate 40 programmings, then the positive voltage Vdd on the control gate 54 is not enough to the first in communication channel district.In this case, electronics can be from the source region in channel region 52 traverses into drain region 72.If but floating gate 40 programmed, then the positive voltage Vdd on the control gate 54 is not enough to the first in communication channel district.In this case, raceway groove is still not conducting.So the 72 detected magnitudes of current or have in the drain region/no current has determined the programming state of floating gate 40.
The work of memory cell array
The work of memory cell 15 arrays now is described.The array of memory cell is illustrated in Fig. 3.As shown in Figure 3, memory cell 15 arrays comprise a plurality of memory cell, are arranged in multiple row: 15a (1-3) and 15b (1-3), and multirow: 15 (a-b) 1,15 (a-b) 2 and 15 (a-b) 3.The word line 62 that is connected to memory cell 15 also is connected to other memory cell 15 of same row.Source region 52 and control gate 54 are connected to the unit 15 with delegation, and be shared by the memory cell 15 of each side.Drain region 72 is connected to the unit 15 with delegation, and shared by the memory cell 15 of either side.The memory cell 15 in the delegation and the memory cell 15 of a side have shared drain region 72, and have shared source region 52 and control gate 72 with the memory cell of opposite side.
Wipe
In the work of wiping, two kinds of possible working methods are arranged as previously mentioned.In first kind of mode, can wipe single memory cell 15.The voltage that is added on each bar line is as follows.Drain region 72 for the memory cell of being chosen 15 adds ground voltage.Drain region 72 for unchecked memory cell 15 also adds ground voltage.Source region 52 for the memory cell of being chosen 15 adds ground voltage.Source region 52 for unchecked memory cell 15 also adds ground voltage.For the word line 62 of the memory cell of being chosen 15, add approximately+2 to+4 volts positive voltage.Word line 62 for unchecked memory cell 15 adds ground voltage.At last, for the control gate 54 of the memory cell of being chosen 15, add approximately-8 to-15 volts high negative voltage.Control gate 54 for unchecked memory cell 15 adds ground voltage.
As previously mentioned, for the memory cell of being chosen 15, the high-capacitance of 54 pairs of floating gates 40 of control gate causes floating gate 40 that high negative voltage is arranged.Positive voltage on the adjacent word line 62 attracted on the word line electronics, and by Fowler-Nordheim tunnel effect mechanism, electronics leaves floating gate 54.For unchecked memory cell 15 in the same row, though on word line 62, added+2 to+4 volts little positive voltage, because the control gate 54 of unchecked memory cell 15 remains ground voltage, the electronics in the same row on the floating gate 40 of unchecked memory cell 15 can not attracted on the word line 62.As for unchecked memory cell 15 in the delegation, though be added with high negative voltage on it, corresponding word line 62 still remains on ground voltage.So there is not positive voltage that the floating gate 40 of electronics from unchecked memory cell 15 attracted.In this manner, wiping is that the position is selectable.
In second kind of erase mode, added various voltages are as follows.Drain region 72 for the memory cell of being chosen 15 adds ground voltage.Drain region 72 for unchecked memory cell 15 also adds ground voltage.Source region 52 for the memory cell of being chosen 15 adds+2 to+5 volts little positive voltage.Source region 52 for unchecked memory cell 15 adds ground voltage.For the word line 62 of the memory cell of being chosen 15, add the little negative voltage that ground voltage arrives about 0 to-2 volts.For the word line 62 of unchecked memory cell 15, add the little negative voltage that ground voltage arrives about 0 to-2 volts.At last, for the control gate 54 of the memory cell of being chosen 15, add approximately-8 to-15 volts high negative voltage.Control gate 54 for unchecked memory cell 15 adds ground voltage.
Under this working method, be wiped free of simultaneously with all memory cell 15 of delegation.So in this manner, wiping is that row is selectable.For the memory cell 15 of institute's selected line, the high-capacitance of 54 pairs of floating gates 40 of control gate causes floating gate 40 that high negative voltage is arranged.Positive voltage on the adjacent source regions 52 is attracted electronics, and by Fowler-Nordheim tunnel effect mechanism, electronics leaves floating gate 54.For the memory cell 15 of selected line not, control gate 54 remains ground voltage.At last, the ground that is added on all word lines 62 has guaranteed that to negative voltage the channel region of all memory cell can not be switched on.
Programming
Let as assume that and to programme to the floating gate 40 of memory cell 15.According to the above discussion, the voltage that is added on each bar line is as follows: line 72b is a ground voltage, and all other drain region 72a are Vdd; Line 52a is+3 to+5 volts, and all other source region 52b are ground voltage; Line 62b is+1 to+3 volts, and all other word line 62a to-2 volts with being; Line 54a is+8 to+10 volts, and all other line 54b are ground voltage.On the unchecked memory cell 15 " disturbance " as follows.
For the memory cell 15 of not choosing row, adding 0 volt means to word line 62a to-2 volts: for those memory cell 15a (1-n) and 15c (1-n), not having channel region is conducting, because not conducting of the second portion of channel region (it is that part of that word line 62a controls).So, do not have disturbance.Samely choose row but be in not the memory cell 15b1 of selected line (described not selected line is to have a side of shared source region 52 and control gate 54 with the memory cell of choosing 15) for being in, add Vdd on the line 72a and mean in memory cell 15b1 seldom or do not have a current lead-through.At last, samely choose row but be in not the memory cell 15b3 of selected line (described not selected line is to have a side in shared drain region 72 with the memory cell of choosing 15) for being in, add ground voltage on line 54b and the 52b and mean in memory cell 15b3 seldom or do not have a current lead-through.
Read
Let as assume that the floating gate 40 that to read memory cell 15b2.According to the above discussion, the voltage that is added on each bar line is as follows: the positive voltage that drain region line 72b remains on approximately+1 volt, and unchecked thread cast-off 72a remains on ground voltage.Control grid line 54a remains on positive voltage Vdd, and unchecked control gate 54b remains on ground voltage.The word line 62b that chooses remains on positive voltage Vdd, and unchecked word line 62a remains on ground voltage.At last, the source line 52a that chooses remains on ground voltage, and the unchecked source line 52b of the thread cast-off 72b that chooses of next-door neighbour remains on 1 volt, and the unchecked source line 52 that is close to unchecked thread cast-off 72a remains on ground voltage.So, have source of being added to 52 and the identical voltage that leaks on 72 in all memory cell 15 of memory cell 15 1 sides of choosing, and in like manner also have source of being added to 52 and the identical voltage that leaks on 72 in all memory cell of opposite side.On the unchecked memory cell 15 " disturbance " as follows.
For the memory cell 15 of not choosing row, add 0 volt and mean to word line 62: for those memory cell 15, not having channel region is conducting.So, do not have disturbance.Samely choose row but be in not the memory cell 15b1 and the 15b3 of selected line for being in, identical voltage is added to means in the source/leakage 52/72 of those memory cell that channel region will can conducting yet.So, almost do not have the disturbance of generation to memory cell 15b2.
As seen by above-mentioned, a kind of high density nonvolatile memory cell, array and manufacture method thereof of novelty disclosed.Though should be pointed out that to preferred embodiment it is to be illustrated with the single position of storage in each floating gate of memory cell.In single memory cell, on floating gate, store a plurality of positions,, also belong within the spirit of the present invention with further increase storage density.
Claims (20)
1. nonvolatile memory cell, it comprises:
The semi-conducting material of the monocrystalline basically of first conduction type, it has the surface on plane basically, in the described surface of described material groove is arranged, and described groove has sidewall and diapire;
In described material along the first area of second conduction type of described first conduction type of being different from of described plane surface;
In described material along the second area of described second conduction type of the described diapire of described groove;
Have first and second portion, be connected the channel region that is used for conduct charges in described first and second zones, wherein said first is along the described surface of contiguous described first area, and described second portion is along the described sidewall of contiguous described second area;
Dielectric layer on described channel region;
Floating gate, it is on described dielectric layer, spaced apart with the described second portion of described channel region in described tunnel;
First grid electrode on described dielectric layer, the described first of it and described channel region is spaced apart; And
Second gate electrode, it is in described groove, and capacitive is coupled to described floating gate.
2. unit as claimed in claim 1, the semi-conducting material of wherein said monocrystalline basically is a monocrystalline silicon.
3. unit as claimed in claim 1, wherein said floating gate have the end of contiguous described first grid electrode substantially.
4. unit as claimed in claim 3 wherein also is included in second dielectric layer between described end and the described first grid electrode, allows electronics to traverse to described first grid electrode from described floating gate with the Fowler-Nordheim tunnel effect.
5. unit as claimed in claim 1 wherein also is included in second dielectric layer between the described diapire of described floating gate and described groove, and its allows electronics Fowler-Nordheim tunneling from described floating gate to described second area.
6. array of nonvolatile memory cells, it is arranged in multiple row and multirow, and described array comprises:
The semi-conducting material of the monocrystalline basically of first conduction type, it has the surface on plane basically, in the described surface of described material a plurality of grooves is arranged, and each described groove has sidewall and diapire;
A plurality of nonvolatile memory cells, they are arranged in multiple row and multirow in described semiconductor substrate materials, and each unit comprises:
In described material along the first area of second conduction type of described first conduction type of being different from of described surface;
In described material along the second area of described second conduction type of the described diapire of described groove;
Have first with second portion, be connected the channel region that described first and second zones are used for conduct charges, wherein said first is along the described surface of contiguous described first area, and described second portion is along the described sidewall of contiguous described second area;
Dielectric layer on described channel region;
Floating gate, it is spaced apart with the described second portion of described channel region on described dielectric layer;
First grid electrode on described dielectric layer, the described first of it and described channel region is spaced apart; And
Second gate electrode, it is in described groove, and capacitive is coupled to described floating gate;
Wherein, has shared described first grid electrode with the described unit in the delegation;
Wherein, the described unit in the same row has shared described first area, shared described second area, shared described two gate electrode, and
Wherein, the described unit in the adjacent column is in the shared described first area that a side has, and shared described second gate electrode and the described second area that have at opposite side.
7. array as claimed in claim 6, the semi-conducting material of wherein said monocrystalline basically is a monocrystalline silicon.
8. array as claimed in claim 6 wherein has the end of contiguous described first grid electrode substantially at floating gate described in each unit.
9. array as claimed in claim 8, wherein each unit also is included in second dielectric layer between described end and the described first grid electrode, and it allows the Fowler-Nordheim tunneling of electronics from described floating gate to described first grid electrode.
10. array as claimed in claim 6, wherein each unit also is included in second dielectric layer between the described diapire of described floating gate and described groove, and its allows electronics Fowler-Nordheim tunneling from described floating gate to described second area.
11. array as claimed in claim 6, wherein isolated area is separated the adjacent lines of each unit.
12. method of in the semiconductor substrate materials of the monocrystalline basically of first conduction type, making array of nonvolatile memory cells, wherein said array of nonvolatile memory cells has a plurality of nonvolatile memory cells that are arranged in multirow and multiple row in described semiconductor substrate materials, and described method comprises:
Form isolated isolated area on described Semiconductor substrate, they are parallel to each other basically and extend in the direction of described row, between each is to adjacent isolated area active area are arranged, and wherein said Semiconductor substrate has the surface on plane basically;
Form a plurality of memory cell in each described active area, wherein the forming process of each memory cell comprises:
Form groove in the described surface of described substrate, described groove has sidewall and diapire;
In described groove, form floating gate with described lateral wall insulation along described sidewall;
Described diapire along described groove in described substrate forms the first area, and described first area has second conduction type that is different from described first conduction type;
Form first grid electrode in described groove, described first grid electrode and the insulation of described first area and capacitive are coupled to described floating gate;
In described substrate, form along its surface have described second conduction type with the isolated second area of described groove; And
Form second gate electrode, spaced between it and described second area and the described groove.
13. method as claimed in claim 12, the described step that wherein forms described first grid electrode are included in and cross multiple row on the described line direction and form described first grid electrode continuously.
14. method as claimed in claim 12, the described step that wherein forms described second gate electrode are included in and cross multirow on the described column direction and form described second gate electrode continuously.
15. method as claimed in claim 14, the described step that wherein forms described first area and described second area are included in and cross multiple row on the described line direction and form described first area and described second area continuously.
16. method as claimed in claim 15, wherein said have shared described second gate electrode with the described unit in the delegation; Described unit in the described same row has shared described first area, shared described second area, shared described first grid electrode; And the described unit in adjacent each row has shared described second area in a side, and has shared described first grid electrode and described first area at opposite side.
17. a method of making nonvolatile memory cell in the semiconductor substrate materials of the monocrystalline basically of first conduction type, described substrate has the surface on plane basically, and described method comprises:
Form groove in the described surface of described substrate, described groove has sidewall and diapire;
In described groove, form floating gate with described lateral wall insulation along described sidewall;
Described diapire along described groove in described substrate forms the first area, and described first area has second conduction type that is different from described first conduction type;
Form first grid electrode in described groove, described first grid electrode and the insulation of described first area and capacitive are coupled to described floating gate;
In described substrate, form and the isolated second area of described groove with described second conduction type along its surface; And
Form second gate electrode, spaced between it and described second area and the described groove.
18. method as claimed in claim 17 wherein also is included between described second gate electrode and the described floating gate and forms insulating material, its thickness allows the Fowler-Nordheim tunneling of electronics from described second floating gate to described second gate electrode.
19. method as claimed in claim 17 wherein also is included between the described diapire of described floating gate and described groove and forms insulating material, described insulating material allows the Fowler-Nordheim tunneling of electronics from described floating gate to described second area.
20. method as claimed in claim 18, the described step that wherein forms described floating gate is included in and forms described floating gate on the described substrate surface.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/797296 | 2004-03-09 | ||
| US10/797,296 US7307308B2 (en) | 2003-04-07 | 2004-03-09 | Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1691336A true CN1691336A (en) | 2005-11-02 |
Family
ID=35085603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005100550905A Pending CN1691336A (en) | 2004-03-09 | 2005-03-08 | Buried bit line non-volatile floating gate memory cell, and array thereof, and method of formation |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2005260235A (en) |
| KR (1) | KR20060043534A (en) |
| CN (1) | CN1691336A (en) |
| TW (1) | TW200601461A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010606A (en) * | 2018-01-05 | 2019-07-12 | 硅存储技术公司 | With the dual bit nonvolatile memory unit of floating gate in substrate trenches |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9293204B2 (en) * | 2013-04-16 | 2016-03-22 | Silicon Storage Technology, Inc. | Non-volatile memory cell with self aligned floating and erase gates, and method of making same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4868629A (en) * | 1984-05-15 | 1989-09-19 | Waferscale Integration, Inc. | Self-aligned split gate EPROM |
| IT1227989B (en) * | 1988-12-05 | 1991-05-20 | Sgs Thomson Microelectronics | EPROM MEMORY CELL MATRIX WITH TABLECLOTH STRUCTURE WITH IMPROVED CAPACITIVE RATIO AND PROCESS FOR ITS MANUFACTURE |
| US5278439A (en) * | 1991-08-29 | 1994-01-11 | Ma Yueh Y | Self-aligned dual-bit split gate (DSG) flash EEPROM cell |
| JP3720358B2 (en) * | 1991-08-29 | 2005-11-24 | ヒュンダイ エレクトロニクス インダストリーズ カムパニー リミテッド | Self-aligned dual bit split gate flash EEPROM cell |
| JPH05211338A (en) * | 1991-10-09 | 1993-08-20 | Mitsubishi Electric Corp | Non-volatile semiconductor device |
| JP3403877B2 (en) * | 1995-10-25 | 2003-05-06 | 三菱電機株式会社 | Semiconductor memory device and manufacturing method thereof |
| US5963806A (en) * | 1996-12-09 | 1999-10-05 | Mosel Vitelic, Inc. | Method of forming memory cell with built-in erasure feature |
| US6952034B2 (en) * | 2002-04-05 | 2005-10-04 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with buried source line and floating gate |
-
2005
- 2005-02-22 TW TW094105237A patent/TW200601461A/en unknown
- 2005-03-08 KR KR1020050019259A patent/KR20060043534A/en not_active Application Discontinuation
- 2005-03-08 CN CNA2005100550905A patent/CN1691336A/en active Pending
- 2005-03-09 JP JP2005065101A patent/JP2005260235A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010606A (en) * | 2018-01-05 | 2019-07-12 | 硅存储技术公司 | With the dual bit nonvolatile memory unit of floating gate in substrate trenches |
| CN110010606B (en) * | 2018-01-05 | 2023-04-07 | 硅存储技术公司 | Dual bit non-volatile memory cell with floating gate in substrate trench |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20060043534A (en) | 2006-05-15 |
| TW200601461A (en) | 2006-01-01 |
| JP2005260235A (en) | 2005-09-22 |
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