DE3685709D1 - Substratstruktur zur herstellung einer halbleiterverbundanordnung. - Google Patents

Substratstruktur zur herstellung einer halbleiterverbundanordnung.

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Publication number
DE3685709D1
DE3685709D1 DE8686113185T DE3685709T DE3685709D1 DE 3685709 D1 DE3685709 D1 DE 3685709D1 DE 8686113185 T DE8686113185 T DE 8686113185T DE 3685709 T DE3685709 T DE 3685709T DE 3685709 D1 DE3685709 D1 DE 3685709D1
Authority
DE
Germany
Prior art keywords
producing
substrate structure
connector arrangement
semiconductor connector
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686113185T
Other languages
English (en)
Other versions
DE3685709T2 (de
Inventor
Koichi Kitahara
Yu Ohata
Tsuyoshi Kuramoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3685709D1 publication Critical patent/DE3685709D1/de
Application granted granted Critical
Publication of DE3685709T2 publication Critical patent/DE3685709T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76278—Vertical isolation by selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
DE8686113185T 1985-09-30 1986-09-25 Substratstruktur zur herstellung einer halbleiterverbundanordnung. Expired - Lifetime DE3685709T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60214853A JPS6276645A (ja) 1985-09-30 1985-09-30 複合半導体結晶体構造

Publications (2)

Publication Number Publication Date
DE3685709D1 true DE3685709D1 (de) 1992-07-23
DE3685709T2 DE3685709T2 (de) 1993-01-28

Family

ID=16662628

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686113185T Expired - Lifetime DE3685709T2 (de) 1985-09-30 1986-09-25 Substratstruktur zur herstellung einer halbleiterverbundanordnung.

Country Status (4)

Country Link
US (1) US4948748A (de)
EP (1) EP0217288B1 (de)
JP (1) JPS6276645A (de)
DE (1) DE3685709T2 (de)

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JPH01125858A (ja) * 1987-11-10 1989-05-18 Fujitsu Ltd 半導体装置およびその製造方法
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US5332920A (en) * 1988-02-08 1994-07-26 Kabushiki Kaisha Toshiba Dielectrically isolated high and low voltage substrate regions
US5049968A (en) * 1988-02-08 1991-09-17 Kabushiki Kaisha Toshiba Dielectrically isolated substrate and semiconductor device using the same
JP2788269B2 (ja) * 1988-02-08 1998-08-20 株式会社東芝 半導体装置およびその製造方法
JP2685819B2 (ja) * 1988-03-31 1997-12-03 株式会社東芝 誘電体分離半導体基板とその製造方法
JP2763107B2 (ja) * 1988-05-30 1998-06-11 株式会社東芝 誘電体分離半導体基板およびその製造方法
US4910164A (en) * 1988-07-27 1990-03-20 Texas Instruments Incorporated Method of making planarized heterostructures using selective epitaxial growth
US4989063A (en) * 1988-12-09 1991-01-29 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
JPH0775243B2 (ja) * 1989-02-22 1995-08-09 株式会社東芝 半導体装置の製造方法
US4908328A (en) * 1989-06-06 1990-03-13 National Semiconductor Corporation High voltage power IC process
JPH0824162B2 (ja) * 1989-07-10 1996-03-06 日本電装株式会社 半導体装置およびその製造方法
JPH0636414B2 (ja) * 1989-08-17 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
US5034343A (en) * 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
JP3111500B2 (ja) * 1991-05-09 2000-11-20 富士電機株式会社 誘電体分離ウエハの製造方法
JP2799254B2 (ja) * 1991-07-11 1998-09-17 三菱電機株式会社 半導体装置の製造方法
FR2687008B1 (fr) * 1992-02-05 2001-06-22 Patrick Launay Procede de fabrication de structures actives et dispositifs semiconducteurs ainsi obtenus.
DE4204004A1 (de) * 1992-02-12 1993-08-19 Daimler Benz Ag Verfahren zur herstellung einer halbleiterstruktur mit vertikalen und lateralen halbleiterbauelementen und nach dem verfahren hergestellte halbleiterstruktur
JP3014012B2 (ja) * 1992-03-19 2000-02-28 日本電気株式会社 半導体装置の製造方法
JP2796012B2 (ja) * 1992-05-06 1998-09-10 株式会社東芝 半導体装置及びその製造方法
US5260233A (en) * 1992-11-06 1993-11-09 International Business Machines Corporation Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
JP2526786B2 (ja) * 1993-05-22 1996-08-21 日本電気株式会社 半導体装置及びその製造方法
JPH1027893A (ja) * 1993-10-29 1998-01-27 Amer Fib Inc 電荷シンク又は電位ウェルとして設けられた絶縁層の下の基板内に電気的に結合され別に形成されたドープされた領域を有するｓｏｉウエーハ上に設けられた集積回路（ｉｃ）装置
JP2773611B2 (ja) * 1993-11-17 1998-07-09 株式会社デンソー 絶縁物分離半導体装置
DE69329999T2 (de) * 1993-12-29 2001-09-13 Cons Ric Microelettronica Verfahren zur Herstellung integrierter Schaltungen, insbesondere intelligenter Leistungsanordnungen
US5468674A (en) * 1994-06-08 1995-11-21 The United States Of America As Represented By The Secretary Of The Navy Method for forming low and high minority carrier lifetime layers in a single semiconductor structure
DE4423067C2 (de) * 1994-07-01 1996-05-09 Daimler Benz Ag Verfahren zum Herstellen eines isolierten Halbleitersubstrats
JP2624186B2 (ja) * 1994-07-29 1997-06-25 日本電気株式会社 貼り合わせシリコン基板の製造方法
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US6015980A (en) * 1996-03-08 2000-01-18 The Regents Of The University Of California Metal layered semiconductor laser
US5977604A (en) * 1996-03-08 1999-11-02 The Regents Of The University Of California Buried layer in a semiconductor formed by bonding
JP2917919B2 (ja) * 1996-06-20 1999-07-12 日本電気株式会社 半導体基板およびその製造方法、並びに半導体素子
US6271070B2 (en) * 1997-12-25 2001-08-07 Matsushita Electronics Corporation Method of manufacturing semiconductor device
TW502458B (en) 1999-06-09 2002-09-11 Toshiba Corp Bonding type semiconductor substrate, semiconductor light emission element and manufacturing method thereof
JP4322453B2 (ja) * 2001-09-27 2009-09-02 株式会社東芝 半導体装置およびその製造方法
JP2003203967A (ja) * 2001-12-28 2003-07-18 Toshiba Corp 部分ｓｏｉウェーハの製造方法、半導体装置及びその製造方法
JP4489366B2 (ja) * 2003-03-17 2010-06-23 株式会社日立製作所 半導体装置
JP2005244020A (ja) * 2004-02-27 2005-09-08 Toshiba Corp 半導体装置及びその製造方法
TWI401749B (zh) * 2004-12-27 2013-07-11 Third Dimension 3D Sc Inc 用於高電壓超接面終止之方法
EP1873821B1 (de) 2006-06-27 2015-11-11 STMicroelectronics Srl SOI Anordnung mit durch eine epitaktische Abscheidung hergestellten vergrabenen Kontakten
JP2008087636A (ja) * 2006-10-02 2008-04-17 Calsonic Kansei Corp 空調装置
US10153300B2 (en) * 2016-02-05 2018-12-11 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device including a high-electron-mobility transistor (HEMT) and method for manufacturing the same

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JPH0671043B2 (ja) * 1984-08-31 1994-09-07 株式会社東芝 シリコン結晶体構造の製造方法
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Also Published As

Publication number Publication date
US4948748A (en) 1990-08-14
JPS6276645A (ja) 1987-04-08
EP0217288A2 (de) 1987-04-08
EP0217288B1 (de) 1992-06-17
DE3685709T2 (de) 1993-01-28
EP0217288A3 (en) 1988-05-18

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