DE3689971D1 - Herstellung einer halbleiteranordnung. - Google Patents
Herstellung einer halbleiteranordnung.Info
- Publication number
- DE3689971D1 DE3689971D1 DE3689971T DE3689971T DE3689971D1 DE 3689971 D1 DE3689971 D1 DE 3689971D1 DE 3689971 T DE3689971 T DE 3689971T DE 3689971 T DE3689971 T DE 3689971T DE 3689971 D1 DE3689971 D1 DE 3689971D1
- Authority
- DE
- Germany
- Prior art keywords
- production
- semiconductor arrangement
- semiconductor
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP1986/000113 WO1987005441A1 (en) | 1986-03-05 | 1986-03-05 | Semiconductor device and a method of producing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3689971D1 true DE3689971D1 (de) | 1994-08-18 |
DE3689971T2 DE3689971T2 (de) | 1994-12-08 |
Family
ID=13874399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3689971T Expired - Fee Related DE3689971T2 (de) | 1986-03-05 | 1986-03-05 | Herstellung einer halbleiteranordnung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4757033A (de) |
EP (1) | EP0259490B1 (de) |
KR (1) | KR940000750B1 (de) |
DE (1) | DE3689971T2 (de) |
WO (1) | WO1987005441A1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01161773A (ja) * | 1987-12-18 | 1989-06-26 | Agency Of Ind Science & Technol | 化合物半導体装置の製造方法 |
US4851370A (en) * | 1987-12-28 | 1989-07-25 | American Telephone And Telegraph Company, At&T Bell Laboratories | Fabricating a semiconductor device with low defect density oxide |
US5223454A (en) * | 1988-01-29 | 1993-06-29 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit device |
US5049972A (en) * | 1988-01-29 | 1991-09-17 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit device |
JPH0682926B2 (ja) * | 1988-04-22 | 1994-10-19 | 日本電気株式会社 | 多層配線基板の製造方法 |
JP2852679B2 (ja) * | 1989-09-01 | 1999-02-03 | 富士通株式会社 | 半導体装置及びその製造方法 |
US5252843A (en) * | 1989-09-01 | 1993-10-12 | Fujitsu Limited | Semiconductor device having overlapping conductor layers |
GB2244373B (en) * | 1990-05-19 | 1994-07-20 | Stc Plc | Semiconductor device manufacture |
US5328868A (en) * | 1992-01-14 | 1994-07-12 | International Business Machines Corporation | Method of forming metal connections |
US5484740A (en) * | 1994-06-06 | 1996-01-16 | Motorola, Inc. | Method of manufacturing a III-V semiconductor gate structure |
US6388322B1 (en) * | 2001-01-17 | 2002-05-14 | Aralight, Inc. | Article comprising a mechanically compliant bump |
DE102007006640A1 (de) * | 2007-02-06 | 2008-08-07 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Aufbringen einer Struktur auf ein Halbleiterbauelement |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS501514B1 (de) * | 1969-04-01 | 1975-01-18 | ||
JPS5728950B2 (de) * | 1973-04-25 | 1982-06-19 | ||
JPS501514A (de) * | 1973-05-12 | 1975-01-09 | ||
JPS5056886A (de) * | 1973-09-14 | 1975-05-17 | ||
JPS5056885A (de) * | 1973-09-14 | 1975-05-17 | ||
JPS5841775B2 (ja) * | 1975-09-25 | 1983-09-14 | 日本電気株式会社 | ハンドウタイソウチノセイゾウホウホウ |
JPS52154351A (en) * | 1976-06-18 | 1977-12-22 | Hitachi Ltd | Formation of electrode contact holes in semiconductor devices |
US4564997A (en) * | 1981-04-21 | 1986-01-21 | Nippon-Telegraph And Telephone Public Corporation | Semiconductor device and manufacturing process thereof |
JPS5841775A (ja) * | 1981-09-07 | 1983-03-11 | 大同特殊鋼株式会社 | セラミツクス−金属複合体の製造方法 |
JPS58130575A (ja) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | 電界効果トランジスタの製造方法 |
US4451971A (en) * | 1982-08-02 | 1984-06-05 | Fairchild Camera And Instrument Corporation | Lift-off wafer processing |
US4440804A (en) * | 1982-08-02 | 1984-04-03 | Fairchild Camera & Instrument Corporation | Lift-off process for fabricating self-aligned contacts |
FR2539556B1 (fr) * | 1983-01-13 | 1986-03-28 | Commissariat Energie Atomique | Procede de fabrication de conducteurs pour circuits integres, en technologie planar |
US4497684A (en) * | 1983-02-22 | 1985-02-05 | Amdahl Corporation | Lift-off process for depositing metal on a substrate |
US4484978A (en) * | 1983-09-23 | 1984-11-27 | Fairchild Camera & Instrument Corp. | Etching method |
US4539222A (en) * | 1983-11-30 | 1985-09-03 | International Business Machines Corporation | Process for forming metal patterns wherein metal is deposited on a thermally depolymerizable polymer and selectively removed |
US4532002A (en) * | 1984-04-10 | 1985-07-30 | Rca Corporation | Multilayer planarizing structure for lift-off technique |
US4523372A (en) * | 1984-05-07 | 1985-06-18 | Motorola, Inc. | Process for fabricating semiconductor device |
US4519872A (en) * | 1984-06-11 | 1985-05-28 | International Business Machines Corporation | Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes |
US4575402A (en) * | 1985-02-13 | 1986-03-11 | Hewlett-Packard Company | Method for fabricating conductors in integrated circuits |
-
1986
- 1986-03-05 KR KR1019870701002A patent/KR940000750B1/ko not_active IP Right Cessation
- 1986-03-05 EP EP86902001A patent/EP0259490B1/de not_active Expired - Lifetime
- 1986-03-05 WO PCT/JP1986/000113 patent/WO1987005441A1/ja active IP Right Grant
- 1986-03-05 DE DE3689971T patent/DE3689971T2/de not_active Expired - Fee Related
- 1986-03-31 US US06/846,090 patent/US4757033A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO1987005441A1 (en) | 1987-09-11 |
KR940000750B1 (ko) | 1994-01-28 |
EP0259490B1 (de) | 1994-07-13 |
EP0259490A1 (de) | 1988-03-16 |
DE3689971T2 (de) | 1994-12-08 |
US4757033A (en) | 1988-07-12 |
KR880701968A (ko) | 1988-11-07 |
EP0259490A4 (en) | 1990-09-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |