JPS60113455A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

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Publication number
JPS60113455A
JPS60113455A JP58219446A JP21944683A JPS60113455A JP S60113455 A JPS60113455 A JP S60113455A JP 58219446 A JP58219446 A JP 58219446A JP 21944683 A JP21944683 A JP 21944683A JP S60113455 A JPS60113455 A JP S60113455A
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JP
Japan
Prior art keywords
layer
semiconductor
dielectric layer
transistor
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58219446A
Other languages
English (en)
Inventor
Kiyoshi Tsukuda
佃　清
Mitsuru Hirao
充 平尾
Osamu Saito
修 斉藤
Tokuo Watanabe
篤雄 渡辺
Takahide Ikeda
池田　隆英
Tatsuya Kamei
亀井　達弥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58219446A priority Critical patent/JPS60113455A/ja
Priority to EP84114151A priority patent/EP0147626A3/en
Publication of JPS60113455A publication Critical patent/JPS60113455A/ja
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置に係９、特に、同一半導体基板上に
バイポーラトランジスタと相補形電界効果形トランジス
タ（以下ＣＭＯ８）ランジスタと略す）ｆｔ形成した半
導体集積回路装置において、各々のトランジスタ間の相
互作用をなくした半導体集積回路装置を提供するにある
。
〔発明の背景〕
一般に、バイポーラトランジスタとＣＭＯ）ランジスタ
を同一基板上に形成した集積回路装置では各々の素子間
に寄生のトランジスタやサイリスタが形成されるため誤
動作しやすく１種々の対策がなされている。
第１図は、その−例を示す。第１図において１はＰ型基
板、２はＮ＋埋込み層％３はＮ型エピタキシャル層、４
はバイポーラ領域とＭＯ８領域を分離するための高濃度
のＰ型層、５はＮチャンネルＭＯ８ｆｆｉ形成するＰ型
ウニイル、６，７．８はバイポーラトランジスタのベー
ス、エミッタ、コレクタ、１０．１１はＭＯＳ）ランジ
スタのゲート％　１２．１３はＮＭＯ８）ランジスタの
ソース。
ドレイン、１４．１５はＰＭＯＳトランジスタのソース
、ドレイン％　１６は高濃度Ｐ型層でＭＯＳトランジス
タ間を分離するためのチャンネルストッパ、１７は表面
保護用のシリコン酸化膜である。
第１図において、各素子間はＰＮ接合によって分離して
いる。たとえば、バイポーラ部とＭＯ８部は高濃度のＰ
型層４で分離されているが、バイポーラ部のエピタキシ
ャル層３とＭＯ８ｉエピタキシャル層３はＰ型層４を介
してｎｐｎ）ランジスタ構造となる。また％ＮＭＯ８，
ＰＭＯ８間はＰ型層１６で分離しているが、ＮＭＯ８，
ソース。
ドレイン１２，１３．エピタキシャル層３、ＰＭＯＳソ
ース、ドレイン１４．１５の間はサイリスタ構造となる
ため各素子間で誤動作しゃ丁い。
このため、Ｐ型層４，１６はできるだけ高濃度にするよ
うな方策が採られているが、ＰＮ接合で分離するかぎり
完全に素子間全分離することは不可能である。
〔発明の目的〕
本発明の目的は、素子間の寄生効果を完全に除去し、同
一基板上にバイポーラトランジスタとＣＭ、Ｏ８）ラン
ジスタを形成した半導体集積回路装置を提供するにある
。
〔発明の実施例〕
以下、実施例を用いて本発明の装置全詳細に説明する。
第２図は本発明の一実施例を示す。第２図は、バイポー
ラトランジスタとＣＭＯＳトランジスタ全同一基板上に
形成した一断面を示す。Ｐ型半導体基板１の主表面に第
一の誘電体層２を形成する。
次に、将来バイポーラトランジスタが形成されるべき領
域全部分的に第一の誘電体層２に開孔部３全形成する。
さらに、開孔部２に、選択的にＮ１埋込み層４を形成す
る。第一の誘電体層２とＮ１埋込み層４全形成したＰ型
半導体基板１の主表面に、第二の半導体層５０を形成す
る。第二の半導体層４は１通常のエピタキシャル法で形
成した場合はその同伴によって、単結晶領域３（Ｎ＋埋
込み層上）には良質な単結晶半導体層が、第一の誘電体
層２の上には多結晶半導体層のそれぞれ形成される。
次に、Ｎ＋埋込み層３の上に形成された単結晶半導体層
會取り囲み、且つ、将来ＭＯ８）ランジスタが形成され
る部分５１．５２’に除き、第一の誘電体層２に達する
まで第二誘電体６を形成する。
次に、ＭＯＳトランジスタ形成領域５１．５２’！５レ
ザーアニール等により単結晶化する。第一の誘電体層２
上の多結晶半導体層の単結晶化は第二誘電体層６を形成
する前に行なっても、その後の効果は同じである。
以上のようにして形成された半導体基板１０表面に通常
の半導体製造プロセスにより良質の単結晶領域４にバイ
ポーラトランジスタを多結晶ヲ単結晶化した領域５１．
５２にＣＭＯＳトランジスタ全形成することにより完全
に絶縁分離されたバイポーラトランジスタと、ＣＭＯＳ
トランジスタを同一基板上に形成することが可能である
。
一般に、バイポーラトランジスタは、その性能上、良質
な単結晶が必要であシ２本発明によれば。
バイポーラ部は良質なエピタキシャル層上に、Ｍ２Ｓ部
は、多結晶を再結晶化した単結晶上にそれぞれ形成され
、かつ、バイポーラ部とＭ２Ｓ部を完全に誘電体で分り
できるため従来のものよシ性能が向上する。
第３図は５本発明の半導体集積回路用絶縁基板の製造方
法を示す。（ａ）は、Ｐ型半導体基板１の主表面上に高
濃度Ｐ型層２を形成する。高濃度Ｐ型層は環状に形成さ
れ、高濃度Ｐ型層に囲まれて領域上にバイポーラトラン
ジスタが形成される。次に、基板１の表面上に第一の誘
電体層ｆｓｉ０２゜８ｉｓＮ４　等）３を形成し、高濃
度Ｐ型層で取シ囲まれた領域上の第一の誘電体層をホト
エツチング等の方法により除去し、開孔部４全形成する
。第一の誘電体層全マスクとして開孔部に高濃度Ｎ型層
５を形成する。
（ｂ）は、半導体基板１の主表面の高濃度Ｎ型層（単結
晶層）５および、第一の誘電体層３上にエピタキシャル
法により第二の半導体層を形成する。
エピタキシャル層は高濃度Ｎ型層（単結晶層）５の上に
は単結晶の第二の半導体層６が形成される。
また、第一の誘電体層３の上には多結晶の第二半導体層
７１．７２が形成される。第二の半導体層６．７１．７
２は低濃度のＮ型であることが望ましい。
（Ｃ）は、第二半導体層６，７１．７２の表面に窒化シ
リコン膜（Ｓ　１３Ｎ４）　ｋ形成し、ホトエツチング
法により５Ｌ３Ｎ４膜８１，８２．８３を残す。
５ｊｓＮ４膜８１は第二半導体層６の上に形成される。
また、Ｓｉ３Ｎ４膜８２．８３は第一の誘電体層上に形
成された第二半導体層７２の上に形成てれる。
（ｄ）は、Ｓｉ３Ｎ４膜８１，８２，８３をマスクとし
て通常の熱酸化法により５ｉｓＮ４膜のない部分全第一
の誘電体層２に達するまで選択的に酸化膜を形成して第
二半導体領域６，１０１，１０２を絶縁物で完全に分離
する。しかし、第二半導体領域１０１，１０２は多結晶
半導体であるために単結晶化する必要がある。
（ｅ）は、（ｄ）で分離された第二半導体層１０１゜１
０２全単結晶化するために基板１の主表面に熱分解法等
により５ｉＯｚ膜１１を形成する。絶縁膜１１は第二半
導体層１０１，１０２’ｅ熱溶融法により単結晶化する
ときの蒸発を防止する役目全もつ。半導体基板１の主表
面側より加熱し、他の表面を冷却すると、高濃朋Ｎ形層
５上の第二半導体層（単結晶）６と第一の誘電体層３上
の第二半導体層（多結晶半導体）１０１，１０２とでは
Ｐ型半導体基板１への熱伝導の違いにより、第二半導体
層６を、第二半導体層１０１，１０２の方が高温となる
ため１０１および１０２のみを溶融を、再結晶化するこ
とによ、！ＤＩＯＬ、１０２’に単結晶化し、単結晶層
１０１１．１０２１が形成される。
その後、５ｉＯｚ膜１１全弗化水素酸と弗化アンモニュ
ム混合液等によりエツチングする。このとき、絶縁分離
用に形成さした酸化膜９１，９２，９３゜９４の表面を
、同時に、第二半導体層６，１０１１゜１０２１　と同
等の厚さになるまでエツチングし、その後、第二半導体
層上に形成された窒化シリコン膜８１，８２．８３全除
去しくｆ）に示すような誘電体で完全に分離された半導
体集積回路用基板が児成さ扛る。
【図面の簡単な説明】
第１図は従来のバイポーラトランジスタと０ＭＯ８）ラ
ンジスタを同一基板に形成した断面図、第２図は、本発
明の一実施例の断面図、第３図は誘電体で完全に分離さ
′ｎた半導体集積回路用基板の製造方法の説明図である
。 ５１．５２・・・ＭＯＳ）ランジスタ形成領域。 矛３月 第１頁の続き ０発　明　者　池　１）　隆　英　日立市幸町３丁目所
内 ０発　明　者　亀　井　達　弥　日立市幸町３丁目所内

Claims (1)

    【特許請求の範囲】
  1. １、第一半導体基板の主表面に、第一の誘電体層を形成
    し、前記第一の誘電体層を部分的に除去し、第二半導体
    層を形成した半導体基板上の第二半導体層上にバイポー
    ラトランジスタを、前記第一誘電体上の第二半導体層上
    に相補形ＭＯ８）ランジスタをそれぞれ形成し、さらに
    、各素子間を前記第一の誘電体層に達するまで第二の誘
    電体層を形成して絶縁分離したこと全特徴とする半導体
    集積回路装置。
JP58219446A 1983-11-24 1983-11-24 半導体集積回路装置 Pending JPS60113455A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58219446A JPS60113455A (ja) 1983-11-24 1983-11-24 半導体集積回路装置
EP84114151A EP0147626A3 (en) 1983-11-24 1984-11-23 Semiconductor device comprising bipolar and mos transistors, and method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58219446A JPS60113455A (ja) 1983-11-24 1983-11-24 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPS60113455A true JPS60113455A (ja) 1985-06-19

Family

ID=16735534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58219446A Pending JPS60113455A (ja) 1983-11-24 1983-11-24 半導体集積回路装置

Country Status (2)

Country Link
EP (1) EP0147626A3 (ja)
JP (1) JPS60113455A (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61184843A (ja) * 1985-02-13 1986-08-18 Toshiba Corp 複合半導体装置とその製造方法
JPS6276645A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 複合半導体結晶体構造
KR900001062B1 (ko) * 1987-09-15 1990-02-26 강진구 반도체 바이 씨 모오스 장치의 제조방법
JPH01179342A (ja) * 1988-01-05 1989-07-17 Toshiba Corp 複合半導体結晶体
JPH02102569A (ja) * 1988-10-12 1990-04-16 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
DE3905149A1 (de) * 1989-02-20 1990-08-30 Fraunhofer Ges Forschung Leistungsschaltung mit einer integrierten cmos- oder bipolar-schaltung und verfahren zum herstellen einer integrierten schaltung
US5244827A (en) * 1991-10-31 1993-09-14 Sgs-Thomson Microelectronics, Inc. Method for planarized isolation for cmos devices
DE4204004A1 (de) * 1992-02-12 1993-08-19 Daimler Benz Ag Verfahren zur herstellung einer halbleiterstruktur mit vertikalen und lateralen halbleiterbauelementen und nach dem verfahren hergestellte halbleiterstruktur
DE69931890T2 (de) * 1999-04-06 2007-01-11 Stmicroelectronics S.R.L., Agrate Brianza Integrierter Leistungsschaltkreis mit vertikalem Stromfluss und dessen Herstellungsverfahren
EP1193752A1 (en) * 2000-09-28 2002-04-03 Motorola, Inc. Method to form a localized silicon-on-insulator structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1439725A1 (de) * 1964-09-17 1968-11-28 Telefunken Patent Verfahren zur Herstellung separierter Halbleiterbereiche mit geringer Nebenschlusskapazitaet in einer mikrominiaturisierten Schaltungsanordnung
US4016596A (en) * 1975-06-19 1977-04-05 International Business Machines Corporation High performance integrated bipolar and complementary field effect transistors

Also Published As

Publication number Publication date
EP0147626A3 (en) 1987-08-12
EP0147626A2 (en) 1985-07-10

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