FR2687008B1 - Procede de fabrication de structures actives et dispositifs semiconducteurs ainsi obtenus. - Google Patents

Procede de fabrication de structures actives et dispositifs semiconducteurs ainsi obtenus.

Info

Publication number
FR2687008B1
FR2687008B1 FR9201293A FR9201293A FR2687008B1 FR 2687008 B1 FR2687008 B1 FR 2687008B1 FR 9201293 A FR9201293 A FR 9201293A FR 9201293 A FR9201293 A FR 9201293A FR 2687008 B1 FR2687008 B1 FR 2687008B1
Authority
FR
France
Prior art keywords
semiconductor devices
devices obtained
active structures
manufacturing active
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9201293A
Other languages
English (en)
Other versions
FR2687008A1 (fr
Inventor
Patrick Launay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to FR9201293A priority Critical patent/FR2687008B1/fr
Priority to EP93400263A priority patent/EP0557152A1/fr
Publication of FR2687008A1 publication Critical patent/FR2687008A1/fr
Application granted granted Critical
Publication of FR2687008B1 publication Critical patent/FR2687008B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/746—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts for AIII-BV integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)
FR9201293A 1992-02-05 1992-02-05 Procede de fabrication de structures actives et dispositifs semiconducteurs ainsi obtenus. Expired - Fee Related FR2687008B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9201293A FR2687008B1 (fr) 1992-02-05 1992-02-05 Procede de fabrication de structures actives et dispositifs semiconducteurs ainsi obtenus.
EP93400263A EP0557152A1 (fr) 1992-02-05 1993-02-03 Procédé de fabrication de structures actives et dispositifs semiconducteurs ainsi obtenus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9201293A FR2687008B1 (fr) 1992-02-05 1992-02-05 Procede de fabrication de structures actives et dispositifs semiconducteurs ainsi obtenus.

Publications (2)

Publication Number Publication Date
FR2687008A1 FR2687008A1 (fr) 1993-08-06
FR2687008B1 true FR2687008B1 (fr) 2001-06-22

Family

ID=9426361

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9201293A Expired - Fee Related FR2687008B1 (fr) 1992-02-05 1992-02-05 Procede de fabrication de structures actives et dispositifs semiconducteurs ainsi obtenus.

Country Status (2)

Country Link
EP (1) EP0557152A1 (fr)
FR (1) FR2687008B1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6276645A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 複合半導体結晶体構造
DE3727517C2 (de) * 1987-08-18 1995-06-01 Licentia Gmbh Verfahren zur Herstellung isolierter Halbleiterbereiche in einem Halbleiterkörper und damit hergestellte strukturierte Halbleiterkörper
JP2619407B2 (ja) * 1987-08-24 1997-06-11 株式会社日立製作所 半導体装置の製造方法
US4929996A (en) * 1988-06-29 1990-05-29 Texas Instruments Incorporated Trench bipolar transistor
US4910164A (en) * 1988-07-27 1990-03-20 Texas Instruments Incorporated Method of making planarized heterostructures using selective epitaxial growth

Also Published As

Publication number Publication date
FR2687008A1 (fr) 1993-08-06
EP0557152A1 (fr) 1993-08-25

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Legal Events

Date Code Title Description
ST Notification of lapse