DE102015103318B4 - Halbleiter-Bauelement mit einer Passivierungsschicht und Verfahren zum Herstellen eines solchen - Google Patents

Halbleiter-Bauelement mit einer Passivierungsschicht und Verfahren zum Herstellen eines solchen Download PDF

Info

Publication number
DE102015103318B4
DE102015103318B4 DE102015103318.6A DE102015103318A DE102015103318B4 DE 102015103318 B4 DE102015103318 B4 DE 102015103318B4 DE 102015103318 A DE102015103318 A DE 102015103318A DE 102015103318 B4 DE102015103318 B4 DE 102015103318B4
Authority
DE
Germany
Prior art keywords
layer
region
semiconductor component
contact electrode
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE102015103318.6A
Other languages
German (de)
English (en)
Other versions
DE102015103318A1 (de
Inventor
Christian Hecht
Andre Kabakow
Roland Rupp
Jens Peter Konrath
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE102015103318A1 publication Critical patent/DE102015103318A1/de
Application granted granted Critical
Publication of DE102015103318B4 publication Critical patent/DE102015103318B4/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H10D30/0512—Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H10D30/831—Vertical FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/34—Bipolar devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01354—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group IV materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
DE102015103318.6A 2014-03-07 2015-03-06 Halbleiter-Bauelement mit einer Passivierungsschicht und Verfahren zum Herstellen eines solchen Active DE102015103318B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/200,732 US20150255362A1 (en) 2014-03-07 2014-03-07 Semiconductor Device with a Passivation Layer and Method for Producing Thereof
US14/200,732 2014-03-07

Publications (2)

Publication Number Publication Date
DE102015103318A1 DE102015103318A1 (de) 2015-09-10
DE102015103318B4 true DE102015103318B4 (de) 2023-09-21

Family

ID=53884150

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102015103318.6A Active DE102015103318B4 (de) 2014-03-07 2015-03-06 Halbleiter-Bauelement mit einer Passivierungsschicht und Verfahren zum Herstellen eines solchen

Country Status (4)

Country Link
US (3) US20150255362A1 (cg-RX-API-DMAC10.html)
JP (2) JP2015170857A (cg-RX-API-DMAC10.html)
CN (1) CN104900685B (cg-RX-API-DMAC10.html)
DE (1) DE102015103318B4 (cg-RX-API-DMAC10.html)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017174608A1 (en) * 2016-04-06 2017-10-12 Abb Schweiz Ag Semiconductor chip with moisture protection layer
CN106252244A (zh) * 2016-09-22 2016-12-21 全球能源互联网研究院 一种终端钝化方法及半导体功率器件
DE102017100109A1 (de) * 2017-01-04 2018-07-05 Infineon Technologies Ag Halbleitervorrichtung und verfahren zum herstellen derselben
JP6828472B2 (ja) 2017-02-01 2021-02-10 富士電機株式会社 半導体装置
JP6528793B2 (ja) 2017-02-22 2019-06-12 サンケン電気株式会社 半導体装置
JP6558385B2 (ja) * 2017-02-23 2019-08-14 トヨタ自動車株式会社 半導体装置の製造方法
JP6846687B2 (ja) * 2017-09-12 2021-03-24 パナソニックIpマネジメント株式会社 半導体装置およびその製造方法
US10332817B1 (en) 2017-12-01 2019-06-25 Cree, Inc. Semiconductor die with improved ruggedness
DE102019100130B4 (de) * 2018-04-10 2021-11-04 Infineon Technologies Ag Ein halbleiterbauelement und ein verfahren zum bilden eines halbleiterbauelements
DE102019131238B4 (de) * 2018-12-06 2025-09-18 Infineon Technologies Ag Passivierungsstruktur enthaltende halbleitervorrichtung und herstellungsverfahren
US10957664B2 (en) * 2019-05-29 2021-03-23 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US12369381B2 (en) 2019-09-30 2025-07-22 Rohm Co., Ltd. Semiconductor device
US20220189840A1 (en) * 2020-12-16 2022-06-16 Stmicroelectronics Pte Ltd Passivation layer for an integrated circuit device that provides a moisture and proton barrier
CN117043964A (zh) * 2021-03-26 2023-11-10 罗姆股份有限公司 半导体装置
CN113921588A (zh) * 2021-09-01 2022-01-11 格力电器(合肥)有限公司 半导体器件及其制备方法
JPWO2023067925A1 (cg-RX-API-DMAC10.html) * 2021-10-21 2023-04-27
IT202100027101A1 (it) * 2021-10-21 2023-04-21 St Microelectronics Srl Procedimento di fabbricazione di un dispositivo elettronico di carburo di silicio e dispositivo elettronico di carburo di silicio
DE102024203635A1 (de) * 2024-04-18 2025-10-23 Infineon Technologies Ag Halbleiterchip und verfahren zum herstellen desselben

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6544904B1 (en) 2001-12-17 2003-04-08 Ryoden Semiconductor System Engineering Corporation Method of manufacturing semiconductor device
US20060220081A1 (en) 2005-03-30 2006-10-05 Fujitsu Limited Semiconductor device and manufacturing method of the same
US20070001176A1 (en) 2005-06-29 2007-01-04 Ward Allan Iii Environmentally robust passivation structures for high-voltage silicon carbide semiconductor devices
US20080284009A1 (en) 2007-05-16 2008-11-20 Heikyung Min Dimple free gold bump for drive IC
US20110018128A1 (en) 2009-07-22 2011-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for reducing dielectric layer delamination
US20110193232A1 (en) 2010-02-08 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure for semiconductor substrate and method of manufacture

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150830A (en) * 1980-04-25 1981-11-21 Hitachi Ltd Semiconductor device
DE69514588T2 (de) * 1994-07-29 2000-06-21 Stmicroelectronics, Inc. Verfahren zum Testen und Reparieren eines integrierten Schaltkreises und zum Herstellen einer Passivierungsstruktur
US5994762A (en) * 1996-07-26 1999-11-30 Hitachi, Ltd. Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof
JP3354424B2 (ja) * 1997-02-27 2002-12-09 三洋電機株式会社 半導体装置および半導体装置の製造方法
KR100252039B1 (ko) * 1997-10-06 2000-04-15 윤종용 자기정렬 콘택홀 형성방법
US6022791A (en) * 1997-10-15 2000-02-08 International Business Machines Corporation Chip crack stop
SE9704150D0 (sv) 1997-11-13 1997-11-13 Abb Research Ltd Semiconductor device of SiC with insulating layer a refractory metal nitride layer
US6246076B1 (en) 1998-08-28 2001-06-12 Cree, Inc. Layered dielectric on silicon carbide semiconductor structures
JP2001094056A (ja) * 1999-09-24 2001-04-06 Victor Co Of Japan Ltd 半導体集積回路及びその製造方法
US6646347B2 (en) * 2001-11-30 2003-11-11 Motorola, Inc. Semiconductor power device and method of formation
JP2004095572A (ja) * 2002-08-29 2004-03-25 Hitachi Ltd 半導体装置およびその製造方法
JP2004273767A (ja) * 2003-03-10 2004-09-30 Nec Kansai Ltd 半導体のパッシベーション構造およびその製造方法
US20050224987A1 (en) * 2004-04-07 2005-10-13 Hortaleza Edgardo R Structure and method for contact pads having double overcoat-protected bondable metal plugs over copper-metallized integrated circuits
US7452803B2 (en) * 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
TWI278090B (en) * 2004-10-21 2007-04-01 Int Rectifier Corp Solderable top metal for SiC device
US7473999B2 (en) * 2005-09-23 2009-01-06 Megica Corporation Semiconductor chip and process for forming the same
JP4840849B2 (ja) * 2005-09-30 2011-12-21 新電元工業株式会社 半導体装置及び半導体装置の製造方法
US20070082475A1 (en) * 2005-10-12 2007-04-12 Dongbu Electronics Co., Ltd. Method for forming bonding pad and semiconductor device having the bonding pad formed thereby
US7659632B2 (en) * 2006-11-03 2010-02-09 Taiwan Seminconductor Manufacturing Co., Ltd. Solder bump structure and method of manufacturing same
CN101388407B (zh) * 2007-09-12 2011-12-14 万国半导体股份有限公司 逆沟槽的场效应晶体管结构
CN101452950A (zh) * 2007-12-04 2009-06-10 科达半导体有限公司 一种采用氮化硅(Si3N4)和掺磷氧化硅(PSG)复合薄膜隔离技术的IGBT功率器件及其制造工艺
US8143729B2 (en) * 2008-01-25 2012-03-27 International Rectifier Corporation Autoclave capable chip-scale package
KR101023080B1 (ko) * 2008-11-13 2011-03-24 주식회사 동부하이텍 반도체 소자의 금속 배선 및 그 형성 방법
US7999320B2 (en) * 2008-12-23 2011-08-16 International Business Machines Corporation SOI radio frequency switch with enhanced signal fidelity and electrical isolation
JP5559775B2 (ja) * 2009-04-30 2014-07-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9607955B2 (en) * 2010-11-10 2017-03-28 Cree, Inc. Contact pad
US20120299187A1 (en) * 2011-05-27 2012-11-29 Broadcom Corporation Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum Products
US8680587B2 (en) * 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
JP6063629B2 (ja) * 2012-03-12 2017-01-18 ローム株式会社 半導体装置および半導体装置の製造方法
JP5600698B2 (ja) * 2012-03-14 2014-10-01 株式会社 日立パワーデバイス SiC素子搭載パワー半導体モジュール
JP2013229455A (ja) * 2012-04-26 2013-11-07 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
JP2013239607A (ja) * 2012-05-16 2013-11-28 Mitsubishi Electric Corp 半導体装置
JP2014011342A (ja) * 2012-06-29 2014-01-20 Denso Corp 炭化珪素半導体装置
US8884342B2 (en) * 2012-08-29 2014-11-11 Infineon Technologies Ag Semiconductor device with a passivation layer
JP2014053393A (ja) * 2012-09-06 2014-03-20 Sumitomo Electric Ind Ltd ワイドギャップ半導体装置およびその製造方法
US8836133B2 (en) * 2012-10-12 2014-09-16 Freescale Semiconductor, Inc. Chip-level humidity protection
US20140110838A1 (en) * 2012-10-22 2014-04-24 Infineon Technologies Ag Semiconductor devices and processing methods
US9355958B2 (en) * 2013-10-31 2016-05-31 Infineon Technologies Ag Semiconductor device having a corrosion-resistant metallization and method for manufacturing thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6544904B1 (en) 2001-12-17 2003-04-08 Ryoden Semiconductor System Engineering Corporation Method of manufacturing semiconductor device
US20060220081A1 (en) 2005-03-30 2006-10-05 Fujitsu Limited Semiconductor device and manufacturing method of the same
US20070001176A1 (en) 2005-06-29 2007-01-04 Ward Allan Iii Environmentally robust passivation structures for high-voltage silicon carbide semiconductor devices
US20080284009A1 (en) 2007-05-16 2008-11-20 Heikyung Min Dimple free gold bump for drive IC
US20110018128A1 (en) 2009-07-22 2011-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for reducing dielectric layer delamination
US20110193232A1 (en) 2010-02-08 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure for semiconductor substrate and method of manufacture

Also Published As

Publication number Publication date
DE102015103318A1 (de) 2015-09-10
US20220005742A1 (en) 2022-01-06
US11854926B2 (en) 2023-12-26
CN104900685B (zh) 2019-10-22
CN104900685A (zh) 2015-09-09
JP6691076B2 (ja) 2020-04-28
US20150255362A1 (en) 2015-09-10
JP2017224838A (ja) 2017-12-21
JP2015170857A (ja) 2015-09-28
US20190252282A1 (en) 2019-08-15
US11158557B2 (en) 2021-10-26

Similar Documents

Publication Publication Date Title
DE102015103318A1 (de) Halbleiter-Bauelement mit einer Passivierungsschicht und Verfahren zum Herstellen eines solchen
DE102013022570B4 (de) Halbleiterbauelement und verfahren zu seiner herstellung
DE112013006308B4 (de) Siliziumcarbid - halbleitervorrichtung und verfahren zu ihrer herstellung
DE112014003481B4 (de) GaN-TRANSISTOREN MIT POLYSILIZIUMSCHICHTEN ZUR BILDUNG VON ZUSÄTZLICHEN KOMPONENTEN UND VERFAHREN ZU DEREN HERSTELLUNG
DE102013022598B3 (de) Halbleiterbauelement und Verfahren zu seiner Herstellung
DE102011056157B4 (de) Verfahren zur Herstellung eines Halbleiterbauteils und Halbleiterbauteile mit isolierten Halbleitermesas
DE69129617T2 (de) Integrierte Schaltungsanordnung, insbesondere geeignet für Hochspannungsanwendungen
DE102014020009B4 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE102013217225B4 (de) Halbleiterbauelement mit einer Passivierungsschicht und Verfahren zu dessen Herstellung
DE112018003086B4 (de) Halbleitervorrichtung und verfahren zur herstellung einer halbleitervorrichtung
DE102014115174B4 (de) Halbleitervorrichtung mit einer korrosionsbeständigen metallisierung und verfahren zu ihrer herstellung
DE102012110133B4 (de) Ein Halbleiterbauelement mit einem Durchkontakt und Herstellungsverfahren dafür
DE102013002986B4 (de) Integrierte Schottky-Diode für HEMTS und Verfahren zu deren Herstellung
DE102016107714B4 (de) Halbleitervorrichtung mit einer Transistorzelle, die einen Sourcekontakt in einem Graben umfasst, Verfahren zum Herstellen der Halbleitervorrichtung und integrierte Schaltung
DE10297177T5 (de) Graben-FET mit selbstausgerichteter Source und selbstausgerichtetem Kontakt
EP1151478A1 (de) Mos-leistungsbauelement und verfahren zum herstellen desselben
DE102014105339A1 (de) Halbleitervorrichtung und verfahren zum herstellen einer halbleitervorrichtung
DE102005041793B4 (de) Top Drain MOSgated Einrichtung und Herstellungsprozess dafür
DE102015105679B4 (de) Halbleitervorrichtung, integrierte schaltung und verfahren zum herstellen der halbleitervorrichtung
DE102011004476B4 (de) Halbleitereinrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
DE102015212048A1 (de) Transistor mit hoher Elektronenbeweglichkeit
DE102023118803A1 (de) Integrierte Galliumnitrid-Transistoren mit hoher Elektronenbeweglichkeit im Verarmungs- und Anreicherungsmodus
DE102021134457A1 (de) Verfahren und strukturen zum kontaktieren des abschirmleiters in einer halbleitervorrichtung
DE102020112069A1 (de) Source-leckstromunterdrückung durch source-umgebende gate-struktur
DE102015106693A1 (de) Superjunction-Halbleitervorrichtung mit Übergangsabschlusserstreckungsstruktur und Verfahren zur Herstellung

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R083 Amendment of/additions to inventor(s)
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R130 Divisional application to

Ref document number: 102015017489

Country of ref document: DE

R020 Patent grant now final
R082 Change of representative
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0029450000

Ipc: H10D0064620000