CN104900685A - 具有钝化层的半导体器件及用于制作其的方法 - Google Patents

具有钝化层的半导体器件及用于制作其的方法 Download PDF

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CN104900685A
CN104900685A CN201510099304.2A CN201510099304A CN104900685A CN 104900685 A CN104900685 A CN 104900685A CN 201510099304 A CN201510099304 A CN 201510099304A CN 104900685 A CN104900685 A CN 104900685A
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layer
semiconductor device
contact electrode
ground floor
semiconductor
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CN104900685B (zh
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C.黑希特
A.卡巴科夫
J.P.康拉特
R.鲁普
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及具有钝化层的半导体器件及用于制作其的方法。一种半导体器件包括具有第一表面的半导体本体、在第一表面上的接触电极、和在第一表面上与接触电极相邻并且与接触电极部分重叠的钝化层。该钝化层包括具有第一层和第二层的层堆叠，该第一层包括在第一表面上的氧化物，该第二层包括在第一层上的氮化物。

Description

具有钝化层的半导体器件及用于制作其的方法
技术领域
本发明的实施例涉及半导体器件，并且具体涉及具有钝化层的功率半导体器件。
背景技术
功率半导体器件，例如功率二极管或功率晶体管，能够阻断几十伏、几百伏或甚至几千伏（kV）的高电压。高电压阻断能力与半导体本体中的高电场相关联，在该半导体本体中集成了半导体器件的有源区。尤其处于阻断状态的半导体本体的表面（在此出现高电场）非常敏感并且需要合适的处理以便防止可能导致电压阻断能力下降的退化效应。这种处理可以包括在所述表面上形成钝化层。然而，在某些情况下，例如诸如在湿热环境下，常规钝化层可能遭受退化，该退化可能引起半导体本体的腐蚀和/或接触半导体本体的金属化物的腐蚀。
需要提供一种具有在机械和化学上非常鲁棒的钝化层的半导体器件。
发明内容
第一实施例涉及一种半导体器件。该半导体器件包括具有第一表面的半导体本体、在第一表面上的接触电极、和在第一表面上与接触电极相邻并且与接触电极部分重叠的钝化层。该钝化层包括具有第一层和第二层的层堆叠，该第一层包括在第一表面上的氧化物，该第二层包括在第一层上的氮化物。
第二实施例涉及一种方法。该方法包括提供具有第一表面的半导体本体，在第一表面上形成接触电极，以及在第一表面上形成与接触电极相邻并且与接触电极部分重叠的钝化层。该钝化层包括具有第一层和第二层的层堆叠，该第一层包括在第一表面上的氧化物，该第二层包括在第一层上的氮化物。
附图说明
现在将参考各图解释实例。各图用于说明基本原理，因此仅示出了用于理解基本原理必须的各方面。各图将不按比例。在图中，相同的参考字符表示类似的特征。
图1示出包括在半导体本体的第一表面上的钝化层的半导体器件的一个实施例的垂直截面图。
图2示出包括在半导体本体的第一表面上的钝化层的半导体器件的另一个实施例的垂直截面图。
图3示出包括在半导体本体的第一表面上的钝化层的半导体器件的一个实施例的自上而下的视图。
图4示出包括在半导体本体的第一表面上的钝化层的半导体器件的另一个实施例的垂直截面图。
图5示出包括在半导体本体的第一表面上的钝化层、软密封层和外壳的半导体器件的一个实施例的垂直截面图。
图6示出包括pn结的半导体器件的垂直截面图。
图7示出被实施为双极二极管的半导体器件的垂直截面图。
图8示出被实施为肖特基二极管的半导体器件的垂直截面图。
图9示出被实施为MOS晶体管的半导体器件的垂直截面图。
图10示出被实施为JFET的半导体器件的垂直截面图。
图11A-11C示出用于制作具有钝化层的半导体器件的方法的一个实施例。
图12A-12B示出用于制作具有钝化层的半导体器件的方法的另一个实施例。
具体实施方式
在下面的详细描述中，参考附图，这些附图构成了该详细描述的一部分，在这些图中借助图示示出了其中可以实践本发明的特定实施例。
图1和2示出半导体器件（例如功率半导体器件）的一部分的垂直截面图。该半导体器件包括具有第一表面101的半导体本体100。该半导体器件还包括在第一表面101上并邻接半导体本体100的接触电极2。
根据一个实施例，接触电极21包括下述中的至少一个：铝、钛、铜、铝合金、铜合金、铝-铜合金（例如AlCu或AlSiCu）。接触电极2可以包括一层，如图1中所示。根据图2中所示的另一实施例，接触电极2包括接触第一表面101的第一子层21和在第一子层21上的第二子层。根据一个实施例，第一子层21是钛（Ti）层并且第二子层22是下述之一：铝层、铜层、铝合金层、铜合金层和铝-铜合金层。参考图2，第一子层可以被实施为具有比第一子层21大的面积，使得在第二子层22下面的第一子层21突出到第二子层22以外。钝化层3与两个子层21、22都重叠。
接触电极2不完全覆盖第一表面101。钝化层3形成在第一表面101的与接触电极21相邻且不被接触电极21覆盖的那些区域中。钝化层保护半导体本体100的第一表面101并且提供半导体器件的长期稳定性。特别地，钝化层3防止或至少减少当半导体器件工作在潮湿气氛中时可能出现的退化过程。那些退化过程尤其可能出现在第一表面101的可能出现高电场的那些区域中。
参考图1，半导体本体100包括边缘表面102。边缘表面102在横向上使半导体本体100终止，其意味着在方向上基本平行于第一表面101。该边缘表面可以基本垂直于第一表面101。然而，根据一个实施例（在图1中用短划线示出），边缘表面102相对于半导体本体100的垂直方向倾斜（该垂直方向是基本垂直于第一表面101的方向）。
参考图1，钝化层3与接触电极2重叠，但是没有完全覆盖接触电极2。根据一个实施例，重叠d0在100微米（μm）和200微米之间。“重叠”d0是在背离接触电极2的外边缘的方向上钝化层3与接触电极重叠的距离。在接触电极2的没有被钝化层3覆盖的那些区域中，接触电极可以被接合线（未示出）等接触。
图1中所示的具有半导体本体100、在半导体本体100的第一表面101上的接触电极2和钝化层3的基本器件结构可以用不同的半导体器件来实施，并且不局限于一种具体类型的半导体器件。由此，在图1中，仅示出了半导体本体100，而没有示出在半导体本体100中实施的具体器件区域。在半导体本体100中的具体半导体器件和具体器件结构的一些实施例在下面参考图6-8来解释。
参考图1，钝化层3包括层堆叠。该层堆叠包括第一层31和第二层32，该第一层包括在第一表面上的氧化物，该第二层包括在第一层上的氮化物。根据一个实施例，该层堆叠还包括包含在第二层中的酰亚胺的第三层33。
根据一个实施例，在第一表面101上的第一层31的厚度d1是至少1.5微米（μm）或至少2.7微米。根据一个实施例，在第一表面上的第一层31的最大厚度是3.5微米。在第一层31与接触电极2重叠的那些区域中的第一层31的厚度可以基本上对应于在第一表面101上方的厚度。
根据一个实施例，第二层32的厚度d2是至少0.6微米（μm）或至少0.8微米。根据一个实施例，第二层32的最大厚度是1微米。在第二层32与接触电极2重叠的那些区域中的第二层32的厚度可以基本上对应于在第二层不与接触电极重叠的那些区域中的厚度。
根据一个实施例，第三层33的厚度d3是至少7微米（μm）、8微米、20微米或30微米。根据一个实施例，第三层33的最大厚度是50微米。在第三层33与接触电极2重叠的那些区域中的第三层33的厚度可以基本上对应于在第三层不与接触电极重叠的那些区域中的厚度。
半导体本体100可以包括常规半导体材料，例如IV族半导体、IV-IV族半导体、III-V族半导体或II-VI族半导体。IV族半导体的实例包括硅（Si）和锗（Ge）。IV-IV族半导体的实例包括碳化硅(SiC)和锗化硅(SiGe)。III-V族半导体的实例包括砷化镓(GaAs)、氮化镓(GaN)、磷化镓(GaP)、磷化铟(InP)、铟镓氮(InGaN)和铟镓砷(InGaAs)。II-VI族半导体的实例包括碲化镉(CdTe)、镉汞碲(CdHgTe)和镉镁碲(CdMgTe)。根据一个实施例，第一层31中的氧化物是氧化硅（二氧化硅，SiO2）以及第二层32中的氮化物是氮化硅（Si3N4）。氧化物和氮化物的这种选择可以与半导体本体100的半导体材料的具体类型无关。
第一层31可以包括两个或更多个子层，其中每个子层包括氧化物。根据一个实施例，第一层包括下面的氧化层中的至少一个、未掺杂的硅酸盐玻璃（USG）、磷掺杂的硅酸盐玻璃(PSG)、硼掺杂的硅酸盐玻璃(BSG)或硼和磷掺杂的硅酸盐玻璃(BPSG)。根据一个实施例，第一层31包括这些玻璃中的仅一个。根据另一实施例，第一层31包括具有不同氧化物的两个或更多个子层。根据一个实施例，第一层31是沉积层，例如PECVD（等离子体增强化学气相沉积）层。根据另一实施例，第一层31是溅射层，其是在溅射工艺中形成的层。
在横向方向上，钝化层3可以远离边缘表面102结束（如图1中所示）。然而，根据一个实施例（在图1中用短划线示出），钝化层3在横向方向上延伸到边缘表面102。
根据一个实施例，第二层32是PECVD氮化硅层。根据另一实施例，第二层32是溅射层。
参考图1和2，钝化层3可以使第一表面101的多个部分不被覆盖。例如，在其中集成了功率半导体器件和低电压半导体器件的半导体本体中，钝化层可以不覆盖第一表面101的在其下面集成了低电压器件的的那些区域。然而，这仅是实例。根据又一实施例（在图1和2中用短划线示出），钝化层3完全覆盖在接触电极2和半导体本体100的边缘表面102之间的半导体本体100上的第一表面101。
然而，在这些实施例的每一个中，钝化层3可以完全包围第一表面101上的接触电极21。这在图3中被示出，其示出完整的半导体本体100的顶视图（而图1和2仅示出半导体本体100的靠近边缘表面102的一部分）。
图4示出根据另一实施例的半导体器件的一部分的垂直截面图。在图1和2中所示的实施例中，第一层31、第二层32和第三层33的边缘基本上对准。在图4中所示的实施例中，第三层33的边缘331、332远离第二层32的边缘321、322。在该实施例中第一层31和第二层32的边缘基本上对准。
在图4中，参考字符321、331分别表示第二层32和第三层33的内边缘，其是面对接触电极2的边缘，并且参考字符322、332分别表示第二层32和第三层33的外边缘，其是背离接触电极2的边缘。参考图4，第三层33的内边缘331远离第二层32的内边缘321，使得第二层32在接触电极2的方向上突出到第二层32以外。也就是，第三层33没有覆盖第二层32的内边缘321和第三层33的内边缘331之间的第二层32的部分。此外，第三层33的外边缘332远离第二层32的外边缘322，使得第二层32在边缘表面102的方向上突出到第二层32以外。也就是，第三层33没有覆盖第二层32的外边缘322和第三层33的外边缘332之间的第二层32的部分。第二层32的内边缘321和第三层33的内边缘331之间的距离d4例如在20微米（μm）和40微米之间。第二层32的外边缘322和第三层33的外边缘332之间的距离d5例如在20微米（μm）和40微米之间。
尽管在图4中示出的实施例中，在第二层32和第三层33的内边缘321、331和外边缘322、332之间存在距离，但这仅是实例。根据另一实施例，仅在第二层32和第三层33的内边缘321、331和外边缘322、332之一之间存在距离。
在钝化层3中，包括第一层31的氧化物和包括第二层32的氮化物充当湿气屏障，其保护第一表面101和接触电极2的被钝化层覆盖的那些区域免受湿气和腐蚀影响。接触电极2和/或半导体本体100的腐蚀可能是由分别沿第三、第二和第一层33、32、32行进到接触电极2和第一表面101的移动离子引起的。在图4中所示的实施例中，其中在第二层32和第三层33的边缘之间存在距离，对那些可以沿第三层33的表面从第三层分别行进到接触电极2和第一表面101的移动离子存在较长的距离。该较长的距离另外可以改善腐蚀保护。
参考图5，半导体器件另外可以包括软密封层61和外壳62。在图5中，仅示出软密封层61和外壳的一部分。软密封层61填充具有接触电极2和钝化层3的半导体100与外壳62之间的空间。该外壳可以包括开口，通过所述开口，接触引脚（图5中未示出）从外壳外面延伸到外壳里面。那些接触引脚允许从外部（即从外壳的外面）接触半导体器件。软密封层61包括例如硅树脂或硅胶。
外壳可以包括底部、侧壁621和盖622，其中在图5中仅示出一个侧壁621的一部分和盖622的一部分。底部（未示出）可以包括衬底，例如诸如DCB(直接铜接合)衬底或PCB(印刷电路板)。侧壁621和盖622可以包括电绝缘塑料材料。侧壁621和盖622可以被实施为两个分离部分。这允许半导体本体100如下述被包装在外壳62中。首先，提供开口外壳62，即不具有盖的外壳。然后，将半导体本体100插入外壳中，用软密封层61填充该开口外壳，并且通过在侧壁621的顶部上安装盖622来封闭该外壳。
上面利用半导体本体100、接触电极2和钝化层3解释的布局可以用在多个不同半导体器件中。图6示出具有参考图1解释的布局（然而也可以使用参考图2和4解释的布局之一）并且在半导体本体100中包括pn结的半导体器件的垂直截面图。该pn结形成在第一掺杂类型的掺杂的第一器件区域11和与第一掺杂类型互补的第二掺杂类型的掺杂的第二器件区域12之间。第二器件区域12电连接到接触电极2。第一器件区域11可以延伸到边缘表面102。此外，在钝化层3下面，第一器件区域11可以延伸到第一表面101。半导体本体100的其中形成pn结的区域可以被称为内部区域110，并且邻接该内部区域110的区域可以被称为外部区域或边缘区域120。边缘区域120可以从半导体本体100的内部区域110延伸到边缘表面102。然而，这仅是实例。根据又一实施例（未示出），另外的半导体区域可以邻接边缘区域120，例如其中实施低电压半导体器件或逻辑器件的半导体区域。
参考图6，pn结可以延伸到表面101并被钝化层3覆盖。也就是，接触电极2的边缘表面远离pn结延伸到第一表面101的位置。
可选地，半导体器件包括在钝化层3下面的边缘区域120中的边缘终止结构。边缘终止结构可以包括第二掺杂类型的JTE（结终止延伸）区域13（如所示）。另外，边缘终止结构可以包括第一掺杂类型的且比第一器件区域11更高掺杂的沟道截断区域14。JTE区域13和沟道截断区域14都邻接第一表面101并且在半导体本体100的水平（横向）方向上是远离的。根据一个实施例，钝化层3覆盖完整的边缘终止结构。也就是，在图6中所示的实施例中，钝化层3覆盖JTE区域13和沟道截断区域14。可以另外使用或代替JTE区域13使用其他类型的边缘终止结构，例如诸如包括场环和/或场板的边缘终止结构。
如图6中所示的半导体器件以及下面解释的半导体器件可以包括如参考图5解释的软密封层61和外壳。然而，这在图6和下面的图中未被示出。
之前解释的钝化层3适合用在高电压半导体器件中，例如具有几百伏或几千伏（kV）的电压阻断能力的半导体器件。钝化层3特别适合用在具有1 kV和更大的电压阻断能力的半导体器件中。
图6中所示的具有半导体本体100、接触器件区域11、12中的一个12的接触电极2和钝化层3的器件布局可以用在不同半导体器件中。下面参考图7-10解释四个可能的实施例。
参考图7，半导体器件可以被实施为双极二极管，特别是被实施为功率二极管。图7示出具有如参考图6解释的器件布局的功率二极管的垂直截面图。然而，钝化层3没有被详细示出（即没有示出层堆叠的各个层）并且没有示出可选的边缘终止结构。可以根据本文之前解释的实施例之一来实施钝化层3。
在图7中所示的二极管中，第一器件区域11形成二极管的基区，以及第二器件区域12形成第一发射极，其是二极管的n发射极和p发射极之一。根据一个实施例，基区11是n掺杂的，因此第二器件区域12是p掺杂的并且形成二极管的p发射极（阳极）。该二极管还包括第一掺杂类型的、比基区11更高掺杂的并且邻接基区11的第二发射区15。接触电极21电连接（欧姆连接）到二极管的第一发射极12和第一端子41。如果第一发射极是p发射极，则第一端子41形成阳极端子。二极管的第二发射极电连接到第二端子42。如果第二发射极是n发射极，则第二端子42形成阴极端子。
根据图8中所示的另一实施例，半导体器件被实施为肖特基二极管。肖特基二极管的器件布局基本上对应于双极二极管的器件布局，差别是省略了第一发射极12，接触电极2包括肖特基金属并接触基区11。肖特基金属的实例包括钛（Ti）、氮化钛、钼（Mo）和氮化钼。根据一个实施例，如图2中所示接触电极2包括两个子层21、22，据此至少接触基区11的第一子层21包括肖特基金属。第二子层可以包括铝、铜、或者铝和铜中的至少一个的合金。
参考图8，与基区11的掺杂类型互补的第二掺杂类型的JTE区域13可以延伸到接触电极下面并且电连接到接触电极。根据一个实施例，第二掺杂类型的并且比JTE区域13更高掺杂的接触区域16提供接触电极2和JTE区域13之间的欧姆接触。
图9示出MOS晶体管的一个实施例的垂直截面图。在该MOS晶体管中，第一器件区域11是漂移区并且第二器件区域12是体区。该MOS晶体管包括多个晶体管单元50。每个晶体管单元包括通过体区12与漂移区11分离的源区51、栅电极52和将栅电极52与源区51、体区12和漂移区11介电绝缘的栅极电介质53。各个晶体管单元50共享漂移区11和漏区14。栅电极52电连接到栅电极43并且通过绝缘层54与接触电极电绝缘。接触电极2形成源电极，连接到源区51和体区52，并连接到形成源极端子的第一端子41。漏区14连接到形成漏极端子的第二端子42。
MOS晶体管可以被实施为MOSFET。在这种情况下，漏区14具有与漂移区11相同的掺杂类型，但被更高掺杂。可替换地，MOS晶体管被实施为IGBT。在该情况下，漏区14被与漂移区11互补地掺杂。MOS晶体管可以被实施为n型或p型晶体管。在n型晶体管中，漂移区11和源区51是n掺杂的，而体区12是p掺杂的。在p型晶体管中，漂移区11和源区51是p掺杂的，而体区12是n掺杂的。
图10示出JFET（结型场效应晶体管）的一个实施例的垂直截面图。图10示出包括在第一表面101的区域中的内部区域110的一部分和边缘区域120的一部分的一部分。JFET与参考图9解释的MOS晶体管的不同之处在于源区51、体区12、漂移区11和漏区（未在图10中示出）具有相同的掺杂类型，其在n-JFET中是n型且在p-JFET中是p型。此外，代替栅电极，JFET包括与体区12的掺杂类型互补的掺杂类型的掺杂栅区。栅区52'邻接体区12并与其形成pn结。接触电极2电连接到源区51并且通过绝缘层54与栅区52'电绝缘。接触电极2形成JFET的源电极并连接到源极端子，并且栅区52'电连接到栅极端子43。类似于MOS晶体管，JFET可以包括多个晶体管单元50，其均包括源区51、体区12和栅区52'，并且其共享漂移区11和漏区。
通过向栅区52'施加驱动电势来切断JFET，使得耗尽区从体区12和栅区52'之间的pn结扩大到体区12中并使体区耗尽以便中断源区52和漂移区11之间的导电沟道。如所示，体区12可以位于栅区52'和与栅区52'相同的掺杂类型并电连接到接触电极（源电极）2的掺杂区域之间。可替换地（未示出），体区12位于两个相邻的栅区之间。
参考图1-5解释的器件结构不局限于用在双极二极管、肖特基二极管、MOS晶体管或JFET中，而是也可以被实施在其他类型的半导体器件中，例如诸如BJT（双极结型晶体管）。
图11A-11C示出用于制作如本文之前参考图1和2解释的器件布局的方法的第一实施例。图9A-9C示意性地示出半导体本体100在制造过程的不同阶段的垂直截面图。
参考图11A，该方法包括在接触电极2和第一表面101的未被接触电极2覆盖的那些部分上形成第一前体层31'。第一前体层31'可以完全覆盖接触电极2和第一表面101的未被接触电极2覆盖的那些部分。在参考图11B和11C解释的刻蚀工艺之后，第一前体层31'形成第一层31。根据实施例，形成第一前体层31'包括PECVD工艺。可替换地，形成第一前体层31'包括溅射工艺。如上所述，第一层31可以包括具有不同材料成分的两个或更多个子层。由此，第一前体层31'可以包括具有不同材料成分的两个或更多个子层。那些子层可以被制作成一个在另一个之上。
在形成第一前体层31'之前，接触电极2的表面和/或半导体本体100的第一表面101可以通过例如溅射被粗糙化以便改善第一层分别对接触电极2和第一表面的粘附。
参考图11A，该方法还包括在第一前体层31'上形成第二前体层32'。第二前体层32'可以完全覆盖第一前体层31'。根据一个实施例，形成第二前体层32'包括PECVD工艺。可替换地，形成第二前体层32'包括溅射工艺。
参考图11B，该方法还包括在第二前体层32'上形成第三层33。形成第三层33可以包括形成完全覆盖第二前体层32'的第三前体层（未示出）以及图案化第三前体层以形成第三层33。图案化第三前体层可以包括光刻工艺，其中使用光刻掩模曝光并显影第三前体层（类似于常规的光致抗蚀剂）。此外，已曝光或未曝光的部分（取决于显影的类型）被去除以便形成第三层33。
第三层33用作用于刻蚀第一和第二前体层31'、32'的刻蚀掩模以便形成第一和第二层。该刻蚀工艺的结果在图11C中被示出。
第三前体层（未在图11B中示出）可以是非固化的酰亚胺层，其如之前所解释的可以被图案化。根据一个实施例，在图案化第三前体层之后以及在使用第三层33作为用于刻蚀第一和第二前体层31'、32'的刻蚀掩模之前，固化第三层33。固化使第三层33足够坚硬和鲁棒以充当刻蚀掩模。固化可以包括在300°C和400°C之间的温度下的退火工艺。
在参考图11A-11C解释的过程之后，第一层31、第二层32和第三层33的边缘对准。下面参考图12A-12B解释将第三层的边缘制作成远离第二层32的边缘的过程的一个实施例。
该过程与参考图11A-11C解释的过程的不同之处在于图案化第一和第二前体层31'、32'以便形成第一和第二层31、32涉及在形成第一和第二层31、32之后完全去除的刻蚀掩模202。该刻蚀掩模在图12A中被示出。
参考图12B，在去除刻蚀掩模202之后，第三前体层33'形成在第二层32以及接触电极2和第一表面101未被第一和第二层31、32覆盖的那些部分上。根据一个实施例，第三前体层33'是未固化的酰亚胺层。该方法还包括图案化第三前体层33'。图案化第三前体层33'可以包括如之前参考图11B解释的光刻工艺。借助该工艺，第三前体层33'可以独立于第一和第二层31、32被图案化，使得第三层33被制作成具有远离第二层32的内边缘和外边缘的内边缘和外边缘，如参考图4解释的。第三层33可以在图案化第三前体层33'的光刻工艺之后被固化。
参考图5，该方法还可以包括形成外壳62以及利用软密封层61填充外壳62中的空间。
尽管已经公开了本发明的各种示例性实施例，但是对于本领域技术人员来说显而易见的是，在不脱离本发明的精神和范围的情况下可以进行各种将实现本发明的优点中的一些的改变和修改。对于本领域适度技术人员来说明显的是，执行相同功能的其它部件可被适当地替代。应当提到，参考特定图解释的特征可以与其它图的特征组合，即使是在这种组合并未被明确提到的情况下。另外，本发明的方法可以使用合适的处理器指令以所有软件实施方式实现、或者可以以利用硬件逻辑和软件逻辑的组合的混合实施方式实现，以实现相同的结果。这种对发明构思的修改旨在被所附权利要求涵盖。
为了易于描述，使用例如"下面"、"以下"，"下部"，"上方"、"上部"等的空间相对术语来解释一个元件相对于第二个元件的定位。这些术语旨在除了包括不同于图中所描绘的那些取向的取向以外还包括器件的不同取向。另外，还使用例如"第一"、"第二"等的术语来描述各种元件、区域、部分等，并且这些术语也并不旨在是限制性的。在整个描述中，类似的术语指代类似的元件。
如本文使用的，术语"具有"、"包括"、"包含"、"含有"等是开放式术语，其表示所陈述的元件或者特征的存在，但并不排除附加的元件或者特征。冠词"一"、"一个"和"该"旨在包括复数以及单数，除非上下文另有清楚表示。
应当理解的是，除非另外特别指出，否则本文所描述的各种实施例的特征可以相互组合。
虽然本文已经示出和描述了特定实施例，但本领域普通技术人员将认识到，在不脱离本发明的范围的情况下，多种替换和/或等效实施方式可替代所示出和描述的特定实施例。本申请旨在涵盖本文所讨论的特定实施例的任何改编或变型。因此，本发明旨在仅由权利要求及其等同物限制。

Claims (31)

1.一种半导体器件，包括：
包括第一表面的半导体本体；
在第一表面上的接触电极；和
在第一表面上与接触电极相邻并且与接触电极部分重叠的钝化层，
其中，所述钝化层包括具有第一层和第二层的层堆叠，所述第一层包括在第一表面上的氧化物，所述第二层包括在第一层上的氮化物。
2.根据权利要求1所述的半导体器件，
其中第一层的厚度是至少1.5微米，以及
其中第二层的厚度是至少0.6微米。
3.根据权利要求1所述的半导体器件，其中半导体本体包括下述中的至少一个：硅（Si）、碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)、磷化镓(GaP)、磷化铟(InP)、铟镓氮(InGaN)、铟镓砷(InGaAs)、碲化镉(CdTe)、镉汞碲(CdHgTe)和镉镁碲(CdMgTe)。
4.根据权利要求1所述的半导体器件，其中氧化物包括氧化硅。
5.根据权利要求4所述的半导体器件，其中第一层包括下述中的至少一个：USG、PSG、BSG和BPSG。
6.根据权利要求1所述的半导体器件，其中氮化物包括氮化硅。
7.根据权利要求1所述的半导体器件，其中层堆叠还包括：
包括在第二层上的酰亚胺的第三层。
8.根据权利要求7所述的半导体器件，其中第三层的厚度是至少7微米。
9.根据权利要求8所述的半导体器件，
其中第二层和第三层均具有内边缘和外边缘，
其中第三层的内边缘远离第二层的内边缘，以及
其中第三层的外边缘远离第二层的外边缘。
10.根据权利要求7所述的半导体器件，还包括：
在第三层和接触电极上的软密封层；和
通过软密封层与第三层分离的外壳。
11.根据权利要求10所述的半导体器件，其中软密封层选自由下述构成的组：
硅树脂，和
硅胶。
12.根据权利要求1所述的半导体器件，其中接触电极包括下述中的至少一个：铝、钛、铜、铝合金和铜合金。
13.根据权利要求1所述的半导体器件，还包括：
掺杂的器件第一区域和掺杂的第二器件区域，
其中第一掺杂半导体区域和第二掺杂半导体区域形成pn结，以及
其中接触电极连接到第二掺杂半导体区域。
14.根据权利要求13所述的半导体器件，
其中pn结延伸到第一表面，以及
其中钝化层覆盖在第一表面的顶部上的pn结。
15.根据权利要求14所述的半导体器件，
其中所述半导体器件被实施为二极管，以及
其中第一器件区域形成二极管的基区并且第二器件区域形成二极管的发射区。
16.根据权利要求14所述的半导体器件，
其中半导体器件被实施为MOS晶体管，以及
其中第一器件区域形成MOS晶体管的漂移区并且第二器件区域形成MOS晶体管的体区。
17.根据权利要求1所述的半导体器件，其中半导体器件被实施为肖特基二极管和JFET中的一个。
18.根据权利要求1所述的半导体器件，还包括：
被接触电极接触的掺杂半导体区域；和
在接触电极和所述掺杂半导体区域之间的肖特基结。
19.一种制作半导体器件的方法，所述方法包括：
提供具有第一表面的半导体本体；
在第一表面上形成接触电极；以及
在第一表面上形成与接触电极相邻并且与接触电极部分重叠的钝化层，
其中，所述钝化层包括具有第一层和第二层的层堆叠，所述第一层包括在第一表面上的氧化物，所述第二层包括在第一层上的氮化物。
20.根据权利要求19所述的方法，
其中第一层被制作成具有至少1. 5微米的厚度，以及
其中第二层被制作成具有至少0. 6微米的厚度。
21.根据权利要求19所述的方法，其中半导体本体（100）包括下述中的至少一个：硅（Si）、碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)、磷化镓(GaP)、磷化铟(InP)、铟镓氮(InGaN)、铟镓砷(InGaAs)、碲化镉(CdTe)、镉汞碲(CdHgTe)和镉镁碲(CdMgTe)。
22.根据权利要求19所述的方法，其中氧化物包括氧化硅。
23.根据权利要求22所述的半导体方法，其中第一层包括下述中的至少一个：USG、PSG、BSG和BPSG。
24.根据权利要求19所述的方法，其中氮化物包括氮化硅。
25.根据权利要求19所述的方法，还包括：
在第二层上制作包括酰亚胺的第三层。
26.根据权利要求25所述的方法，其中制作第一层和第二层包括在刻蚀工艺中使用第三层作为刻蚀掩模图案化第一层和第二层。
27.根据权利要求25所述的方法，其中第三层被制作成具有至少7微米的厚度。
28.根据权利要求25所述的方法，
其中制作第一层和第二层包括在刻蚀工艺中使用第一刻蚀掩模图案化第一层和第二层；
其中制作第三层包括去除第一刻蚀掩模，沉积前体层以及图案化前体层以形成第三层。
29.根据权利要求28所述的方法，其中图案化前体层包括光刻工艺。
30.根据权利要求28所述的方法，
其中第二层和第三层均具有内边缘和外边缘，
以及其中图案化前体层包括图案化第三层，这样第三层的内边缘远离第二层的内边缘并且第三层的外边缘远离第二层的外边缘。
31.根据权利要求19所述的方法，还包括：
在第三层和接触电极上形成软密封层；以及
形成通过软密封层与第三层分离的外壳。
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