US20200411555A1 - Semiconductor device including a leadframe or a diode bridge configuration - Google Patents
Semiconductor device including a leadframe or a diode bridge configuration Download PDFInfo
- Publication number
- US20200411555A1 US20200411555A1 US17/017,089 US202017017089A US2020411555A1 US 20200411555 A1 US20200411555 A1 US 20200411555A1 US 202017017089 A US202017017089 A US 202017017089A US 2020411555 A1 US2020411555 A1 US 2020411555A1
- Authority
- US
- United States
- Prior art keywords
- region
- die
- diode
- semiconductor device
- lead finger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 238000002955 isolation Methods 0.000 claims abstract description 40
- 239000004020 conductor Substances 0.000 claims 13
- 239000000463 material Substances 0.000 abstract description 8
- 239000012212 insulator Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 23
- 238000000034 method Methods 0.000 description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- 230000008569 process Effects 0.000 description 12
- 238000005530 etching Methods 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 229910002601 GaN Inorganic materials 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 5
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- IHGSAQHSAGRWNI-UHFFFAOYSA-N 1-(4-bromophenyl)-2,2,2-trifluoroethanone Chemical compound FC(F)(F)C(=O)C1=CC=C(Br)C=C1 IHGSAQHSAGRWNI-UHFFFAOYSA-N 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 2
- 239000013590 bulk material Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
Definitions
- the present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method for a monolithically integrated power device and control logic.
- a semiconductor wafer or substrate can be made with a variety of base substrate materials, such as silicon (Si), germanium, aluminum phosphide, aluminum arsenide, gallium arsenide (GaAs), gallium nitride (GaN), aluminum gallium nitride over gallium nitride (AlGaN/GaN), indium phosphide, silicon carbide (SiC), or other bulk material for structural support.
- a plurality of semiconductor die is formed on the wafer separated by a non-active, inter-die substrate area or saw street. The saw street provides cutting areas to singulate the semiconductor wafer into individual semiconductor die.
- a power metal oxide semiconductor field effect transistor is commonly used to switch relatively large currents.
- Many applications require several power MOSFETs, for example, to independently control electrical current in different loads.
- an automobile may require separate power MOSFETs to switch current through actuators that roll windows up and down, adjust rear-view mirrors, and adjust the position of car seats.
- Power MOSFETs may also be used to switch electrical current to heating elements within windows and mirrors, or as part of a switch-mode power supply to convert battery voltage to another voltage. In such applications, the electrical currents can be relatively high, leading to a need for high density, low loss switches resulting in high efficiency.
- Each power device used to switch an electrical current requires control logic to determine when to turn the switch on and off.
- the control logic for each power device is located in a control logic semiconductor package, and each of the power devices are separately packaged and placed on a common printed circuit board (PCB) or remotely from the control logic package.
- PCB printed circuit board
- FIGS. 1 a -1 b illustrate a semiconductor substrate with a plurality of semiconductor die separated by a saw street
- FIGS. 2 a -2 t illustrate a process of forming power regions and control regions in an SOI substrate
- FIGS. 3 a -3 h illustrate a process of forming vertical gate structures in the power regions for the power MOSFET
- FIGS. 4 a -4 f illustrate a process of forming control logic in the control region for the power MOSFET
- FIG. 5 illustrates the semiconductor device in a leadframe with drain sensing
- FIGS. 6 a -6 e illustrate forming power regions and control regions in a non-SOI substrate
- FIGS. 7 a -7 b illustrate the semiconductor device in a diode bridge configuration.
- semiconductor die refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
- FIG. 1 a shows a semiconductor wafer or substrate 100 with a base substrate material 102 , such as Si, germanium, aluminum phosphide, aluminum arsenide, GaAs, GaN, AlGaN/GaN, indium phosphide, SiC, or other bulk material for structural support.
- Semiconductor substrate 100 has a width or diameter of 100-450 millimeters (mm) and thickness of about 700-800 micrometers ( ⁇ m).
- a plurality of semiconductor die 104 is formed on substrate 100 separated by a non-active, inter-die substrate area or saw street 106 .
- Saw street 106 provides cutting areas to singulate semiconductor substrate 100 into individual semiconductor die 104 .
- Semiconductor die 104 may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing.
- IPDs integrated passive devices
- semiconductor die 104 contains one or more monolithically integrated vertically oriented power devices and associated control logic with relatively high density.
- silicon-on-insulator (SOI) substrate 120 includes a base substrate or handle wafer 122 .
- Base substrate 122 is relatively heavily doped (N++) with donor dopant atoms.
- Donor dopant atoms provide an extra electron to the silicon lattice to provide a negative or N-type region.
- Acceptor dopant atoms create an electron hole in the silicon lattice to provide a positive or P-type region.
- An N-type epitaxial (EPI) layer 124 can be grown on base substrate 122 .
- Wafer 126 is relatively light doped with donor atoms.
- Wafer 126 and base substrate 122 each have an oxide layer grown on surfaces of the wafers.
- the oxide layers on wafer 126 and base substrate 122 are cleaned and atomically bonded to form buried oxide (BOX) layer 128 .
- Base substrate 122 with EPI layer 124 bonded to wafer 126 through BOX layer 128 forms SOI substrate 120 .
- EPI layer 124 can be grown to a greater thickness.
- SOI substrate 120 de-couples the drain regions from the control logic regions.
- an oxide layer 130 is formed over wafer 126 of SOI substrate 120 .
- Nitride layer 132 is formed over oxide layer 130 .
- a portion of wafer 126 , BOX layer 128 , oxide layer 130 , and nitride layer 132 is removed in power regions 140 a and 140 b , as shown in FIG. 2 c , to form openings 134 extending partially through SOI substrate 120 to contain later-formed power MOSFETs.
- the layers are removed by laser direct ablation (LDA), plasma etching, or combination of etching process.
- Wafer 126 , BOX layer 128 , oxide layer 130 , and nitride layer 132 remain within control region 144 , as isolation for later formed control logic.
- Control region 144 can be centrally located with respect to power regions 140 a and 140 b , or disposed in any other location on semiconductor die 104 .
- control region 144 can be disposed at one or more locations around a perimeter of semiconductor die 104 and power regions 140 a and 140 b disposed central to control region.
- FIG. 2 e illustrates a smaller portion 146 of SOI substrate 120 focused around boundary 148 between control region 144 , where CMOS control logic is formed, and power region 140 a or 140 b , where vertical power MOSFETs are formed. While the disclosed examples illustrate the power devices as being vertical power MOSFETs, other power devices can be formed in power regions 140 a and 140 b .
- Semiconductor die 104 may have multiple power devices formed monolithically, each having accompanying control logic.
- an oxide layer 150 is formed to isolate sidewalls 152 of wafer 126 and BOX layer 128 .
- Oxide layer 150 extends over EPI layer 124 in power regions 140 a and 140 b .
- FIG. 2 f and subsequent figures continue to show the smaller portion 146 of SOI substrate 120 focused around boundary 148 between control region 144 and power region 140 b , similar to FIG. 2 e .
- oxide layer 150 across EPI layer 124 in power regions 140 a and 140 b is removed by plasma etching or other etching process, leaving oxide layer 150 oriented vertically on sidewalls 152 of wafer 126 and BOX layer 128 .
- Nitride layer 132 is removed by plasma etching or other etching process to expose oxide layer 130 .
- FIG. 2 h shows a plan view of SOI substrate 120 with power regions 140 a and 140 b and the remaining oxide layer 130 over control region 144 .
- a selective EPI growth is performed on EPI layer 124 of SOI substrate 120 to form EPI layer 160 within power regions 140 a and 140 b .
- Region 162 at the boundary between EPI layer 160 and oxide layer 150 typically contains defects in the atomic lattice.
- the selective EPI growth provides silicon with near perfect atomic lattice up from EPI layer 124 , while leaving a relatively small region 162 of defects proximate to oxide layer 150 .
- EPI layer 160 has a different dopant atom concentration than wafer 126 .
- the disclosed manufacturing process provides the flexibility of having various dopant concentrations, types of dopant, or dopant thicknesses between the multiple control region 144 and power regions 140 a and 140 b . Accordingly, each power device can be formed with a different doping profile by separate selective EPI growth steps using multiple masks.
- FIG. 2 j shows a plan view of SOI substrate 120 with EPI layer 160 in power regions 140 a and 140 b.
- pad oxide 164 is formed over EPI layer 160 in power regions 140 a and 140 b .
- isolation trench 166 is formed around power regions 140 a and 140 b including through region 162 to remove imperfections where EPI layer 160 meets oxide layer 150 .
- Isolation trench 166 has a ring, rectangular, or otherwise enclosing shape and extends through EPI layer 160 and partially into EPI layer 124 .
- An oxide layer 168 is conformally applied over EPI layer 160 in power regions 140 a and 140 b and over oxide layer 130 in control region 144 and further on the sidewall of isolation trench 166 .
- a polysilicon material 170 can be deposited in a remaining portion of isolation trench 166 over oxide layer 168 to form isolation structure 172 in power regions 140 a and 140 b .
- isolation trench 166 is filled with oxide layer 168 .
- Isolation structure 172 isolates power devices in power regions 140 a and 140 b from the control logic in control region 144 .
- Isolation trench 174 is formed in control region 144 to isolate control region 144 a from control region 144 b .
- Isolation trenches 166 and 174 can be formed by LDA, plasma etching, or other etching process.
- Isolation trench 174 has a ring, rectangular, or otherwise enclosing shape and extends through wafer 126 to BOX layer 128 in control region 144 .
- Oxide layer 168 is conformally applied on the sidewall of isolation trench 174 .
- Polysilicon material 170 can be deposited in a remaining portion of isolation trench 174 over oxide layer 168 to form isolation structure 175 in control region 144 .
- isolation trench 174 is filled with oxide layer 168 or other dielectric.
- Isolation trench 174 isolates control logic between multiple power devices in control regions 144 a and 144 b .
- FIG. 2 m shows a plan view of SOI substrate 120 with isolation trenches 166 and 174 and oxide layer 168 .
- Additional isolation trenches 166 can be used with more power devices monolithically integrated on a common SOI substrate 120 .
- wider isolation regions or multiple concentric trench rings 166 a and 166 b in FIGS. 2 n and 2 o are formed where additional isolation is desired, e.g., for high voltage termination.
- FIG. 2 p show an alternate embodiment with isolation trench 166 formed similar to FIG. 2 l followed by a deeper oxide spacer etch extending into base substrate 122 .
- isolation trench 174 is formed similar to FIG. 2 l followed by a deeper oxide spacer etch extending into base substrate EPI layer 124 .
- the oxide spacer etch is filled with phosphorous doped polysilicon 176 to create a conductive channel from the top surface of SOI substrate 120 to base substrate 122 in power regions 140 a and 140 b , and further create a conductive channel from the top surface of SOI substrate 120 to EPI layer 124 in control region 144 a and 144 b .
- Polysilicon 176 extending into base substrate 122 and EPI layer 124 provides a top surface connection to the power device substrates that can be routed to control logic in control region 144 using metal routing. Polysilicon 176 allows control logic to sense the drain voltage of power devices in power regions 140 a and 140 b . For embodiments with higher drain voltages being sensed by control logic, additional trenches around polysilicon 176 may be formed.
- vertical gate trenches 180 are formed across power regions 140 a and 140 b , for example, in a parallel arrangement.
- a width W 1 of gate trenches 180 is about 0.3 ⁇ m.
- a width W 2 between gate trenches 180 is about 0.5 ⁇ m.
- a high voltage termination trench 182 is formed around gate trenches 180 of power regions 140 a and 140 b .
- FIG. 2 r shows a plan view of SOI substrate 120 with gate trenches 180 and termination trench 182 around the gate trenches.
- FIGS. 3 a -3 h illustrate further detail of forming vertical gate structures of the power MOSFET in gate trenches 180 and high voltage termination trench 182 in power regions 140 a and 140 b .
- gate oxide layer 184 is conformally applied over EPI layer 160 and into gate trenches 180 and termination trench 182 .
- Nitride layer 186 is conformally applied over gate oxide layer 184 on EPI layer 160 and into gate trenches 180 and termination trench 182 .
- a width W 3 of the opening in gate trench 180 is about 0.16 ⁇ m after forming nitride layer 186 .
- an oxide layer 188 is conformally applied into gate trenches 180 and termination trench 182 over nitride layer 186 .
- Phosphorous doped polysilicon 190 is deposited into gate trenches 180 to form field plates for the power MOSFET.
- a width W 4 of phosphorous doped polysilicon 190 in gate trenches 180 is about 0.1 ⁇ m.
- Phosphorous doped polysilicon 190 is also deposited into termination trench 182 .
- a portion of polysilicon 190 in gate trenches 180 is removed by LDA, plasma etching, or other etching process to a depth D 1 of 1.0 ⁇ m or less.
- a portion of polysilicon 190 in termination trench 182 is also removed by LDA, plasma etching, or other etching process.
- a portion of oxide layer 188 is removed wet etching or other etching process down below polysilicon 190 .
- An end portion of polysilicon 190 extends above the remaining oxide layer 188 in gate trenches 180 and termination trench 182 after the etching process.
- oxide layer 192 is formed over the exposed end portion of polysilicon 190 in gate trenches 180 and termination trench 182 .
- oxide layer 194 is formed in gate trenches 180 and termination trench 182 to smooth the oxide over polysilicon 190 .
- the exposed portion of nitride layer 186 is removed by wet etching or other etching techniques.
- a high temperature oxide (HTO) layer 196 is formed over oxide layer 192 , oxide layer 194 , and gate oxide layer 184 .
- phosphorous doped polysilicon 200 is deposited to fill gate trenches 100 as vertical gate structures 202 of the power MOSFET. Surface 204 undergoes chemical-mechanical planarization or other removal technique.
- FIG. 2 s shows SOI substrate 120 following formation of vertical gate structures 202 in FIGS. 3 a -3 h for the power MOSFET in power regions 140 a and 140 b .
- FIG. 2 t shows a plan view of SOI substrate 120 with vertical gate structures 202 in power regions 140 a and 140 b .
- the power MOSFET is a high density vertical power semiconductor device.
- FIGS. 4 a -4 f show a process of forming complementary metal oxide semiconductor (CMOS) control logic in control regions 144 a and 144 b , and the doped regions of the power MOSFET in power regions 140 a and 140 b .
- SOI substrate 120 is oriented to show further detail of control regions 144 a and 144 b .
- P-type well region 210 is formed in control region 144 b of wafer 126
- P-type well region 212 is formed in control region 144 a of wafer 126 .
- One or more transistors are formed in wafer 126 , including P-well regions 210 and 212 , as control logic circuits 213 a and 213 b to achieve the requisite functionality in control of the power MOSFETs in power regions 140 a and 140 b .
- other CMOS, bipolar, or DMOS analog and mixed signal transistors are used to form control logic in control regions 144 a and 144 b of wafer 126 .
- a P-type region 214 is formed between gate structures 202 in power regions 140 a and 140 b as the channel region of the power MOSFETs.
- a charge balanced superjunction can be used.
- FIG. 4 b shows a plan view of SOI substrate 120 with P-type well region 210 formed in control region 144 b of wafer 126 , P-type well region 212 formed in control region 144 a for various control logic transistors, and P-type region 214 is formed between gate structures 202 in power regions 140 a and 140 b.
- Interconnect structure 220 is formed over SOI substrate 120 .
- Interconnect structure 220 includes conductive vias 222 formed through insulating layer 224 to connect to control logic transistors formed in control regions 144 a and 144 b .
- Conductive vias 222 further connect to P-type region 214 and gate structures 202 in power regions 140 a and 140 b .
- Conductive layer 226 is formed over insulating layer 224 and conductive vias 222 .
- Insulating layer 228 is formed over conductive layers 226 and insulating layer 224 .
- Conductive layer 226 and conductive vias 222 provide electrical interconnect for control circuits 213 a and 213 b to control the power devices in control regions 140 a and 140 b .
- Additional insulating layers like 230 , conductive layer 226 , and conductive via 232 can be formed for electrical interconnect and routing.
- Conductive plug 234 operates as a front-side source contact through conductive vias 222 to the power MOSFET in power regions 140 a and 140 b and is configured for a leadframe to be coupled to the source of the power MOSFET by a clip, bond wire, or other appropriate mechanism.
- Conductive layer 236 routes electrical signals from the control logic in control regions 144 a and 144 b to contact pads for connection to the leadframe by wire bonding or other appropriate connection method.
- Insulating layer or encapsulant 238 is formed over conductive layer 236 and conductive plug 234 for environmental protection and structural integrity. An opening is etched through insulating layer 238 to expose conductive plug 234 and contact pads of conductive layer 236 for subsequent interconnect.
- SOI substrate 120 is shown inverted to form trench 240 with backside etching through base substrate 122 and EPI layer 124 .
- plasma etching is used to form trench 240 .
- Trench 240 provides lateral isolation between the plurality of power regions 140 and control regions 144 on SOI substrate 120 .
- Trench 240 separates base substrate 122 into a portion 122 a connected to the drain of a power MOSFET formed in power region 140 a , and a portion 122 b connected to the drain of a power MOSFET formed in power region 140 b . Accordingly, trench 240 provides isolation of the multiple drain regions on semiconductor die 104 .
- EPI layer 124 is likewise separated into portions 124 a and 124 b .
- an additional trench like 240 is formed between power region 140 a and control region 144 , such that the portion 122 a of base substrate 122 is isolated from the power MOSFET in power region 140 a and sits as an island over control region 144 .
- Trench 240 can extend laterally to trench 166 such that base substrate 122 and EPI layer 124 remain directly over power region 140 , and are completely removed over control region 144 .
- base substrate 122 and EPI layer 124 remain extending over control region 144 to improve die strength and planarity of the wafer backside.
- Base substrate 122 extending over control region 144 also allows conductive vias to be formed through BOX layer 128 to couple the control logic circuitry to the respective power MOSFETs.
- an insulating or passivation layer 242 is formed over base substrate 122 , including into trench 240 .
- Insulating layer 242 includes openings over power regions 140 for the formation of drain contacts 244 .
- FIG. 4 f illustrates a plan view of semiconductor device 250 after formation of passivation layer 242 and drain contacts 244 .
- Semiconductor device 250 includes two monolithically integrated vertical power MOSFETs formed in power regions 140 a and 140 b , and separately isolated analog, digital, or mixed signal control logic formed in control region 144 for each of the vertical power MOSFET.
- Each of the power devices can operate at a different voltage by varying the thickness of the EPI layers for the particular power devices, as well as varying the trench depth of the power devices.
- Trench 240 surrounds power regions 140 a and 140 b and creates a lateral separation between portion 122 a and portion 122 b of base substrate 122 .
- Trench 240 electrically isolates the drain terminal of a power MOSFET in power region 140 a from the drain terminal of a power MOSFET in power region 140 b .
- Vertical isolation between the control logic and power device drain terminals is provided by buried oxide layer 128 .
- Portion 122 a of base substrate 122 includes a branch that extends under control region 144 a , and portion 122 b extends under control region 144 b , so that control logic is able to contact the drain of power MOSFETs formed in power region 140 a using a conductive via through BOX layer 128 .
- base substrate 122 may be completely removed under control region 144 . Removing additional material of base substrate 122 and EPI layer 124 under control region 144 , or electrically isolating the material from all power devices, reduces interference in the control logic caused by the high voltage drain contacts.
- Semiconductor device 250 is disposed on a leadframe and attached by metallurgical bonding between drain contacts 244 and the leadframe.
- a clip from the leadframe to source contacts 234 provides an external source contact for each of the vertical power MOSFETs.
- drain contact 244 can be routed by bond wire or clip to the top surface of semiconductor device 250 , e.g. for drain sensing. Bonding wires are used to couple other leadframe contacts to terminals of control region 144 for I/O of signals necessary for control of power MOSFETs formed in power regions 140 a and 140 b .
- Semiconductor device 250 is encapsulated electrical interconnect and singulated to finish the package.
- Semiconductor device 250 combines one or more power devices and control logic fully isolated (source, drain, and gate of power MOSFET and control logic) in an integrated monolithic semiconductor package using an SOI substrate or non-SOI substrate.
- the power devices and control logic can be lateral or high density vertical trench-based semiconductor devices with vertical conduction path from active surface 110 to back surface 108 in semiconductor die 102 .
- Conductive layers 226 and 236 provide electrical interconnect on a first major surface for control logic circuits 213 a and 213 b .
- Conductive layer 234 provides electrical interconnect on the first major surface for the power MOSFET, e.g. source connection.
- Conductive layer 244 provides electrical interconnect on a second major surface for the power MOSFET, e.g. drain connection.
- Semiconductor device 250 provides a flexible platform for different voltages based on vertical thickness and/or trench depth.
- Semiconductor device 250 containing one or more isolated power devices and associated control logic can be used in many applications, such as automotive, switch mode power supplies, and diode bridges for sine-wave rectification.
- FIG. 5 illustrates semiconductor device 250 disposed in split leadframe 252 with lead fingers 252 a - 252 h .
- Bond wire 254 is coupled between lead finger 252 a at the drain of the power MOSFET in power region 140 a to control logic in control region 144 a for drain sensing.
- Lead fingers 252 b and 252 c are coupled by bond wire to control region 144 a and control region 144 b .
- Bond wire 256 is coupled between lead finger 252 d at the drain of the power MOSFET in power region 140 b to control logic in control region 144 b for drain sensing.
- Lead finger 252 e is coupled to the source of the power MOSFET in power region 140 a .
- Lead fingers 252 f and 252 g are coupled by bond wire to control region 144 a and control region 144 b .
- Lead finger 252 h is coupled by bond wire to the source of the power MOSFET in power region 140 b.
- FIGS. 6 a -6 e illustrate an alternative embodiment of monolithically integrating isolated vertical power devices and control logic on non-SOI substrate 258 .
- FIG. 6 a shows an N-type base substrate 260 doped with donor atoms.
- a P-type EPI layer 262 is grown on base substrate 260 .
- a portion 264 of EPI layer 262 is doped with acceptor atoms to an N-type region as part of the drain connection of a power MOSFET to be formed in power region 140 b .
- Buried layer 266 is formed in EPI layer 262 in control region 144 for isolation and low resistance path.
- An insulating layer 268 is formed over EPI layer 262 .
- an N-type EPI layer 270 is grown over EPI layer 262 .
- a portion 272 of EPI layer 270 is doped with donor atoms to form a heavily doped N-type region as part of the drain terminal of power region 140 b .
- a portion 274 of EPI layer 270 is additionally doped with donor atoms to form a heavily doped N-type region for an N-well of control region 144 .
- a portion 276 of EPI layer 270 is doped with acceptor atoms for a P-well of control region 144 .
- Insulation-filled trenches 280 are formed to isolate power region 140 a and 140 b from control region 144 .
- Isolation trenches 280 form concentric rings around power region 140 a and 140 b , or otherwise extend completely between power region 140 and control region 144 .
- Insulation-filled trenches 282 and 284 are formed to laterally isolate N-well 274 and P-well 276 .
- Gate structures 290 for power MOSFETs are formed within power regions 140 a and 140 b , similar to FIGS. 3 a -3 h .
- High voltage termination trench 292 is formed around gate structures 290 , similar to FIG. 2 l .
- MOSFETs in control region 144 and doped regions of power regions 140 a and 140 b similar to FIGS. 4 a - 4 f.
- an interconnect structure 300 includes conductive vias 302 formed through insulating layer 304 to connect to control logic transistors formed in control regions 144 .
- Conductive layer 306 is formed over insulating layer 304 and conductive vias 302 .
- Insulating layer 308 is formed over conductive layers 306 and insulating layer 304 . Additional insulating layers like 310 , conductive layer 306 , and conductive via 312 can be formed for electrical interconnect and routing.
- Conductive plug 314 operates as a front-side source contact through conductive vias 302 to the power MOSFET in power regions 140 a and 140 b and is configured for a leadframe to be coupled to the source of the power MOSFET by a clip, bond wire, or other appropriate mechanism.
- Drain contact 346 can be routed by bond wire or clip to the top surface of semiconductor device 340 , e.g. for drain sensing.
- Conductive layer 316 routes electrical signals from the control logic in control regions 144 a and 144 b to contact pads for connection to the leadframe by wire bonding or other appropriate connection method.
- Insulating layer or encapsulant 320 is formed over conductive layer 316 and conductive plug 314 for environmental protection and structural integrity. An opening is etched through insulating layer 320 to expose conductive plug 314 and contact pads of conductive layer 316 for subsequent interconnect.
- semiconductor device 340 is shown inverted to form trench 342 using a backside etch, e.g. plasma etch.
- Trench 342 electrically isolates the drain terminal of a power MOSFET in power region 140 a from the drain terminal of a power MOSFET in power region 140 b .
- Trench 342 is formed extending to trenches 280 to complete the lateral isolation between power region 140 and control region 144 .
- Trench 342 follows the path of trenches 280 .
- trench 342 and trench 280 extend completely around each power region 140 .
- trench 342 and trench 280 extend vertically completely through the die for complete isolation between control region 144 and power region 140 .
- trench 342 extends completely across control region 144 such that base substrate 260 and EPI layer 262 are completely removed within the footprint of control region 144 .
- An insulating or passivation layer 344 is formed over base substrate 260 and into trench 342 .
- Drain contact 346 is formed over base substrate 260 for backside interconnect.
- Semiconductor device 340 combines one or more power devices and control logic fully isolated (source, drain, and gate of power MOSFET and control logic) in an integrated monolithic semiconductor package using an SOI substrate or non-SOI substrate.
- the power devices and control logic can be lateral or high density vertical trench-based semiconductor devices with vertical conduction path from active surface 110 to back surface 108 in semiconductor die 102 .
- Conductive layers 306 and 316 provide electrical interconnect on a first major surface for control logic circuits.
- Conductive layer 314 provides electrical interconnect on the first major surface for the power MOSFET, e.g. source connection.
- Conductive layer 346 provides electrical interconnect on a second major surface for the power MOSFET, e.g. drain connection.
- Semiconductor device 340 provides a flexible platform for different voltages based on vertical thickness and/or trench depth. Semiconductor device 340 containing one or more isolated power devices and associated control logic can be used in many applications, such as automotive, switch mode power supplies, and diode bridges for sine-wave rectification.
- FIGS. 7 a and 7 b illustrate diode bridge 350 for sine-wave rectification, including diodes 352 , 354 , 356 , and 358 , formed in four power regions 140 .
- Diode 352 is coupled between conductive layer 360 and conductive layer 362 .
- Diode 354 is coupled between conductive layer 362 and conductive layer 364 .
- Diode 356 is coupled between conductive layer 364 and conductive layer 366 .
- Diode 358 is coupled between conductive layer 366 and conductive layer 360 .
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
- The present application claims the benefit of U.S. Provisional Application No. 62/363,449, filed Jul. 18, 2016, by Jefferson W. HALL and Gordon M. GRIVNA, which application is incorporated herein by reference.
- The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method for a monolithically integrated power device and control logic.
- A semiconductor wafer or substrate can be made with a variety of base substrate materials, such as silicon (Si), germanium, aluminum phosphide, aluminum arsenide, gallium arsenide (GaAs), gallium nitride (GaN), aluminum gallium nitride over gallium nitride (AlGaN/GaN), indium phosphide, silicon carbide (SiC), or other bulk material for structural support. A plurality of semiconductor die is formed on the wafer separated by a non-active, inter-die substrate area or saw street. The saw street provides cutting areas to singulate the semiconductor wafer into individual semiconductor die.
- A power metal oxide semiconductor field effect transistor (MOSFET) is commonly used to switch relatively large currents. Many applications require several power MOSFETs, for example, to independently control electrical current in different loads. For instance, an automobile may require separate power MOSFETs to switch current through actuators that roll windows up and down, adjust rear-view mirrors, and adjust the position of car seats. Power MOSFETs may also be used to switch electrical current to heating elements within windows and mirrors, or as part of a switch-mode power supply to convert battery voltage to another voltage. In such applications, the electrical currents can be relatively high, leading to a need for high density, low loss switches resulting in high efficiency.
- Each power device used to switch an electrical current requires control logic to determine when to turn the switch on and off. Commonly, the control logic for each power device is located in a control logic semiconductor package, and each of the power devices are separately packaged and placed on a common printed circuit board (PCB) or remotely from the control logic package. The plurality of separate semiconductor packages adds cost and consumes PCB area.
-
FIGS. 1a-1b illustrate a semiconductor substrate with a plurality of semiconductor die separated by a saw street; -
FIGS. 2a-2t illustrate a process of forming power regions and control regions in an SOI substrate; -
FIGS. 3a-3h illustrate a process of forming vertical gate structures in the power regions for the power MOSFET; -
FIGS. 4a-4f illustrate a process of forming control logic in the control region for the power MOSFET; -
FIG. 5 illustrates the semiconductor device in a leadframe with drain sensing; -
FIGS. 6a-6e illustrate forming power regions and control regions in a non-SOI substrate; and -
FIGS. 7a-7b illustrate the semiconductor device in a diode bridge configuration. - The following describes one or more embodiments with reference to the figures, in which like numerals represent the same or similar elements. While the figures are described in terms of the best mode for achieving certain objectives, the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
-
FIG. 1a shows a semiconductor wafer orsubstrate 100 with abase substrate material 102, such as Si, germanium, aluminum phosphide, aluminum arsenide, GaAs, GaN, AlGaN/GaN, indium phosphide, SiC, or other bulk material for structural support.Semiconductor substrate 100 has a width or diameter of 100-450 millimeters (mm) and thickness of about 700-800 micrometers (μm). A plurality of semiconductor die 104 is formed onsubstrate 100 separated by a non-active, inter-die substrate area or sawstreet 106. Saw street 106 provides cutting areas to singulatesemiconductor substrate 100 into individual semiconductor die 104. -
FIG. 1b shows a cross-sectional view of a portion ofsemiconductor substrate 100. Each semiconductor die 104 includes aback surface 108 and active surface orregion 110 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface orregion 110 to implement analog circuits or digital circuits. Semiconductor die 104 may also contain a power device, control logic, digital signal processor (DSP), microcontroller, ASIC, standard logic, amplifiers, clock management, memory, interface circuit, optoelectronics, and other signal processing circuits. Semiconductor die 104 may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. In particular,semiconductor die 104 contains one or more monolithically integrated vertically oriented power devices and associated control logic with relatively high density. - The following figures illustrate manufacturing high density power MOSFETs on a common die with control logic for switching the power MOSFETs. In
FIG. 2a , silicon-on-insulator (SOI)substrate 120 includes a base substrate orhandle wafer 122.Base substrate 122 is relatively heavily doped (N++) with donor dopant atoms. Donor dopant atoms provide an extra electron to the silicon lattice to provide a negative or N-type region. Acceptor dopant atoms create an electron hole in the silicon lattice to provide a positive or P-type region. - An N-type epitaxial (EPI)
layer 124 can be grown onbase substrate 122. Wafer 126 is relatively light doped with donor atoms. Wafer 126 andbase substrate 122 each have an oxide layer grown on surfaces of the wafers. The oxide layers onwafer 126 andbase substrate 122 are cleaned and atomically bonded to form buried oxide (BOX)layer 128.Base substrate 122 withEPI layer 124 bonded to wafer 126 throughBOX layer 128forms SOI substrate 120. In some embodiments, where a high voltage power MOSFET is formed,EPI layer 124 can be grown to a greater thickness.SOI substrate 120 de-couples the drain regions from the control logic regions. - In
FIG. 2b , anoxide layer 130 is formed overwafer 126 ofSOI substrate 120. Nitridelayer 132 is formed overoxide layer 130. A portion ofwafer 126,BOX layer 128,oxide layer 130, andnitride layer 132 is removed inpower regions FIG. 2c , to formopenings 134 extending partially throughSOI substrate 120 to contain later-formed power MOSFETs. The layers are removed by laser direct ablation (LDA), plasma etching, or combination of etching process.Wafer 126,BOX layer 128,oxide layer 130, andnitride layer 132 remain withincontrol region 144, as isolation for later formed control logic.FIG. 2d illustrates a plan view ofSOI substrate 120 withpower regions control region 144.Control region 144 can be centrally located with respect topower regions semiconductor die 104. For example,control region 144 can be disposed at one or more locations around a perimeter of semiconductor die 104 andpower regions -
FIG. 2e illustrates asmaller portion 146 ofSOI substrate 120 focused aroundboundary 148 betweencontrol region 144, where CMOS control logic is formed, andpower region power regions - In
FIG. 2f , anoxide layer 150 is formed to isolatesidewalls 152 ofwafer 126 andBOX layer 128.Oxide layer 150 extends overEPI layer 124 inpower regions FIG. 2f and subsequent figures continue to show thesmaller portion 146 ofSOI substrate 120 focused aroundboundary 148 betweencontrol region 144 andpower region 140 b, similar toFIG. 2e . InFIG. 2g ,oxide layer 150 acrossEPI layer 124 inpower regions oxide layer 150 oriented vertically onsidewalls 152 ofwafer 126 andBOX layer 128.Nitride layer 132 is removed by plasma etching or other etching process to exposeoxide layer 130.FIG. 2h shows a plan view ofSOI substrate 120 withpower regions oxide layer 130 overcontrol region 144. - In
FIG. 2i , a selective EPI growth is performed onEPI layer 124 ofSOI substrate 120 to formEPI layer 160 withinpower regions Region 162 at the boundary betweenEPI layer 160 andoxide layer 150 typically contains defects in the atomic lattice. The selective EPI growth provides silicon with near perfect atomic lattice up fromEPI layer 124, while leaving a relativelysmall region 162 of defects proximate tooxide layer 150. In some embodiments,EPI layer 160 has a different dopant atom concentration thanwafer 126. The disclosed manufacturing process provides the flexibility of having various dopant concentrations, types of dopant, or dopant thicknesses between themultiple control region 144 andpower regions FIG. 2j shows a plan view ofSOI substrate 120 withEPI layer 160 inpower regions - In
FIG. 2k ,pad oxide 164 is formed overEPI layer 160 inpower regions FIG. 2l ,isolation trench 166 is formed aroundpower regions region 162 to remove imperfections whereEPI layer 160 meetsoxide layer 150.Isolation trench 166 has a ring, rectangular, or otherwise enclosing shape and extends throughEPI layer 160 and partially intoEPI layer 124. Anoxide layer 168 is conformally applied overEPI layer 160 inpower regions oxide layer 130 incontrol region 144 and further on the sidewall ofisolation trench 166. Apolysilicon material 170 can be deposited in a remaining portion ofisolation trench 166 overoxide layer 168 to formisolation structure 172 inpower regions isolation trench 166 is filled withoxide layer 168.Isolation structure 172 isolates power devices inpower regions control region 144. - An
isolation trench 174 is formed incontrol region 144 to isolatecontrol region 144 a fromcontrol region 144 b.Isolation trenches Isolation trench 174 has a ring, rectangular, or otherwise enclosing shape and extends throughwafer 126 toBOX layer 128 incontrol region 144.Oxide layer 168 is conformally applied on the sidewall ofisolation trench 174.Polysilicon material 170 can be deposited in a remaining portion ofisolation trench 174 overoxide layer 168 to formisolation structure 175 incontrol region 144. Alternatively,isolation trench 174 is filled withoxide layer 168 or other dielectric.Isolation trench 174 isolates control logic between multiple power devices incontrol regions FIG. 2m shows a plan view ofSOI substrate 120 withisolation trenches oxide layer 168. -
Additional isolation trenches 166 can be used with more power devices monolithically integrated on acommon SOI substrate 120. In some embodiments, wider isolation regions or multiple concentric trench rings 166 a and 166 b inFIGS. 2n and 2o are formed where additional isolation is desired, e.g., for high voltage termination. -
FIG. 2p show an alternate embodiment withisolation trench 166 formed similar toFIG. 2l followed by a deeper oxide spacer etch extending intobase substrate 122. Likewise,isolation trench 174 is formed similar toFIG. 2l followed by a deeper oxide spacer etch extending into basesubstrate EPI layer 124. The oxide spacer etch is filled with phosphorous dopedpolysilicon 176 to create a conductive channel from the top surface ofSOI substrate 120 tobase substrate 122 inpower regions SOI substrate 120 toEPI layer 124 incontrol region Polysilicon 176 extending intobase substrate 122 andEPI layer 124 provides a top surface connection to the power device substrates that can be routed to control logic incontrol region 144 using metal routing.Polysilicon 176 allows control logic to sense the drain voltage of power devices inpower regions polysilicon 176 may be formed. - Returning to
FIG. 2l ,vertical gate trenches 180 are formed acrosspower regions gate trenches 180 is about 0.3 μm. A width W2 betweengate trenches 180 is about 0.5 μm. A highvoltage termination trench 182 is formed aroundgate trenches 180 ofpower regions FIG. 2r shows a plan view ofSOI substrate 120 withgate trenches 180 andtermination trench 182 around the gate trenches. -
FIGS. 3a-3h illustrate further detail of forming vertical gate structures of the power MOSFET ingate trenches 180 and highvoltage termination trench 182 inpower regions FIG. 3a ,gate oxide layer 184 is conformally applied overEPI layer 160 and intogate trenches 180 andtermination trench 182.Nitride layer 186 is conformally applied overgate oxide layer 184 onEPI layer 160 and intogate trenches 180 andtermination trench 182. A width W3 of the opening ingate trench 180 is about 0.16 μm after formingnitride layer 186. InFIG. 3b , anoxide layer 188 is conformally applied intogate trenches 180 andtermination trench 182 overnitride layer 186. Phosphorous dopedpolysilicon 190 is deposited intogate trenches 180 to form field plates for the power MOSFET. A width W4 of phosphorous dopedpolysilicon 190 ingate trenches 180 is about 0.1 μm. Phosphorous dopedpolysilicon 190 is also deposited intotermination trench 182. - In
FIG. 3c , a portion ofpolysilicon 190 ingate trenches 180 is removed by LDA, plasma etching, or other etching process to a depth D1 of 1.0 μm or less. A portion ofpolysilicon 190 intermination trench 182 is also removed by LDA, plasma etching, or other etching process. InFIG. 3d , a portion ofoxide layer 188 is removed wet etching or other etching process down belowpolysilicon 190. An end portion ofpolysilicon 190 extends above the remainingoxide layer 188 ingate trenches 180 andtermination trench 182 after the etching process. InFIG. 3e ,oxide layer 192 is formed over the exposed end portion ofpolysilicon 190 ingate trenches 180 andtermination trench 182. InFIG. 3f ,oxide layer 194 is formed ingate trenches 180 andtermination trench 182 to smooth the oxide overpolysilicon 190. InFIG. 3g , the exposed portion ofnitride layer 186 is removed by wet etching or other etching techniques. A high temperature oxide (HTO)layer 196 is formed overoxide layer 192,oxide layer 194, andgate oxide layer 184. InFIG. 3h , phosphorous dopedpolysilicon 200 is deposited to fillgate trenches 100 asvertical gate structures 202 of the power MOSFET.Surface 204 undergoes chemical-mechanical planarization or other removal technique. -
FIG. 2s showsSOI substrate 120 following formation ofvertical gate structures 202 inFIGS. 3a-3h for the power MOSFET inpower regions FIG. 2t shows a plan view ofSOI substrate 120 withvertical gate structures 202 inpower regions -
FIGS. 4a-4f show a process of forming complementary metal oxide semiconductor (CMOS) control logic incontrol regions power regions SOI substrate 120 is oriented to show further detail ofcontrol regions FIG. 4a , P-type well region 210 is formed incontrol region 144 b ofwafer 126, and P-type well region 212 is formed incontrol region 144 a ofwafer 126. One or more transistors are formed inwafer 126, including P-well regions control logic circuits power regions control regions wafer 126. - A P-
type region 214 is formed betweengate structures 202 inpower regions FIG. 4b shows a plan view ofSOI substrate 120 with P-type well region 210 formed incontrol region 144 b ofwafer 126, P-type well region 212 formed incontrol region 144 a for various control logic transistors, and P-type region 214 is formed betweengate structures 202 inpower regions - In
FIG. 4c , aninterconnect structure 220 is formed overSOI substrate 120.Interconnect structure 220 includesconductive vias 222 formed through insulatinglayer 224 to connect to control logic transistors formed incontrol regions Conductive vias 222 further connect to P-type region 214 andgate structures 202 inpower regions Conductive layer 226 is formed overinsulating layer 224 andconductive vias 222. Insulatinglayer 228 is formed overconductive layers 226 and insulatinglayer 224.Conductive layer 226 andconductive vias 222 provide electrical interconnect forcontrol circuits control regions conductive layer 226, and conductive via 232 can be formed for electrical interconnect and routing. -
Conductive plug 234 operates as a front-side source contact throughconductive vias 222 to the power MOSFET inpower regions Conductive layer 236 routes electrical signals from the control logic incontrol regions encapsulant 238 is formed overconductive layer 236 andconductive plug 234 for environmental protection and structural integrity. An opening is etched through insulatinglayer 238 to exposeconductive plug 234 and contact pads ofconductive layer 236 for subsequent interconnect. - In
FIG. 4d ,SOI substrate 120 is shown inverted to formtrench 240 with backside etching throughbase substrate 122 andEPI layer 124. In one embodiment, plasma etching is used to formtrench 240.Trench 240 provides lateral isolation between the plurality of power regions 140 andcontrol regions 144 onSOI substrate 120.Trench 240 separatesbase substrate 122 into aportion 122 a connected to the drain of a power MOSFET formed inpower region 140 a, and aportion 122 b connected to the drain of a power MOSFET formed inpower region 140 b. Accordingly,trench 240 provides isolation of the multiple drain regions onsemiconductor die 104.EPI layer 124 is likewise separated intoportions power region 140 a andcontrol region 144, such that theportion 122 a ofbase substrate 122 is isolated from the power MOSFET inpower region 140 a and sits as an island overcontrol region 144. Trench 240 can extend laterally to trench 166 such thatbase substrate 122 andEPI layer 124 remain directly over power region 140, and are completely removed overcontrol region 144. However,base substrate 122 andEPI layer 124 remain extending overcontrol region 144 to improve die strength and planarity of the wafer backside.Base substrate 122 extending overcontrol region 144 also allows conductive vias to be formed throughBOX layer 128 to couple the control logic circuitry to the respective power MOSFETs. - In
FIG. 4e , an insulating orpassivation layer 242 is formed overbase substrate 122, including intotrench 240. Insulatinglayer 242 includes openings over power regions 140 for the formation ofdrain contacts 244.FIG. 4f illustrates a plan view ofsemiconductor device 250 after formation ofpassivation layer 242 anddrain contacts 244.Semiconductor device 250 includes two monolithically integrated vertical power MOSFETs formed inpower regions control region 144 for each of the vertical power MOSFET. Each of the power devices can operate at a different voltage by varying the thickness of the EPI layers for the particular power devices, as well as varying the trench depth of the power devices. - Trench 240 surrounds
power regions portion 122 a andportion 122 b ofbase substrate 122. Trench 240 electrically isolates the drain terminal of a power MOSFET inpower region 140 a from the drain terminal of a power MOSFET inpower region 140 b. Vertical isolation between the control logic and power device drain terminals is provided by buriedoxide layer 128.Portion 122 a ofbase substrate 122 includes a branch that extends undercontrol region 144 a, andportion 122 b extends undercontrol region 144 b, so that control logic is able to contact the drain of power MOSFETs formed inpower region 140 a using a conductive via throughBOX layer 128. If a bonding wire is used to couplecontrol region 144 to the drain leadframe contacts, or if no backside connection is required,base substrate 122 may be completely removed undercontrol region 144. Removing additional material ofbase substrate 122 andEPI layer 124 undercontrol region 144, or electrically isolating the material from all power devices, reduces interference in the control logic caused by the high voltage drain contacts. -
Semiconductor device 250 is disposed on a leadframe and attached by metallurgical bonding betweendrain contacts 244 and the leadframe. A clip from the leadframe to sourcecontacts 234 provides an external source contact for each of the vertical power MOSFETs. Likewise,drain contact 244 can be routed by bond wire or clip to the top surface ofsemiconductor device 250, e.g. for drain sensing. Bonding wires are used to couple other leadframe contacts to terminals ofcontrol region 144 for I/O of signals necessary for control of power MOSFETs formed inpower regions Semiconductor device 250 is encapsulated electrical interconnect and singulated to finish the package. -
Semiconductor device 250 combines one or more power devices and control logic fully isolated (source, drain, and gate of power MOSFET and control logic) in an integrated monolithic semiconductor package using an SOI substrate or non-SOI substrate. The power devices and control logic can be lateral or high density vertical trench-based semiconductor devices with vertical conduction path fromactive surface 110 to backsurface 108 in semiconductor die 102.Conductive layers control logic circuits Conductive layer 234 provides electrical interconnect on the first major surface for the power MOSFET, e.g. source connection.Conductive layer 244 provides electrical interconnect on a second major surface for the power MOSFET, e.g. drain connection.Semiconductor device 250 provides a flexible platform for different voltages based on vertical thickness and/or trench depth.Semiconductor device 250 containing one or more isolated power devices and associated control logic can be used in many applications, such as automotive, switch mode power supplies, and diode bridges for sine-wave rectification. -
FIG. 5 illustratessemiconductor device 250 disposed insplit leadframe 252 withlead fingers 252 a-252 h.Bond wire 254 is coupled betweenlead finger 252 a at the drain of the power MOSFET inpower region 140 a to control logic incontrol region 144 a for drain sensing. Leadfingers region 144 a andcontrol region 144 b.Bond wire 256 is coupled betweenlead finger 252 d at the drain of the power MOSFET inpower region 140 b to control logic incontrol region 144 b for drain sensing.Lead finger 252 e is coupled to the source of the power MOSFET inpower region 140 a. Leadfingers region 144 a andcontrol region 144 b.Lead finger 252 h is coupled by bond wire to the source of the power MOSFET inpower region 140 b. -
FIGS. 6a-6e illustrate an alternative embodiment of monolithically integrating isolated vertical power devices and control logic onnon-SOI substrate 258.FIG. 6a shows an N-type base substrate 260 doped with donor atoms. A P-type EPI layer 262 is grown onbase substrate 260. InFIG. 6b , aportion 264 ofEPI layer 262 is doped with acceptor atoms to an N-type region as part of the drain connection of a power MOSFET to be formed inpower region 140 b.Buried layer 266 is formed inEPI layer 262 incontrol region 144 for isolation and low resistance path. An insulatinglayer 268 is formed overEPI layer 262. - In
FIG. 6c , an N-type EPI layer 270 is grown overEPI layer 262. Aportion 272 ofEPI layer 270 is doped with donor atoms to form a heavily doped N-type region as part of the drain terminal ofpower region 140 b. Aportion 274 ofEPI layer 270 is additionally doped with donor atoms to form a heavily doped N-type region for an N-well ofcontrol region 144. Aportion 276 ofEPI layer 270 is doped with acceptor atoms for a P-well ofcontrol region 144. Insulation-filledtrenches 280 are formed to isolatepower region control region 144.Isolation trenches 280 form concentric rings aroundpower region region 144. Insulation-filledtrenches -
Gate structures 290 for power MOSFETs are formed withinpower regions FIGS. 3a-3h . Highvoltage termination trench 292 is formed aroundgate structures 290, similar toFIG. 2l . MOSFETs incontrol region 144 and doped regions ofpower regions FIGS. 4a -4 f. - In
FIG. 6d , aninterconnect structure 300 includesconductive vias 302 formed through insulatinglayer 304 to connect to control logic transistors formed incontrol regions 144.Conductive layer 306 is formed overinsulating layer 304 andconductive vias 302. Insulatinglayer 308 is formed overconductive layers 306 and insulatinglayer 304. Additional insulating layers like 310,conductive layer 306, and conductive via 312 can be formed for electrical interconnect and routing. -
Conductive plug 314 operates as a front-side source contact throughconductive vias 302 to the power MOSFET inpower regions Drain contact 346 can be routed by bond wire or clip to the top surface of semiconductor device 340, e.g. for drain sensing.Conductive layer 316 routes electrical signals from the control logic incontrol regions encapsulant 320 is formed overconductive layer 316 andconductive plug 314 for environmental protection and structural integrity. An opening is etched through insulatinglayer 320 to exposeconductive plug 314 and contact pads ofconductive layer 316 for subsequent interconnect. - In
FIG. 6e , semiconductor device 340 is shown inverted to formtrench 342 using a backside etch, e.g. plasma etch. Trench 342 electrically isolates the drain terminal of a power MOSFET inpower region 140 a from the drain terminal of a power MOSFET inpower region 140 b.Trench 342 is formed extending totrenches 280 to complete the lateral isolation between power region 140 and controlregion 144.Trench 342 follows the path oftrenches 280. In one embodiment,trench 342 andtrench 280 extend completely around each power region 140. In combination,trench 342 andtrench 280 extend vertically completely through the die for complete isolation betweencontrol region 144 and power region 140. In some embodiments,trench 342 extends completely acrosscontrol region 144 such thatbase substrate 260 andEPI layer 262 are completely removed within the footprint ofcontrol region 144. An insulating orpassivation layer 344 is formed overbase substrate 260 and intotrench 342.Drain contact 346 is formed overbase substrate 260 for backside interconnect. - Semiconductor device 340 combines one or more power devices and control logic fully isolated (source, drain, and gate of power MOSFET and control logic) in an integrated monolithic semiconductor package using an SOI substrate or non-SOI substrate. The power devices and control logic can be lateral or high density vertical trench-based semiconductor devices with vertical conduction path from
active surface 110 to backsurface 108 in semiconductor die 102.Conductive layers Conductive layer 314 provides electrical interconnect on the first major surface for the power MOSFET, e.g. source connection.Conductive layer 346 provides electrical interconnect on a second major surface for the power MOSFET, e.g. drain connection. The drain of the power MOSFET can be routed to the first major surface for drain sensing by the control logic, seeFIG. 5 . Semiconductor device 340 provides a flexible platform for different voltages based on vertical thickness and/or trench depth. Semiconductor device 340 containing one or more isolated power devices and associated control logic can be used in many applications, such as automotive, switch mode power supplies, and diode bridges for sine-wave rectification. -
FIGS. 7a and 7b illustratediode bridge 350 for sine-wave rectification, includingdiodes Diode 352 is coupled betweenconductive layer 360 andconductive layer 362.Diode 354 is coupled betweenconductive layer 362 andconductive layer 364.Diode 356 is coupled betweenconductive layer 364 andconductive layer 366.Diode 358 is coupled betweenconductive layer 366 andconductive layer 360. - While one or more embodiments have been illustrated and described in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present disclosure.
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/017,089 US20200411555A1 (en) | 2016-07-18 | 2020-09-10 | Semiconductor device including a leadframe or a diode bridge configuration |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662363449P | 2016-07-18 | 2016-07-18 | |
US15/644,613 US10347656B2 (en) | 2016-07-18 | 2017-07-07 | Semiconductor device and monolithic semiconductor device including a power semiconductor device and a control circuit |
US16/415,164 US10804296B2 (en) | 2016-07-18 | 2019-05-17 | Semiconductor device and method including a conductive member within a trench |
US17/017,089 US20200411555A1 (en) | 2016-07-18 | 2020-09-10 | Semiconductor device including a leadframe or a diode bridge configuration |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/415,164 Division US10804296B2 (en) | 2016-07-18 | 2019-05-17 | Semiconductor device and method including a conductive member within a trench |
Publications (1)
Publication Number | Publication Date |
---|---|
US20200411555A1 true US20200411555A1 (en) | 2020-12-31 |
Family
ID=60941287
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/644,613 Active US10347656B2 (en) | 2016-07-18 | 2017-07-07 | Semiconductor device and monolithic semiconductor device including a power semiconductor device and a control circuit |
US16/415,164 Active US10804296B2 (en) | 2016-07-18 | 2019-05-17 | Semiconductor device and method including a conductive member within a trench |
US17/017,089 Abandoned US20200411555A1 (en) | 2016-07-18 | 2020-09-10 | Semiconductor device including a leadframe or a diode bridge configuration |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/644,613 Active US10347656B2 (en) | 2016-07-18 | 2017-07-07 | Semiconductor device and monolithic semiconductor device including a power semiconductor device and a control circuit |
US16/415,164 Active US10804296B2 (en) | 2016-07-18 | 2019-05-17 | Semiconductor device and method including a conductive member within a trench |
Country Status (2)
Country | Link |
---|---|
US (3) | US10347656B2 (en) |
CN (4) | CN208189591U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023140991A3 (en) * | 2021-12-17 | 2023-11-09 | Wolfspeed, Inc, | Multi-typed integrated passive device (ipd) components and devices and processes implementing the same |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10347656B2 (en) * | 2016-07-18 | 2019-07-09 | Semiconductor Components Industries, Llc | Semiconductor device and monolithic semiconductor device including a power semiconductor device and a control circuit |
DE112016007081T5 (en) * | 2016-07-20 | 2019-04-04 | Mitsubishi Electric Corporation | Semiconductor device and method for its production |
US10573803B1 (en) * | 2018-08-21 | 2020-02-25 | Semiconductor Components Industries, Llc | Current sensor packages with through hole in semiconductor |
US11664372B2 (en) * | 2019-01-30 | 2023-05-30 | United Microelectronics Corp. | Semiconductor device integrating silicon-based device with semiconductor-based device and method for fabricating the same |
US10950699B2 (en) * | 2019-08-05 | 2021-03-16 | Vishay-Siliconix, LLC | Termination for vertical trench shielded devices |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4908328A (en) * | 1989-06-06 | 1990-03-13 | National Semiconductor Corporation | High voltage power IC process |
US5049521A (en) * | 1989-11-30 | 1991-09-17 | Silicon General, Inc. | Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate |
SE521301C2 (en) * | 1998-12-08 | 2003-10-21 | Eftec Europe Holding Ag | sealing nozzle |
JP2001127270A (en) * | 1999-10-27 | 2001-05-11 | Nec Corp | Semiconductor device and manufacturing method therefor |
FR2820903B1 (en) * | 2001-02-12 | 2003-06-06 | St Microelectronics Sa | HIGH VOLTAGE TRANSLATOR TYPE SWITCHING DEVICE |
JP2003203967A (en) * | 2001-12-28 | 2003-07-18 | Toshiba Corp | Method for forming partial soi wafer, semiconductor device and its manufacturing method |
JP4290378B2 (en) * | 2002-03-28 | 2009-07-01 | Necエレクトロニクス株式会社 | Horizontal power MOS transistor and manufacturing method thereof |
US8188543B2 (en) * | 2006-11-03 | 2012-05-29 | Freescale Semiconductor, Inc. | Electronic device including a conductive structure extending through a buried insulating layer |
EP2111412A2 (en) * | 2007-02-02 | 2009-10-28 | Amgen, Inc | Hepcidin and hepcidin antibodies |
US7919800B2 (en) * | 2007-02-26 | 2011-04-05 | Micron Technology, Inc. | Capacitor-less memory cells and cell arrays |
US8278731B2 (en) * | 2007-11-20 | 2012-10-02 | Denso Corporation | Semiconductor device having SOI substrate and method for manufacturing the same |
WO2012060032A1 (en) * | 2010-11-04 | 2012-05-10 | パナソニック株式会社 | Semiconductor integrated circuit |
US9059306B2 (en) * | 2011-10-11 | 2015-06-16 | Maxim Integrated Products, Inc. | Semiconductor device having DMOS integration |
US9041105B2 (en) * | 2012-07-20 | 2015-05-26 | International Business Machines Corporation | Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure |
US20140167163A1 (en) * | 2012-12-17 | 2014-06-19 | International Business Machines Corporation | Multi-Fin FinFETs with Epitaxially-Grown Merged Source/Drains |
US9660074B2 (en) * | 2014-08-07 | 2017-05-23 | Texas Instruments Incorporated | Methods and apparatus for LDMOS devices with cascaded RESURF implants and double buffers |
US10347656B2 (en) * | 2016-07-18 | 2019-07-09 | Semiconductor Components Industries, Llc | Semiconductor device and monolithic semiconductor device including a power semiconductor device and a control circuit |
-
2017
- 2017-07-07 US US15/644,613 patent/US10347656B2/en active Active
- 2017-07-18 CN CN201820399757.6U patent/CN208189591U/en active Active
- 2017-07-18 CN CN201820399760.8U patent/CN208189592U/en active Active
- 2017-07-18 CN CN201720869307.4U patent/CN207367973U/en active Active
- 2017-07-18 CN CN201820405821.7U patent/CN208189593U/en active Active
-
2019
- 2019-05-17 US US16/415,164 patent/US10804296B2/en active Active
-
2020
- 2020-09-10 US US17/017,089 patent/US20200411555A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023140991A3 (en) * | 2021-12-17 | 2023-11-09 | Wolfspeed, Inc, | Multi-typed integrated passive device (ipd) components and devices and processes implementing the same |
Also Published As
Publication number | Publication date |
---|---|
CN208189593U (en) | 2018-12-04 |
CN207367973U (en) | 2018-05-15 |
CN208189591U (en) | 2018-12-04 |
US10347656B2 (en) | 2019-07-09 |
US10804296B2 (en) | 2020-10-13 |
US20190273094A1 (en) | 2019-09-05 |
US20180019259A1 (en) | 2018-01-18 |
CN208189592U (en) | 2018-12-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20200411555A1 (en) | Semiconductor device including a leadframe or a diode bridge configuration | |
KR101888369B1 (en) | Vertical semiconductor device with thinned substrate | |
US11817487B2 (en) | Semiconductor device and method for manufacturing the same | |
US9396997B2 (en) | Method for producing a semiconductor component with insulated semiconductor mesas | |
US8941217B2 (en) | Semiconductor device having a through contact | |
US9356017B1 (en) | Switch circuit and semiconductor device | |
US9502401B2 (en) | Integrated circuit with first and second switching devices, half bridge circuit and method of manufacturing | |
US11239188B2 (en) | Terminal structure of a power semiconductor device | |
US11367780B2 (en) | Semiconductor device having integrated diodes | |
US20120264259A1 (en) | Method for Forming a Semiconductor Device and a Semiconductor Device | |
US10490642B2 (en) | Semiconductor device having silicide layers | |
JP6133373B2 (en) | Semiconductor device with sensor potential applied to active region | |
US10636900B2 (en) | High voltage termination structure of a power semiconductor device | |
US10411126B2 (en) | Semiconductor device having a first through contact structure in ohmic contact with the gate electrode | |
US10249723B2 (en) | Semiconductor device | |
US20240234529A1 (en) | Wide band gap semiconductor device with surface insulating film |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HALL, JEFFERSON W.;GRIVNA, GORDON M.;SIGNING DATES FROM 20170710 TO 20170717;REEL/FRAME:053736/0225 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY INTEREST;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:054523/0378 Effective date: 20201105 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 054523, FRAME 0378;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:064615/0602 Effective date: 20230816 |