CN1677658A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN1677658A CN1677658A CNA2005100561952A CN200510056195A CN1677658A CN 1677658 A CN1677658 A CN 1677658A CN A2005100561952 A CNA2005100561952 A CN A2005100561952A CN 200510056195 A CN200510056195 A CN 200510056195A CN 1677658 A CN1677658 A CN 1677658A
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- conductive plug
- hole
- semiconductor device
- embolism
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract
Description
Claims (19)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004108304 | 2004-03-31 | ||
JP2004108304A JP4439976B2 (ja) | 2004-03-31 | 2004-03-31 | 半導体装置およびその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101993435A Division CN101202257B (zh) | 2004-03-31 | 2005-03-31 | 半导体器件 |
Publications (2)
Publication Number | Publication Date |
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CN1677658A true CN1677658A (zh) | 2005-10-05 |
CN100390981C CN100390981C (zh) | 2008-05-28 |
Family
ID=35050067
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101993435A Active CN101202257B (zh) | 2004-03-31 | 2005-03-31 | 半导体器件 |
CNB2005100561952A Active CN100390981C (zh) | 2004-03-31 | 2005-03-31 | 半导体器件及其制造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101993435A Active CN101202257B (zh) | 2004-03-31 | 2005-03-31 | 半导体器件 |
Country Status (4)
Country | Link |
---|---|
US (5) | US7541677B2 (zh) |
JP (1) | JP4439976B2 (zh) |
CN (2) | CN101202257B (zh) |
TW (1) | TWI253103B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102237300A (zh) * | 2010-04-27 | 2011-11-09 | 南亚科技股份有限公司 | 直通基底穿孔结构及其制造方法 |
US11380584B2 (en) | 2018-02-23 | 2022-07-05 | Sony Semiconductor Solutions Corporation | Semiconductor device and manufacturing method of semiconductor device including a through electrode for connection of wirings |
Families Citing this family (101)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090115042A1 (en) * | 2004-06-04 | 2009-05-07 | Zycube Co., Ltd. | Semiconductor device having three-dimensional stacked structure and method of fabricating the same |
WO2006019156A1 (ja) * | 2004-08-20 | 2006-02-23 | Zycube Co., Ltd. | 三次元積層構造を持つ半導体装置の製造方法 |
JP4139803B2 (ja) * | 2004-09-28 | 2008-08-27 | シャープ株式会社 | 半導体装置の製造方法 |
US7534722B2 (en) * | 2005-06-14 | 2009-05-19 | John Trezza | Back-to-front via process |
US7989958B2 (en) | 2005-06-14 | 2011-08-02 | Cufer Assett Ltd. L.L.C. | Patterned contact |
TWI416663B (zh) * | 2005-08-26 | 2013-11-21 | Hitachi Ltd | Semiconductor device manufacturing method and semiconductor device |
JP4851163B2 (ja) * | 2005-10-31 | 2012-01-11 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置の製造方法 |
US7563714B2 (en) * | 2006-01-13 | 2009-07-21 | International Business Machines Corporation | Low resistance and inductance backside through vias and methods of fabricating same |
TWI336913B (en) * | 2006-07-18 | 2011-02-01 | Via Tech Inc | A chip and manufacturing method and application thereof |
KR100824635B1 (ko) * | 2006-09-13 | 2008-04-24 | 동부일렉트로닉스 주식회사 | 시스템 인 패키지를 이용한 인덕터 제조 방법 |
DE102006046869B4 (de) * | 2006-10-02 | 2012-11-29 | Infineon Technologies Ag | Verfahren und Vorrichtung zur Herstellung einer Halbleitervorrichtung und Halbleiterwafer |
US7646064B1 (en) * | 2006-10-27 | 2010-01-12 | National Semiconductor Corporation | Semiconductor die with aluminum-spiked heat pipes |
US7544605B2 (en) * | 2006-11-21 | 2009-06-09 | Freescale Semiconductor, Inc. | Method of making a contact on a backside of a die |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
JP5266650B2 (ja) * | 2007-03-05 | 2013-08-21 | セイコーエプソン株式会社 | 半導体装置とその製造方法および電子機器 |
TWI368978B (en) * | 2007-09-21 | 2012-07-21 | Unimicron Technology Corp | Method for fabricating ball-implantation side surface structure of package substrate |
WO2009050207A1 (en) * | 2007-10-15 | 2009-04-23 | Interuniversitair Microelectronica Centrum Vzw | Method for producing electrical interconnects and devices made thereof |
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-
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Also Published As
Publication number | Publication date |
---|---|
JP4439976B2 (ja) | 2010-03-24 |
US20090215261A1 (en) | 2009-08-27 |
US8704355B2 (en) | 2014-04-22 |
US8008191B2 (en) | 2011-08-30 |
US20080265392A1 (en) | 2008-10-30 |
TW200535977A (en) | 2005-11-01 |
US20110316124A1 (en) | 2011-12-29 |
US20130032930A1 (en) | 2013-02-07 |
US7541677B2 (en) | 2009-06-02 |
CN101202257B (zh) | 2010-08-25 |
CN100390981C (zh) | 2008-05-28 |
JP2005294577A (ja) | 2005-10-20 |
US8310039B2 (en) | 2012-11-13 |
US8022529B2 (en) | 2011-09-20 |
CN101202257A (zh) | 2008-06-18 |
TWI253103B (en) | 2006-04-11 |
US20050221601A1 (en) | 2005-10-06 |
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