CN1647283A - 半导体设备 - Google Patents
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Abstract
公开了一种半导体设备,例如DRAM存储器设备。半导体材料的基底(12)被提供有形式为盒状区域(38)的能带调整装置,且该基底由一绝缘层(14)覆盖。半导体层(16)其中形成有源区(18)和漏区(20),用以限定各场效应晶体管的体(22)。盒状区域(38)的掺杂浓度高于相邻的体(22),但低于对应的源区(18)和漏区(20),且其调整体(22)的价带和/或导带,以提高可存储于体(22)内的电荷的数量。
Description
技术领域
本发明涉及一种半导体设备,具体地但并非排他地涉及例如半导体存储器的半导体存储设备,以及涉及用于制造此设备的基底。
背景技术
国际专利号为PCT/EP02/06495的文献披露了一DRAM设备(动态随机存储器),其包含一存储单元矩阵,每个单元由一场效应晶体管构成。通过在每个晶体管的栅极和漏极之间,以及源极和漏极之间施加合适的电压脉冲,就能在晶体管的体内产生并存储电荷。电荷的有无分别代表二进制数据位的“1”和“0”状态。采用SOI(硅绝缘)型场效应晶体管的存储器设备在“SOI technology:materials to VLSI”,第二版,Kluwer,波士顿,1997中有详细介绍。
用于这种设备类型的晶体管为为PD-SOI(部分耗尽SOI)晶体管,它形成在一硅层上,而所述硅层形成在一绝缘层上,每个晶体管的源极、体和漏极形成在同一层,穿过该硅层的整个厚度。然后,在该硅层上覆盖一电介质膜,而在该电介质膜上形成每个晶体管的栅极。
为了使电荷存储于这类晶体管的体内,晶体管的体在其中央部分必须有足够厚的硅层,以提供具有非耗尽区域的硅,所述非耗尽区域称为中性区,电荷就被存储在这一区域内或附近。因此,这种晶体管叫做部分耗尽晶体管。
FD-SOI(完全耗尽SOI)晶体管已经被大家所熟知,其中,与部分耗尽SOI晶体管相比,其源、漏区域的硅层厚度都更薄,而且/或者杂质浓度也更低。结果,这种设备无中性区域,这就意味着在此种晶体管中不可能存储电荷。然而,FD-SOI晶体管与PD-SOI晶体管相比,也有一系列优点,比如:极好的短沟道特性,非常快的开关频率。而这些都是由于硅层厚度较薄所致。
从图1和图2中可以看出,体(bulk)晶体管与SOI晶体管的比较。根据图1a和图2a,由基底10构成一SOI晶体管,而基底10包含一硅基底层12,一氧化硅或蓝宝石材料的绝缘层14和硅层16;在采用腔体技术的晶体管的情况下,如图1b和图2b所示,基底10只包含一硅基底层12。
参见图2a和图2b,其中,相同的部分由相同的附图标记示出,包含若干场效应晶体管(在图2a和图2b中各仅示出一个)的集成电路通过连续光刻操作形成在基底10上,在所述光刻操作中,层被部分刻蚀、掺杂,或者又沉积新层。在图2a中示意的场效应晶体管有一源极18和一漏极20,形成于层16内,一体22被限定在源极18和漏极20之间,源极18和漏极20延伸穿过层16的整个厚度。如本领域的技术人员所知,源极18、漏极20和体22都通过掺杂硅层16来形成。体22被一电介质膜24所覆盖,电介质膜24与源极18和漏极20部分重叠,其上提供栅极26。在源极18和漏极20周围的层26被除区,取而代之的是氧化硅材质的绝缘框架28。当在栅极26上施加一合适的电压时,在体22的表面与电介质膜24的界面处形成一连接源极18和漏极20的导电沟道30。
在图2b中,源区18和漏区20形成在基底层12内,以限定位于源极和漏极之间的体22,电介质膜24覆盖体22,且与源极18和漏极20部分重叠。
现在看图3a和图3b,图3b示出电势随图3a所示腔体结构晶体管的区域B的厚度Z(从与电介质膜24的界面处算起)变化的示意图。图3b中的曲线Bc、Bv和Nf分别代表体22内部的价带电势、导带电势、和费米能级。同样,图4a和图4b分别示意了PD-SOI晶体管的相应示图,图5a和图5b分别示出了FD-SOI晶体管的相应示图。
从图3b到图5b可以看到,在每种晶体管的情况下,在体22与电介质膜24的界面处,价带Bv和导带Bc都有最小值。然而,图3b也示意了电势Bv和Bc在第一区域Zd变化,但趋向一极限值,超过该极限值即开始称为中性区的第二区域Zn。该第二区域Zn延伸穿过基底层12的整个厚度。当对栅极26施加一合适的电压时,在体22与电介质膜24的界面处形成一导电沟道30。
现在看图4b,可以看出,PD-SOI晶体管有两个耗尽区Zd1和Zd2,分别邻近电介质膜24和绝缘层14,其间为中性区Zn。本领域的技术人员可知,耗尽区Zd2的形状和宽度取决于后栅级电势和前栅级电势的相对值。有可能在体22内存储电荷,具体地,在两个耗尽区Zd1和Zd2之间的中性区Zn内和附近存储电荷。此晶体管的一个可能的应用是单个存储单元,其能够根据中性区Zn之内和附近电荷的有无来代表两个逻辑状态,用于形成如DRAM的半导体存储器。
现在看图5b,可以看出,在FD-SOI晶体管的情况下,在体22的整个厚度范围内导带Bc和价带Bv的电势持续变化。换句话说,体22具有一延伸穿过其整个厚度的耗尽区Zd,结果就不存在中性区。从而也就不可能在体22中存储电荷,这种类型的晶体管因此不能被用来作为存储元件使用。当然,这种类型的晶体管也具有一些优点,具体来说,其具有极好的短沟道特性,非常快的开关频率,这些都是由于硅层16的厚度较薄所致。
本发明的优选实施例正是为了综合部分耗尽SOI晶体管与完全耗尽SOI晶体管的有优势的特点。
发明内容
根据对本发明的一个方面,提供一半导体设备,包括:
半导体材料的基底;
提供于所述基底上的第一电绝缘层;
提供于所述第一电绝缘层上的第一半导体层,其适于在其中形成至少一个场效应管的相应的源和漏区,以限定所述源区和漏区之间的一个相应的体区;和
能带调整装置,用于调整在至少一个所述场效应晶体管的所述体区内的价带和/或导带的能级来增加电荷数量,所述电荷可至少被暂时存储在所述体区内。
通过提供用于调整在至少一个所述场效应晶体管的所述体区内的价带和/或导带的能级来增加电荷数量的能带调整装置,其中,所述电荷可至少被暂时存储在所述体区内,本发明提供了惊人的优势,即可将第一半导体层制作为远比在现有技术中的薄,这意味着FD-SOI晶体管的第一半导体层的薄层(比如:较快的设备性能)可以和PD-SOI晶体管的电荷存储能力结合起来的优势。例如,本发明可用于构建一特别紧凑的半导体存储设备,其中,数据的各个位可以由存储在各晶体管体内的电荷的存在与否来表示,同时还利用高性能的晶体管。
能带调整装置还适于创建一区,其中,可至少暂时将电荷存储在在至少一个所述场效应晶体管的体区内。
在一优选实施例中,该能带调整装置适于沿基本与所述第一绝缘层垂直的方向增加一区域的长度,在所述区域内,在至少一个所述场效应晶体管的体区内的价带和导带的能量是基本恒定的。
所述能带调整装置可适于将一相应的电压变化施加于至少一个所述场效应晶体管的相应的源极、漏极和至少一个栅极。
通过向至少一个所述场效应晶体管的源极、漏极和至少一个栅极施加电压漂移,使得能够实现本发明的电荷存储能力,而不用显著地改变基底的电势。这例如通过提供可将电荷存储存储器设备与逻辑设备置于相同的基底上的优势,大大改善自该设备形成的集成设备的多样性,后者在向基底施加大的电压漂移时不能其作用,且电压漂移仅施加于基底。还提供可以最少的制造步骤制造该设备的优势。
在一优选实施例中,所述能带调整装置包括至少一个所述场效应晶体管的体区的一掺杂部分,其中,所述掺杂部分的掺杂浓度比相应所述体区的相邻部分的高。
所述掺杂部分可邻近所述第一绝缘层设置。
所述能带调整装置在使用中可包含至少一个第二半导体层,其被邻近至少一个所述场效应晶体管的源和漏区设置,且其位于所述第一绝缘层的一侧,远离所述第一半导体层。
至少一个所述第二半导体层可至少部分覆盖所述基底。
至少一个所述第二半导体层形成部分所述基底。
所述设备进一步包括接触装置,用以使该或每一个所述第二半导体层与一相应的电输入信号源相连。
该设备进一步包括形成于所述第一半导体层上的至少一个所述场效应晶体管的相应的漏和源区,以限定所述源和漏区之间的相应的体区。
所述设备还包含相邻所述场效应晶体管的相应的所述体区设置的至少一个所述场效应晶体管的至少一个相应的栅极。
所述设备进一步包含在所述第一半导体层上形成的第二绝缘层,且至少一个所述场效应晶体管的至少一个相应的栅区设置在所述第二绝缘层上。
在一优选实施例中,所述设备为半导体存储器。
根据本发明的另一方面,提供一种控制半导体设备的方法,包括:半导体材料的基底,提供于所述基底上的第一电绝缘层,以及提供于所述第一绝缘层上的第一半导体层,且其中形成至少一个场效应管的源和漏区,以限定在所述源和漏区之间的一相应的体区;所述方法包括调整在至少一个所述场效应晶体管的一相应体区内的价带和/或导带以提高电荷的数量,所述电荷可至少被暂时存储在所述体区内。
所述调整所述价带和/或导带的步骤包括将一相应的电压改变施加至所述场效应晶体管的相应的源极、漏极和至少一个栅极。
所述调整价带和/或导带的步骤包含将一相应的电压施加至至少一个第二半导体层,所述至少一个半导体层位于所述第一绝缘层的一侧,远离所述第一半导体层。
根据本发明的再一方面,提供一种半导体晶片,包括:
掺杂的半导体材料的基底;
提供于所述基底上的第一电绝缘层;
提供于所述第一电绝缘层上的第一半导体层;和
提供于所述第一电绝缘层的一侧上的至少一个第二掺杂的半导体材料层,远离所述的第一半导体层,其中,该或每个所述第二半导体层的杂质浓度远远高于与其邻近的所述基底的相应区域。
附图说明
以下参考附图,通过例子对本发明的优选实施例进行描述,其中,所述例子并非是限制性的:
图1a示出现有的应用SOI技术制造集成电路的基底的截面示意图;
图1b示出已知的应用腔体技术制造集成电路的基底的截面示意图;
图2a是已知的自图1a所示基底形成的一晶体管的截面图;
图2b是已知的自图1b所示基底形成的一晶体管的截面图;
图3a为图2b的晶体管的示意性的横截面图,示出其中考虑电势变化的区域;
图3b示出在图3a所示晶体管的区域B中的电势变化图;
图4a为应用PD-SOI技术的图2a所示晶体管的截面图;
图4b为示出在图4a所示晶体管的B区域的电势变化图;
图5a是应用FD-SOI技术的图2a所示晶体管的截面图;
图5b为示出图5a所示的晶体管的B区域中的电势变化图;
图6是本设备第一实施例的半导体设备的截面图;
图7a是本设备第二实施例的半导体设备的截面图,其能带未被调整;
图7b是图7a能带被调整的本设备的截面图;以及
图8是本发明第三实施例的半导体设备的截面图;
具体实施方式
参考图6,其中示出体现本发明的半导体设备,图6中所示设备与图5a中设备相同的部分由相同的附图标记表示。形式为硅层16的第一半导体层内形成一NMOS晶体管,并且该半导体层上覆盖一绝缘层32,其被穿孔形成窗,所述窗被填充导电材料从而形成接触区34、35,它们分别与源区18和漏区20相连。接触区34、35也分别与导线36、37相连。
图6所示的NMOS晶体管具有一n型硅层的基底层12,其具有形式为p型硅的盒状区域38的第二半导体层,该层的掺杂浓度高于体22的杂质浓度,但低于相应的源极18和漏极20的杂质浓度。通过穿过绝缘层14、框架28和绝缘层32的接触区41,盒状区域38与导线40相连。可采用0.13um技术对这类晶体管进行布局,使之具有一个400nm厚的绝缘层14和30nm厚的硅层16。应注意,单个接触区41可用于该类型的多个晶体管,且典型地,可用于成百上千个晶体管。
通过对盒状区域38施加负电压,通常在用于厚度为400nm的层14的-20V的区域,由于栅极26和盒状区域38之间的电势差,可能在体22中形成一中性区,与图4所示的PD-SOI晶体管的中性区类似。这样,就可能产生、存储和消耗该中性区内的电荷,如果减小层14的厚度,则创建中性区所需的电压也降低。由此,可使用此种晶体管将代表二进制数据的电荷,存储在例如一半导体DRAM设备或嵌入式存储设备中。在国际专利申请号为PCT/GB02/06495的文献中描述了用于产生或消除此种晶体管中的电荷的处理。在不具有盒状区38的设备的区域中,可能形成传统的PD-SOI晶体管或FD-SOI晶体管。
参考图7a和图7b,其中,与图6的实施例中相同的部件使用类似的附图标记表示,其作为一种选择方案,用以提供盒状区38,通过使体22中的价带和/或导带失真,来增加可存储在体22中的电荷的数量,有可能在栅极26和与体22相邻的基底层12之间有足够大的电势差,以在体12内提供一电荷存储中性区。这可以通过,例如向晶体管的栅极26、源极18和漏极20的每一个施加一相对高的电压偏移(例如,在20V范围内)来实现。
具体地,如图7a和图7b所示,图7a示意的完全耗尽(FD)SOI晶体管,其被偏置的方式使其表现为一标准的完全耗尽设备。在图7a中,对栅极26施加2V的电压、对漏极20施加2V的电压,而源极18保持在0V,使晶体管导通。另一方面,在图7b中示出在电力上表现为部分耗尽型(PD)设备的相同的FD-SOI晶体管。在所有的设备节点上施加20V电压使所述能带失真,造成在晶体管的体22内产生中性区23,通常,在绝缘层14的厚度是400nm时,施加20V电压。当绝缘层14的厚度更薄的情况下,所加的电压相应地成比例地减小。
图7b的布局使得能够在不需要很大程度上改变基底层12的电压的情况下,形成电荷存储中性区,且所需的制造步骤少于图6所示的设备所需的制造步骤。而且,还能提供的优点是,可将存储设备和逻辑设备做在同一基底上,由于尽管如果向基底施加大的移位电压移位(voltage shift),存储设备一般能正常工作,然而,对如处理器的逻辑设备则通常并非如此。因此,对存储设备而不对逻辑设备施加电压移位。
参见图8,其中,与图6和图7所示实施例相同的部分由相同的附图标记示出,盒状区域38由与绝缘层14、源极18和漏极20邻近的体22的下部的高掺杂区域替代。这一层所其的效果与图6的盒状区域38的效果类似。具体地,通过更重地掺杂体22的区域25来调整该晶体管的体的能带。这在体内产生了掺杂梯度。因此,体22具有一含有底掺杂内容的上部21,和含有高掺杂内容的下部25。这通过适当的离子植入,外延或扩散来实现。体下部25较高的掺杂标准使得所述能带失真,从而产生一所述能带平坦的区域,由此产生一中性区23。
由此可见,本发明能够形成这样的晶体管,其体可在远窄于现有技术的硅层中存储代表二进制数据位的电荷,且具有能够获得FD-SOI晶体管的改进的设备性能的优点。
虽然参考示出的实施例描述了本发明,但此描述不认为是限制性的。在不脱离如权利要求所限定的本发明的范围的情况下,可对本发明进行多种变化和改进。而且本领域的技术人员可知,当中性区厚度不足以达到那些电路的所期望的目的时,上述原理可适用于部分耗尽SOI型电路,且与应用于NMOS晶体管中一样,上述原理同样可应用于PMOS晶体管,在这种情况下,所施加的电压的极性与上述实施例中提出的极性相反。
Claims (18)
1.一种半导体设备,包括:
半导体材料的基底;
提供于所述基底上的第一电绝缘层;
提供于所述第一电绝缘层上的第一半导体层,其适于在其中形成至少一个场效应管的相应的源和漏区,以限定所述源区和漏区之间的一个相应的体区;和
能带调整装置,用于调整在至少一个所述场效应晶体管的所述体区内的价带和/或导带以增加电荷数量,所述电荷可至少被暂时存储在所述体区内。
2.根据权利要求1所述的设备,其中,所述能带调整装置适于创建一区,其中,可至少暂时将电荷存储在至少一个所述场效应晶体管的体区内。
3.根据权利要求1或2所述的设备,其中,所述能带调整装置适于沿基本与所述第一绝缘层垂直的方向增加一区域的长度,在所述区域内,在至少一个所述场效应晶体管的体区内的价带和导带的能量基本是恒定的。
4.根据上述权利要求中任何一项所述的设备,其中,所述能带调整装置适于将一相应的电压变化施加于至少一个所述场效应晶体管的相应的源极、漏极和至少一个栅极。
5.根据上述权利要求中任何一项所述的设备,其中,所述能带调整装置包括至少一个所述场效应晶体管的体区的一掺杂部分,其中,所述掺杂部分的掺杂浓度比相应所述体区的相邻部分的高。
6.根据权利要求5所述的设备,其中,所述掺杂部分邻近所述第一绝缘层设置。
7.根据上述权利要求中任何一项所述的设备,其中,所述能带调整装置包含至少一个第二半导体层,其被邻近至少一个所述场效应晶体管的源和漏区设置,且其位于所述第一绝缘层的一侧,远离所述第一半导体层。
8.根据权利要求7所述的设备,其中,至少一个所述第二半导体层至少部分覆盖所述基底。
9.根据权利要求7或8所述的设备,其中,至少一个第二半导体层形成部分所述基底。
10.根据权利要求7到9中任何一项所述的设备,进一步包括接触装置,用以使该或每一个所述第二半导体层与一相应的电输入信号源相连。
11.根据上述权利要求中任何一项所述的设备,进一步包括形成于所述第一半导体层上的至少一个所述场效应晶体管的相应的漏和源区,以限定所述源和漏区之间的相应的体区。
12.根据权利要求11所述的设备,还包含邻近所述场效应晶体管的相应的所述体区设置的至少一个所述场效应晶体管的至少一个相应的栅极。
13.根据权利要求12所述的设备,进一步包含在所述第一半导体层上形成的第二绝缘层,且至少一个所述场效应晶体管的至少一个相应的栅区设置在所述第二绝缘层上。
14.根据上述权利要求中任何一项所述的设备,其中,所述设备为半导体存储设备。
15.一种控制半导体设备的方法,包括:
半导体材料的基底,提供于所述基底上的第一电绝缘层,以及提供于所述第一绝缘层上的第一半导体层,且其中形成至少一个场效应管的源和漏区,以限定在所述源和漏区之间的一相应的体区,所述方法包括调整在至少一个所述场效应晶体管的一相应体区内的价带和/或导带以提高电荷的数量,所述电荷可至少被暂时存储在所述体区内。
16.根据权利要求15所述的方法,其中,调整所述价带和/或导带的步骤包括将一相应的电压改变施加至所述场效应晶体管的相应的源极、漏极和至少一个栅极。
17.根据权利要求15所述的方法,其中,所述调整价带和/或导带的步骤包含将一相应的电压施加至至少一个第二半导体层,所述至少一个第二半导体层位于所述第一绝缘层的一侧,远离所述第一半导体层。
18.一半导体晶片,包括:
掺杂的半导体材料的基底;
提供于所述基底上的第一电绝缘层;
提供于所述第一电绝缘层上的第一半导体层;和
提供于所述第一电绝缘层的一侧上的至少一个第二掺杂的半导体材料层,其远离所述第一半导体层,其中,该或每个所述第二半导体层的掺杂浓度远远高于与其邻近的所述基底的相应区域的掺杂浓度。
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2005
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Cited By (2)
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CN102088028A (zh) * | 2009-12-08 | 2011-06-08 | S.O.I.Tec绝缘体上硅技术公司 | 具有埋置绝缘层下第二控制栅极的SeOI闪存存储单元 |
CN102088028B (zh) * | 2009-12-08 | 2014-10-08 | S.O.I.Tec绝缘体上硅技术公司 | 闪存存储器单元及其控制方法,存储器阵列及其构造方法 |
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AU2003226646A1 (en) | 2003-10-27 |
US7514748B2 (en) | 2009-04-07 |
EP1357603A3 (en) | 2004-01-14 |
US20040238890A1 (en) | 2004-12-02 |
US20060006468A1 (en) | 2006-01-12 |
US7061050B2 (en) | 2006-06-13 |
EP1357603A2 (en) | 2003-10-29 |
WO2003088322A3 (en) | 2004-04-01 |
WO2003088322A2 (en) | 2003-10-23 |
AU2003226646A8 (en) | 2003-10-27 |
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