CN1714451A - 双晶体管或非器件 - Google Patents

双晶体管或非器件 Download PDF

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CN1714451A
CN1714451A CNA2003801039418A CN200380103941A CN1714451A CN 1714451 A CN1714451 A CN 1714451A CN A2003801039418 A CNA2003801039418 A CN A2003801039418A CN 200380103941 A CN200380103941 A CN 200380103941A CN 1714451 A CN1714451 A CN 1714451A
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fin fet
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CN100524762C (zh
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Z·克里沃卡皮奇
J·X·安
林明仁
汪海宏
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GlobalFoundries US Inc
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Advanced Micro Devices Inc
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Abstract

一种或非(NOR)门，由二个非对称鳍型场效应晶体管(FinFET)类型的晶体管(801、802)所构成，替代传统的由四个晶体管所构成的NOR门。晶体管数目由四个降至两个可明显增进集成的半导体电路的性能。

Description

双晶体管或非器件
发明领域
本发明涉及一种半导体制法以及半导体器件，更具体地，是涉及一种双栅极金属氧化物半导体场效应晶体管(MOSFET)。
背景技术
晶体管(如MOSFET等)是绝大多数半导体器件的核心建构模块(Core Building Block)，部分的半导体器件如高性能处理器等可包括数以百万计的晶体管。对于这些器件而言，缩小晶体管的尺寸，进而增加晶体管的密度，已成为半导体制造领域亟待解决的问题。
传统的MOSFET在50纳米以下范围的工艺极难进行。为发展次50纳米(Sub-50nm)的MOSFET，于是提出双栅极MOSFET技术。在许多方面，该双栅极MOSFET相较于传统的体硅(bulk silicon)MOSFET提供了更好的特性。此种改进的兴起是因为该双栅极MOSFET在该沟道的两侧边上具有栅极电极，而不像传统的MOSFET仅在一侧边上具有栅极电极。当具有双栅极时，通过其漏极所产生的电场从该沟道的源极端受到较佳的遮蔽(screen)。此外，双栅极能够控制大约是单一栅极两倍大的电流量，而形成更强的切换(switching)信号。
半导体器件中的晶体管经常连接成组，以实现较高水平的逻辑门电路(logical gate)。其中较常使用的逻辑门的其中一种即为“或非”(NOR)门。通常使用四个晶体管，诸如四个双栅极MOSFET，以创建一个NOR门。
如何更有效率的实现例如NOR门的逻辑门，以增进该半导体器件整体的效率，是亟待解决的问题。
发明内容
本发明的实施方式包括仅通过两个晶体管予以实现的NOR门。
本发明的一个方面是涉及一种集成(integrated)半导体器件。该器件包括多个非对称鳍型场效应晶体管(以下简称FinFET)，该FinFET中的至少一部分被配置为许多FinFET对(pairs)以定义多个的逻辑NOR门。
本发明的第二方面是涉及一种由第一双栅极晶体管与第二双栅极晶体管所构成的逻辑NOR门。连接至该第一与第二晶体管的输出信号用于反映连接至该第一与第二晶体管的两输入信号的逻辑NOR操作(operation)。
附图说明
下文将参照附图，其中具有相同参考标记符号的元件可表示类似的元件。
图1是概略示意图，是用于说明与本发明的原则一致的FinFET的顶视图；
图2至7是沿图1中A-A’线段的剖面图，是用于说明形成非对称FinFET的方法；
图8是概略示意图，是用于说明与本发明一致的方法所构成的NOR门的顶视图；以及
图9是用于说明在FinFET的两个栅极部分沉积多晶硅的示意图。
参考标记说明
100鳍型场效应晶体管(FinFET)
101源极区域                 102漏极区域
103沟道区域                 104、105栅极
210硅衬底                   220掩埋氧化物层
225鳍                       230层
235栅极介电层               240多晶硅间隔物
250非掺杂多晶硅层           251、252层
800NOR门                    801、802FinFET
810电源                  820漏极区域
821源极区域              822第一栅极
823第二栅极              824沟道区域
830漏极区域              831源极区域
832第一栅极              833第二栅极
834沟道区域              900FinFET
901多晶硅层              930氮化物层
具体实施方式
本发明的以下列详细说明参考了附图。在不同附图中所使用的相同参考标记是指相同或类似的组件。而且，下列详细说明并非用于限定。反之，本发明的范畴是由所附权利要求书及等价物所定义。
两晶体管相互连接以提供NOR门，每一个该晶体管可以是具有两个互相分离的可寻址栅极的非对称FinFET。
非对称FinFET
在以下所述的FinFET是一种双栅极MOSFET类型，在该双栅极MOSFET中的导电沟道(conducting channel)形成在通过自对准双栅极(self-aligned double gate)加以控制的垂直硅“鳍(fin)”中。FinFET是本领域所公知的。虽然传统的FinFET通常形容为“双栅极”MOSFET，但该双栅极被电性连接并且因而形成单一的逻辑化可寻址栅极。
图1是与本发明的原则一致的FinFET 100的顶视图。该FinFET 100包括源极区域101、漏极区域102、以及沟道区域103。该沟道区域103包括如下述图2所示的该晶体管的鳍。不同于传统的FinFET，该栅极两边被相互的电性连接，FinFET100还可另外包括两个可寻址栅极，标示为栅极104与105。这些栅极还可以是非对称掺杂的。栅极104可例如被注入有n型掺杂物(如As+或P+)，而该栅极105则可注入p型掺杂物(如B或BF2)，更多的细节在稍后描述。
图2至7是沿图1中的A-A’线段剖开的横截面图。图2至8分别用于显示该FinFET 100的制造工艺步骤。
请参阅图2，该FinFET 100可为包括有硅衬底210以及形成在该硅衬底210上的掩埋氧化物(Buried Oxide，BOX)层220的绝缘体上硅(Silicon On Insulator，SOI)器件。该衬底210与该层230可选择性的包含锗、金属、或这些材料的组合物(诸如锗硅)。该掩埋氧化物层220可依传统的方法形成在该硅衬底210上。该掩埋氧化物层220的厚度范围可例如在接近200纳米至400纳米之间。
将硅层硅形成在该掩埋氧化物层220上且通过蚀刻以形成源极、漏极、以及鳍225(源极与漏极并未显示在图2中)。此外，该源极/漏极区域101与102可通过沉积硅并在该鳍225形成后蚀刻该硅层而形成。在一个实施例中，该鳍225的宽度范围可例如介于接近5纳米至约225纳米之间。在蚀刻该鳍225之前，氮化硅(Si3N4)层230通过化学气相沉积(ChemicalVapor Deposition，CVD)被沉积在该鳍225上。该层230也可以是二氧化硅(SiO2)层。该层230用于在制造过程中保护该鳍225，并且将该层230的厚度沉积至约20至50纳米范围间。
通过氧化该鳍225的硅层表面，在该鳍225侧表面上长出栅极介电层235。该栅极介电层235的宽度可薄到0.8纳米至2纳米间。
请参阅图3，通过传统的沉积与蚀刻技术在该鳍235的周围形成多晶硅间隔物240(同时也环绕着该栅极介电层235与层230)。
接着可对该多晶硅间隔物240使用斜向注入工艺(请参阅图4)注入n型掺杂物。该掺杂物可例如为As+或P+，且可在倾斜角度介于15与45度间使用3至6keV(注入P+时)或12至15keV(注入As+时)离子束加以注入。由于该鳍型结构的存在，包括栅极介电层235与层230，该n型掺杂物将受该多晶硅间隔物240的一个侧边(如图4中所示的右侧)大规模地阻挡。
紧接在该n型掺杂物注入之后，对该多晶硅间隔物可使用斜向注入工艺注入p型掺杂物。该注入工艺的离子束可依与图4所示角度的互补角度而倾斜。该掺杂物可例如为B或BF2，且可在倾斜角度介于15与45度间使用1至2keV(注入B时)或4至8keV(注入BF2时)离子束加以注入。由于该鳍结构225的存在，包括栅极介电层235与层230，该p型掺杂物将受该多晶硅间隔物240的一个侧边(如图5中所示的左侧所示者)大规模地阻挡。据此，该两个多晶硅间隔物240将非对称地掺杂有n型与p型掺杂物。本领域技术人员应了解，图4与图5的步骤其顺序可轻易互换。
请参阅图6，接着将未掺杂的多晶硅层250沉积在该FinFET 100上。该多晶硅层250将形成该FinFET 100的栅极。该多晶硅层250可通过例如化学气相沉积(CVD)被沉积至接近100纳米的深度。
在沉积该多晶硅层250之后，如图7A所示，可将该FinFET100平坦化以使该多晶硅层250实质上与该层230的上表面齐平。这产生了两个未电性连接的多晶硅层，这些多晶硅层被标示为层251及252。如图7B所示，接着可对FinFET 100进行退火以形成完全硅化的多晶硅层251及252。该层251与252可连接至该栅极104与105且可独立地加以控制。
可选择性地使用其它生成非对称FinFET的工艺，例如显示在图7B中的这些。举例言的，可在该多晶硅栅极材料沉积且平坦化之后实施如图4与图5所示的斜向注入工艺。在每一种情况下，所得的结构均包括如图7B所示的该两个相互分离的可控制栅极。
NOR门
NOR门是常用于集成电路中的逻辑门。NOR门依据二个或更多的输入信号而输出值。以往地是，NOR门通过使用四个晶体管而构成。具有二个输入的NOR门的逻辑显示于下列的表1中。
    表1
    输入A     输入B     输出
    0     0     1
    0     1     0
    1     0     0
    1     1     0
与本发明的一个方面一致的是，NOR门是利用如FinFET100等的两个非对称FinFET而构成。图8是利用与本发明一致的方法所构成的NOR门800的顶视图。该NOR门800可设置在集成的半导体器件中。
该NOR门800包括标示为FinFET 801与802的两个FinFET。每一个FinFET 801及802均与该FinFET 100类似。具体而言，FinFET 801包括漏极区域820、源极区域821、第一栅极822、第二栅极823以及沟道(鳍型)区域824。该FinFET802同样也包括漏极区域830、源极区域831、第一栅极832、第二栅极833以及沟道区域834。该第一栅极822与832可掺杂有n型杂质而该第二栅极823与833则可掺杂有p型杂质。
如图8所示，该栅极822与832可电性连接；该栅极823与833可电性连接；且该源极区域821可电性连接至该漏极区域830。该漏极区域820可连接至接地端，且该源极区域831可连接至电源810。
在操作时，NOR门800的输出信号线(如图8所标示的输入“A”与“B”)应用在该第一与第二对电性连接的栅极。因此，输入信号线A连接至该栅极823与833，而该输入信号线B则连接至该栅极822与832。该NOR门800的输出信号是在该源极区域821与漏极区域830之间取得的。该输出值则依据上述的表1所示由该输入A与B加以决定。
附带说明
在某些情况下，期望形成包括两个传统FinFET的集成电路，该集成电路具有单独连接的双栅极以及如前述的具有两个互相分离的可寻址栅极的非对称FinFET。在此情况下，所有的FinFET可如图2至图7所示被初始形成。然后可在这些作为传统的FinFET上应用额外选定的外延生长步骤。
图9说明了在FinFET 900的两个栅极部分上沉积的多晶硅。多晶硅层901可选择性形成在设计成具有单独连接的栅极结构的集成电路中的FinFET上。该多晶硅层901例如可以通过可选择的外延生长而形成至100内米的厚度。
在其它的情况下，也可令该FinFET形成为肖特基(Schottky)型源极/漏极形式。这可使用镶嵌(damascene)技术而完成，其中，形成在该鳍上的氮化物层用于作为蚀刻阻挡层。请参阅图9，多晶硅层901可用作蚀刻阻挡层，以在该氮化物层930的上蚀刻沟槽。在移除该硅化物之后，在该源极/漏极区域上留下沟槽。接着可将该氮化物层930用作阻挡层以进行沉积与抛光。该金属与该硅沟道形成肖特基接触。
结论
前述的NOR门可由二个FinFET型晶体管替代传统的由四个晶体管所构成的NOR门。因此，此处所述的NOR门仅利用传统晶体管的一半数量，由此在栅极密度与该集成硅化物器件的整体功能方面均能明显的增进。
在先前的叙述中，为了提供本发明的全盘了解，提了为数众多的特定细节，例如特定的材料、结构、化学材料以及工艺等等。然而，本发明可在不依据在此所提出的这些特定细节下予以实施。换言之，传统的处理结构并未详细的描述，以避免模糊本发明的特征所在。
依据本发明用于制造半导体器件的该介电层与该导电层可通过传统的沉积技术而沉积。举例而言，在金属化技术中，如包括低压化学气相沉积(LPCVD)以及增强型化学气相沉积(ECVD)等不同类型的化学气相沉积(CVD)工艺均可予以利用。
本发明适用于半导体器件的制造且特别适用于设计尺寸在100纳米以下的半导体器件的制造，由此增进晶体管与电路速度并提升可靠性。本发明适用于形成任何不同类型的半导体器件，因此，为避免模糊本发明的特征所在，细节的部分并未予以提出。本发明在实施时，可利用传统的光刻与蚀刻技术，因此，这些技术的细节并未详细的提出。
在本揭露中所示与所述者仅为本发明的较佳实施例以及一些多用途的例子。应了解的是，在不背离本发明的概念在此所表达的范畴下，本发明可用于其它结合及环境中并且可进行修饰。

Claims (10)

1.一种或非(NOR)门，包括：
第一鳍型场效应晶体管(FinFET)(801)，包括独立可控制的第一栅极与第二栅极区域(822、823)、源极区域(821)、以及漏极区域(820)；
第二鳍型场效应晶体管(802)，包括独立可控制的第一栅极与第二栅极区域(832、833)、源极区域(831)、以及漏极区域(830)；
该NOR门的第一输入线，其连接至该第一鳍型场效应晶体管(801)的第一栅极区域(822)以及该第二鳍型场效应晶体管(802)的第一栅极区域(832)；
该NOR门的第二输入线，其连接至该第一鳍型场效应晶体管(801)的第二栅极区域(823)以及该第二鳍型场效应晶体管(802)的第二栅极区域(833)；以及
该NOR门的输出线，其连接至该第一鳍型场效应晶体管(801)的源极区域(820)以及该第二鳍型场效应晶体管(802)的漏极区域(830)。
2.如权利要求1所述的NOR门，其中该第一与第二鳍型场效应晶体管的第一栅极区域掺杂有n型杂质。
3.如权利要求2所述的NOR门，其中该第一与第二鳍型场效应晶体管的第二栅极区域掺杂有p型杂质。
4.如权利要求1所述的NOR门，其中该第一与第二鳍型场效应晶体管是该NOR门中仅有的晶体管。
5.一种包括多个鳍型场效应晶体管(801、802)的集成半导体器件，该器件的特征在于：
至少部分的鳍型场效应晶体管被设置成用于定义逻辑NOR门的鳍型场效应晶体管对。
6.如权利要求5所述的集成半导体器件，其中这些鳍型场效应晶体管对包括：
第一鳍型场效应晶体管(801)，包括相互独立可控制的第一栅极与第二栅极区域(822、823)、源极区域(821)、以及漏极区域(820)；
第二鳍型场效应晶体管(802)，包括相互独立可控制的第一栅极与第二栅极区域(832、833)、源极区域(831)、以及漏极区域(830)；
第一输入线，其连接至该第一鳍型场效应晶体管(801)的第一栅极区域(822)以及该第二鳍型场效应晶体管(802)的第一栅极区域(832)；
第二输入线，其连接至该第一鳍型场效应晶体管(801)的第二栅极区域(823)以及该第二鳍型场效应晶体管(802)的第二栅极区域(833)；以及
输出线，其连接至该第一鳍型场效应晶体管(801)的源极区域(821)以及该第二鳍型场效应晶体管(802)的漏极区域(830)。
7.一种逻辑NOR电路，包括：
第一双栅极晶体管(801)；以及
第二双栅极晶体管(802)，
其中连接至该第一与第二晶体管的输出信号反映施加在该第一与第二晶体管的两个输入信号的逻辑NOR操作。
8.如权利要求7所述的逻辑NOR电路，其中该第一与第二双栅极晶体管是鳍型场效应晶体管。
9.如权利要求7所述的逻辑NOR电路，其中该第一与第二双栅极晶体管均包括：
第一栅极区域(822或832)；
第二栅极区域(823或833)，其架构为可独立于该第一栅极区域而加以控制；
源极区域(821或831)；以及
漏极区域(820或830)。
10.如权利要求9所述的逻辑NOR电路，其中该第一栅极区域掺杂有n型掺杂物。
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