CN1494153A - 半导体器件结构及其制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000005669 field effect Effects 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 6
- 230000007704 transition Effects 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 238000000034 method Methods 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000010415 tropism Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
本发明公开了一种半导体器件结构，其在同一衬底上具有至少两个场效应晶体管，该第一场效应晶体管包括具有第一宽度的间隔壁，而该第二场效应晶体管包括具有第二宽度的间隔壁，该第一宽度不同于该第二宽度。优选该第一宽度比该第二宽度窄。
Description
技术领域
本发明涉及半导体器件结构，并且特别涉及形成于同一衬底上的场效应晶体管(FET)器件结构，及其制造方法。
背景技术
在互补金属氧化物半导体(CMOS)技术中，优化NFET和PFET器件以实现所需的CMOS性能。因此，对NFET和PFET器件使用极不相同的杂质种类。这些种类具有极不相同的物理性质，诸如扩散速率和最大活化浓度。在传统的CMOS技术中，NFET和PFET通常采用相同的间隔壁工艺和技术。为了优化CMOS性能，间隔壁通常具有最大化的宽度，并且设计为在NFET与PFET的性能之间实现平衡。例如，若将砷和硼分别用作NFET和PFET的源极/漏极杂质，公知越窄的间隔壁对于NFET越好，而越宽的间隔壁对于PFET越好，因为砷扩散得比硼慢得多。在此情况下，PFET是一个限制因素。因此，所有间隔壁的最大宽度为PFET而优化，兼顾NFET的性能。例如，参见：美国专利第5547894号(1996年8月20日授予Mandelman等人，名为“CMOS Processing with Low and High-Current FETS”)；美国专利第4729006号(1988年3月1日授予Dally等人，名为“SidewallSpacers for CMOS Circuit Stress Relief/Isolation and Method for Making”)；以及美国专利第4648937号(1987年3月10日授予Ogura等人，名为“Methodof Preventing Asymmetric Etching of Lines in Sub-Micrometer Range SidewallImages Transfer”)，这些文献都在此作为参考引入。
因此，存在了在同一衬底上为NFET和PFET两者优化间隔壁宽度和FET性能的问题。
发明内容
本发明通过在同一衬底上使用双重间隔壁宽度来允许独立地优化NFET或PFET器件性能，从而解决这一问题。
本发明的主要目的在于优化具有共同半导体衬底的两个不同MOS器件的性能。
本发明的额外目的在于独立地优化形成在一个衬底上的NFET器件和PFET器件的性能。
本发明的再一个目的在于增大NFET器件的驱动电流性能，同时减小PFET的短通道效应。
根据本发明，一种半导体器件结构，包括：至少第一和第二场效应晶体管，形成于一个衬底上；所述第一场效应晶体管包括具有第一宽度的第一间隔壁；所述第二场效应晶体管包括具有第二宽度的第二间隔壁；以及，所述第一宽度与所述第二宽度不同。
本发明还包括用于制造半导体器件结构的方法(工艺)。
附图说明
本发明的这些以及其它的目的、优点和方面将通过下面结合附图对优选实施例进行详细的描述而得到更好的理解。
图1为根据本发明的在同一衬底上具有不同间隔壁宽度的两个彼此相邻的MOSFET的侧面示意图；
图2为根据本发明的在同一衬底上的彼此相邻的具有较窄间隔壁的n型MOSFET和具有较宽间隔壁的p型MOSFET的侧面示意图；
图3(a)为根据本发明的具有双重宽度的间隔壁的变极器电路的电路示意图，而图3(b)为其晶片上布局图的顶视平面图；
图4为部分处理的具有栅极叠层、间隔壁延伸区、注入延伸区和隔离区的MOSFET器件结构的侧面示意图；
图5示出了图4的结构，在沉积了电介质薄膜220后；
图6示出了图5的结构，在沉积了另外的电介质薄膜230后；
图7示出了图6的结构，在构图了光致抗蚀剂240后；
图8示出了图7的结构，在去除了电介质230的露出部分并去除了光致抗蚀剂240后；
图9示出了图8的结构，在方向性蚀刻后，该方向性蚀刻仅于PFET一例上形成了包括电介质230的间隔壁260；
图10示出了图6的结构，在方向性蚀刻后，该方向性蚀刻于NFET和PFET两侧上形成了包括电介质230的间隔壁270；
图11示出了图10的结构，在构图了光致抗蚀剂280后；
图12示出了图11的结构，在去除了电介质230的露出部分并去除了光致抗蚀剂280后；
图13示出了图12或图9的结构，在方向性蚀刻后，该方向性蚀刻于NFET一侧上形成窄间隔壁300并于PFET一侧上形成L形复合间隔壁290；
图14示出了图13的结构，在注入源极/漏极310、320和形成硅化物330后；以及
图15为图14示出的所发明的结构的截面示意图，但进一步清晰了本发明的优选特征S1和S2。
具体实施方式
首先介绍本发明的最终结构(图1、2、14和15)，随后介绍工艺过程。图1示出了形成于同一半导体衬底10上的、具有两个不同间隔壁120、130的两个MOSFET100、110。间隔壁120具有比间隔壁130的宽度(W2)小的宽度(W1)。衬底为体材料晶片、SOI晶片、GaAs或任何类型的半导体衬底。如果需要满足不同的晶体管的需要，不同间隔壁宽度的数量可多于两个。根据本发明的优选实施例，如图2所示，存在对于NFET 140和PFET 150的不同的间隔壁宽度。PFET 150具有比NFET 140更宽的间隔壁170。为讨论将间隔壁120、130、160、170作为单个的间隔壁示意地示出，但应该理解其包括多个层(复合间隔壁)。为了最小化已知的源极/漏极阻抗，较窄的间隔壁160有利于优化注入NFET中的源极/漏极的N+杂质。图3(a)和图3(b)示出了使用本发明的电路和布局图的示例。图3(a)示出了变极器电路示意图，而图3(b)示出了相应的晶片上布局图(on-wafer layout)。在附图中，PFET150示为在NFET 140的顶上。间隔壁宽度从PFET区域中的宽变为NFET区域中的窄。转变区R近似位于两个器件140、150之间的中间区域。
图4至图14示出了根据本发明的两种可选的工艺流程。两种流程都开始于图4，其中按传统方式形成隔离区190、栅极叠层200、注入延伸区215和间隔壁延伸区210。然后，沉积电介质薄膜220(例如，CVD氮化物)(见图5)。然后，再沉积第二电介质膜230(例如，CVD氧化物)(见图6)。在第一种工艺流程中，应用光刻(图7)。光致抗蚀剂240覆盖PFET一侧，而随后通过湿法蚀刻或干法蚀刻去除电介质230露出的部分(图8)。这一步骤留下了仅保留在PFET一侧上的电介质薄膜230的另外一部分250。然后，使用方向性蚀刻(directional etch)仅在PFET一侧上形成间隔壁(S)260(图9)。
相同的中间结构(图9)也可通过可选择的工艺流程实现。该流程起始于图6，其中沉积了第二电介质薄膜230。然后，进行方向性蚀刻从而在NFET和PFET两侧用电介质230形成间隔壁270(图10)。然后，应用光刻(图11)。光致抗蚀剂280覆盖PFET一侧，并去除NFET一侧的间隔壁(图12)。去除光致抗蚀剂，这导致了间隔壁260仅在PFET一侧上。该结构在此阶段与由前述流程形成的结构相同(图9)。
从图9或图12中的任意一个结构对第一电介质220进行另外的方向性蚀刻将导致NFET一侧上的窄间隔壁300和PFET一层上的L形间隔壁290。最终的结构(图14)在利用传统工艺进行形成n型310和p型320源极/漏极，以及形成硅化物330后形成。
为概括，根据本发明的可选的优选工艺步骤：
1)提供起始晶片衬底(例如，体材料、SOI、GaAs)。
2)进行传统的CMOS器件处理：
器件隔离；
形成栅极叠层；
延伸注入物。
3)沉积电介质薄膜220(例如，CVD氮化物)。膜厚应最小化，从而形成最高的可能NFET驱动电流。氮化物厚度为多晶硅栅极间隔S1(图15)确定了最终的硅化物。多晶硅化物间隔对于实现高NFET驱动电流(漏极输出的饱和驱动电流)至关重要。沉积厚度优选在10nm至40nm的范围内。
4)沉积第二电介质膜230(例如，CVD氧化物)。此膜厚选择为自主地优化PFET短通道控制(对漏电流的控制)。膜230的厚度为多晶硅栅极间隔S2(图15)确定了最终的硅化物。可选择40nm至100nm范围内的膜厚度。
使用仅覆盖PFET器件的第二电介质膜230的间隔壁可利用两种独立的方法形成：
工艺选项#1：
5a)图案化光致抗蚀剂240，从而覆盖PFET器件并露出NFET器件。从NFET器件中通过湿法或干法蚀刻去除第二电介质膜230。通过传统的方法去除光致抗蚀剂240。现在第二电介质膜仅覆盖PFET器件。
5b)使用方向性蚀刻从第二电介质膜形成间隔壁。此间隔壁260仅形成于PFET器件上。
工艺选项#2
5aa)使用方向性蚀刻从第二电介质膜形成间隔壁。此间隔壁形成于NFET和PFET器件两者上。
5bb)图案化光致抗蚀剂从而覆盖PFET器件并露出NFET器件。从NFET器件通过湿法或干法蚀刻去除间隔壁。使用第二电介质膜形成的间隔壁仅覆盖PFET器件。
6)利用第二次方向性蚀刻形成NFET器件上的、窄的、I形间隔壁，以及PFET器件上的、宽的、L形间隔壁。
7)在形成n型和p型源极/漏极，并形成硅化物后，形成最终的结构。
优选：W2在50nm至120nm的范围内；
S1在1nm至20nm的范围内基本均匀；
S2在30nm至90nm的范围内基本均匀。
Claims (10)
1.一种半导体器件结构，包括：
至少第一和第二场效应晶体管，形成于一个衬底上；
所述第一场效应晶体管包括具有第一宽度的第一间隔壁；
所述第二场效应晶体管包括具有第二宽度的第二间隔壁；以及
所述第一宽度与所述第二宽度不同。
2.如权利要求1所述的结构，其特征在于，所述第一场效应晶体管为NFET而所述第二场效应晶体管为PFET。
3.如权利要求1所述的结构，其特征在于，所述第一宽度小于所述第二宽度。
4.如权利要求1所述的结构，其特征在于，所述结构为变极器。
5.如权利要求1所述的结构，其特征在于，所述结构包括一宽度转变区域，该区域近似位于所述晶体管之间的中间区域。
6.如权利要求1所述的结构，其特征在于，所述第一间隔壁为I形而所述第二间隔壁具有L形部分。
7.如权利要求1所述的结构，其特征在于，所述第一间隔壁为I形，并且所述I形间隔壁的宽度(W1)被最小化以增大NFET的电流。
8.如权利要求1所述的结构，其特征在于，所述第二间隔壁为L形，并且所述L形间隔壁的宽度(W2)被最大化以减小PFET的短通道效应。
9.如权利要求1所述的结构，其特征在于，所述第一宽度为10nm至40nm范围内的基本均匀的宽度，而所述第二宽度为50nm至120nm范围内的基本均匀的宽度
10.一种制造半导体器件结构的方法，包括：
提供半导体衬底；
形成衬底上的栅极叠层、栅极叠层上的间隔壁延伸区、临近间隔壁延伸区的注入延伸区、以及至少两个注入延伸区之间的隔离区；
向栅极叠层、间隔壁延伸区和注入延伸区上沉积第一电介质材料；
向第一电介质材料上沉积第二电介质材料；
遮蔽第二电介质材料位于一个栅极叠层上方的第一部分；
去除第二电介质材料位于另一栅极叠层上方的第二部分；
蚀刻第一部分以形成接近该一个栅极叠层的中间间隔壁；以及
蚀刻第一电介质材料以形成接近该另一栅极叠层的窄间隔壁和接近该一个栅极叠层的宽间隔壁。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/277,907 | 2002-08-26 | ||
| US10/277,907 US6806584B2 (en) | 2002-10-21 | 2002-10-21 | Semiconductor device structure including multiple fets having different spacer widths |
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| Publication Number | Publication Date |
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| CN1494153A true CN1494153A (zh) | 2004-05-05 |
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| CNA031585469A Pending CN1494153A (zh) | 2002-10-21 | 2003-09-18 | 半导体器件结构及其制造方法 |
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|---|---|
| US (1) | US6806584B2 (zh) |
| JP (1) | JP2004146824A (zh) |
| KR (1) | KR100544546B1 (zh) |
| CN (1) | CN1494153A (zh) |
| TW (1) | TWI247385B (zh) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103563066A (zh) * | 2011-06-12 | 2014-02-05 | 国际商业机器公司 | 互补双极型反相器 |
| CN105185785A (zh) * | 2014-06-13 | 2015-12-23 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
| CN106816369A (zh) * | 2015-11-30 | 2017-06-09 | 台湾积体电路制造股份有限公司 | 间隔件结构及其制造方法 |
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-
2002
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- 2003-09-18 CN CNA031585469A patent/CN1494153A/zh active Pending
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103563066A (zh) * | 2011-06-12 | 2014-02-05 | 国际商业机器公司 | 互补双极型反相器 |
| CN103563066B (zh) * | 2011-06-12 | 2016-03-16 | 国际商业机器公司 | 互补双极型反相器 |
| CN105185785A (zh) * | 2014-06-13 | 2015-12-23 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
| CN105185785B (zh) * | 2014-06-13 | 2020-11-27 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
| CN106816369A (zh) * | 2015-11-30 | 2017-06-09 | 台湾积体电路制造股份有限公司 | 间隔件结构及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004146824A (ja) | 2004-05-20 |
| KR100544546B1 (ko) | 2006-01-24 |
| TW200406881A (en) | 2004-05-01 |
| US20040075151A1 (en) | 2004-04-22 |
| KR20040034391A (ko) | 2004-04-28 |
| TWI247385B (en) | 2006-01-11 |
| US6806584B2 (en) | 2004-10-19 |
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