CN105185785A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN105185785A
CN105185785A CN201510323633.0A CN201510323633A CN105185785A CN 105185785 A CN105185785 A CN 105185785A CN 201510323633 A CN201510323633 A CN 201510323633A CN 105185785 A CN105185785 A CN 105185785A
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layer
semiconductor layer
skew
isolation part
semiconductor
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CN105185785B (zh
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尾田秀一
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明涉及半导体装置及其制造方法，提高具有完全耗尽型SOI晶体管的半导体装置的可靠性以及性能。将在栅极电极(GE)的侧壁形成的偏移隔离部(OF)的宽度(Losw)设定为半导体层(SL)的厚度(Tsi)以上且半导体层(SL)的厚度(Tsi)与绝缘膜(BX)的厚度(Tbox)的合计厚度以下，将杂质离子注入到未被栅极电极(GE)以及偏移隔离部(OF)覆盖的半导体层(SL)。由此，使得通过杂质的离子注入形成的扩展层(EX)不从栅极电极(GE)的端部下方进入到沟道内。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造技术，能够适当地利用例如使用SOI(SiliconOnInsulator，绝缘体上硅结构)基板的半导体装置及其制造方法。
背景技术
在日本特开2003-100902号公报(专利文献1)中，记载了例如在低电压nMOS区域形成nMOS晶体管的扩展层之后，在栅极电极的侧面形成偏移隔离部，其后，在低电压pMOS区域形成pMOS晶体管的扩展层的技术。
另外，在日本特开2014-038878号公报(专利文献2)中记载了一种半导体装置，该半导体装置具有：在SOI基板的半导体层上隔着栅极绝缘膜而形成的栅极电极、在栅极电极的侧壁上形成的边墙隔离部、在半导体层上外延生长了的源极漏极用的半导体层以及在源极漏极用的半导体层的侧壁上形成的边墙隔离部。
现有技术文献
专利文献
专利文献1：日本特开2003-100902号公报
专利文献2：日本特开2014-038878号公报
发明内容
在完全耗尽型SOI晶体管中，由于伴随着微型化，栅极电极与源极漏极的重叠(栅极重叠)变大，从而担心由DIBL(DrainInducedBarrierLowering，漏致势垒降低)的劣化、栅极漏电流的增加、GIDL(GateInducedDrainLeak，栅致漏极泄漏)的增加、寄生电容的增加所导致的开关速度的降低等。
其他课题与新的特征根据本说明书的叙述以及附图将变得明确。
根据一种实施方式，在使用具有半导体基板、半导体基板上的绝缘膜以及绝缘膜上的半导体层的SOI基板的半导体装置中，将在完全耗尽型SOI晶体管的栅极电极的侧壁形成的偏移隔离部的宽度设定为半导体层的厚度以上且半导体层与绝缘膜的合计厚度以下。然后，通过以栅极电极以及偏移隔离部作为掩模向半导体层进行杂质的离子注入，来形成完全耗尽型SOI晶体管的扩展层。
根据一种实施方式，能够提高具有完全耗尽型SOI晶体管的半导体装置的可靠性以及性能。
附图说明
图1是说明本实施方式的第一完全耗尽型SOI晶体管的构造的主要部分剖视图。
图2是说明本实施方式的第一完全耗尽型SOI晶体管的扩展层的结构的概略剖视图。图2(a)是放大地示出具有最小宽度的偏移隔离部的第一完全耗尽型SOI晶体管的一部分的概略剖视图，图2(b)是放大地示出具有最大宽度的偏移隔离部的第一完全耗尽型SOI晶体管的一部分的概略剖视图。
图3是说明本实施方式的第二完全耗尽型SOI晶体管的扩展层的结构的概略剖视图。图3(a)是放大地示出第二完全耗尽型n沟道SOI晶体管的一部分的概略剖视图，图3(b)是放大地示出第二完全耗尽型p沟道SOI晶体管的一部分的概略剖视图。
图4是说明本实施方式的第三完全耗尽型SOI晶体管的扩展层的结构的概略剖视图。图4(a)是放大地示出第三完全耗尽型n沟道SOI晶体管的一部分的概略剖视图，图4(b)是放大地示出第三完全耗尽型p沟道SOI晶体管的一部分的概略剖视图。
图5是示出本实施方式的半导体装置的制造工序的主要部分剖视图。
图6是接着图5的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图7是接着图6的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图8是接着图7的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图9是接着图8的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图10是接着图9的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图11是接着图10的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图12是接着图11的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图13是接着图12的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图14是接着图13的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图15是接着图14的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图16是接着图15的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图17是接着图16的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图18是接着图17的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图19是接着图18的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图20是接着图19的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图21是接着图20的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图22是接着图21的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图23是接着图22的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图24是接着图23的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图25是接着图24的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图26是接着图25的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
图27是接着图26的半导体装置的制造工序中的与图5相同的部位的主要部分剖视图。
具体实施方式
以下的实施方式中，在为了方便而需要时，分割成多个部分或者实施方式来进行说明，但除了在特别明确说明的情况下，它们并非相互无关，存在着其中一个是另一个的一部分或者全部的变形例、详细说明、补充说明等的关系。
另外，在以下的实施方式中，在提及要素的数量等(包括个数、数值、量、范围等)的情况下，除了在特别明确说明的情况以及从原理上明确地限定于确定的数量的情况等下，并非限定于该确定的数量，也可以是确定的数量以上或以下。
另外，在以下的实施方式中，关于其结构要素(也包括要素步骤等)，除了在特别明确说明的情况以及从原理上明确地认为是必需的情况等下，不一定是必需的，这自不待言。
另外，在提到“由A构成”、“由A组成”、“具有A”、“包括A”时，除了在特别明确说明仅指该要素的意思的情况下等，并非排除它之外的要素，这自不待言。同样地，在以下的实施方式中，在提及结构要素等的形状、位置关系等时，除了在特别明确说明的情况以及从原理上明确地认为并非这样的情况下等，设为包括实质上与该形状等近似或者类似的形状等。这对于上述数值以及范围也一样。
另外，在以下的实施方式中，将代表场效应晶体管的MISFET(MetalInsulatorSemiconductorFieldEffectTransistor，金属绝缘体半导体场效应晶体管)简称为晶体管。另外，在以下的实施方式中使用的附图中，即使是俯视图，为了容易观察附图，有时也附加剖面线。另外，在用于说明以下的实施方式的全部附图中，原则上对具有相同功能的部件附加相同的标号，省略其重复的说明。以下，根据附图，详细说明本实施方式。
(课题的详细说明)
为了让本实施方式的半导体装置被认为更加明确，针对通过本发明者发现的完全耗尽型SOI晶体管中的要解决的课题来进行说明。
在完全耗尽型SOI晶体管中，伴随着微型化，如果源极漏极深深地进入到沟道内，则产生有效沟道长变短、漏极电场对源极造成影响而沟道表面的电位降低的被称为所谓DIBL的现象。
另外，如果源极漏极与栅极电极的重叠(栅极重叠)变大，则在重叠部分，源极与栅极电极之间以及漏极与栅极电极之间的栅极漏电流增加。进而，如果对栅极电极施加电压，则上述重叠部分耗尽化，发生碰撞电离化而GIDL增加。
另外，在上述重叠部分，如果源极与栅极电极之间以及漏极与栅极电极之间的重叠电容增加，则完全耗尽型SOI晶体管的开关速度降低，进而半导体装置的电路动作速度降低。
(实施方式)
<第一完全耗尽型SOI晶体管的构造>
使用图1来说明本实施方式的第一完全耗尽型SOI晶体管的构造。图1是说明本实施方式的第一完全耗尽型SOI晶体管的构造的主要部分剖视图。
完全耗尽型SOI晶体管形成于包括由单晶硅构成的半导体基板SB、在半导体基板SB上形成的由氧化硅构成的绝缘膜(嵌入绝缘膜、嵌入氧化膜、BOX(BuriedOxide，隐埋氧化物)膜)BX以及在绝缘层BX上形成的由单晶硅构成的半导体层(SOI层、硅层)SL的SOI基板的主表面。半导体基板SB是支撑绝缘层BX和其上方的构造的支撑基板。绝缘膜BX的厚度是例如10～20nm左右，半导体层SL的厚度是例如10～20nm左右。
在半导体层SL上，隔着栅极绝缘膜GI而形成栅极电极GE。栅极绝缘膜GI例如由氧化硅膜或者氧氮化硅膜形成。栅极绝缘膜GI的厚度是例如2～3nm左右。作为其他形式，作为栅极绝缘膜GI，也能够使用介电常数比氮化硅膜更高的高介电常数栅极绝缘膜(例如氧化铪膜或者氧化铝膜等金属氧化物膜)。
栅极电极GE由导电膜例如多晶硅膜(多晶硅膜、掺杂多晶硅膜)形成。作为其他形式，作为栅极电极GE，也能够使用金属膜或者表现出金属传导性的金属化合物膜。
栅极电极GE的下方的半导体层SL为形成完全耗尽型SOI晶体管的沟道的区域。另外，在栅极电极GE的侧壁，隔着偏移隔离部OF而形成边墙SW。偏移隔离部OF以及边墙SW由绝缘膜构成。
在半导体层SL中的未被栅极电极GE、偏移隔离部OF以及边墙SW覆盖的区域上，选择性地形成外延层EP。因此，在栅极电极GE的两侧(栅极长度方向的两侧)，隔着偏移隔离部OF以及边墙SW而形成外延层EP。
在栅极电极GE的两侧(栅极长度方向的两侧)的半导体层SL以及外延层EP中，形成完全耗尽型SOI晶体管的源极漏极用的半导体区域，该源极漏极用的半导体区域由扩展层EX以及杂质浓度比扩展层EX高的扩散层SD构成。
即，在偏移隔离部OF以及边墙SW的下方的半导体层SL中，在隔着沟道相互间隔开的区域，形成一对扩展层EX，在半导体层SL与外延层EP的层叠部，在扩展层EX的外侧(远离沟道的一侧)，形成一对扩散层SD。
扩展层EX与沟道相邻接，扩散层SD与沟道间隔开了扩展层EX的量，并且被形成于与扩展层EX相接的位置。
在扩散层SD的上部(表层部)，形成作为金属与扩散层SD的反应层(化合物层)的金属硅化物层MS。金属硅化物层MS是例如硅化钴层、硅化镍层或者硅化镍铂层等。另外，在栅极电极GE由多晶硅膜构成的情况下，在栅极电极GE的上部也形成金属硅化物层MS。
在SOI基板的主表面上，以覆盖栅极电极GE、偏移隔离部OF、边墙SW以及金属硅化物层MS等的方式，形成层间绝缘膜IL。在层间绝缘膜IL中形成接触孔，在该接触孔的内部形成接触插塞，但在这里省略它们的图示。另外，在层间绝缘膜IL上形成布线，但在这里省略其图示。
接下来，使用上述的图1以及图2(a)和(b)，来说明本实施方式的第一完全耗尽型SOI晶体管的扩展层的结构。图2(a)是放大地示出具有最小宽度的偏移隔离部的第一完全耗尽型SOI晶体管的一部分的概略剖视图，图2(b)是放大地示出具有最大宽度的偏移隔离部的第一完全耗尽型SOI晶体管的一部分的概略剖视图。
如上述的图1所示，在完全耗尽型SOI晶体管的栅极电极GE的侧壁，形成偏移隔离部OF，在该偏移隔离部OF的下方的半导体层SL中，在隔着沟道相互间隔开的区域，形成源极漏极用的一对扩展层EX。
但是，如上所述，在完全耗尽型SOI晶体管中，如果扩展层EX进入到栅极电极GE的下方的沟道内，则栅极电极GE与扩展层EX的重叠(栅极重叠)变大，从而担心由短沟道效应、漏电流(栅极漏电流以及GIDL)的增加、寄生电容的增加所导致的开关速度的降低等。因此，在本实施方式中，通过使栅极电极GE与扩展层EX的重叠(栅极重叠)适当化，来解决这些课题。以下，详细说明用于解决这些课题的手段。
当在栅极电极GE的侧壁形成偏移隔离部OF之后，将杂质离子注入到半导体层SL，从而形成扩展层EX。因此，以满足下述条件(1)、条件(2)以及条件(3)的方式设定偏移隔离部OF的宽度，从而在将杂质离子注入到半导体层SL时，使得杂质不从栅极电极GE的端部下方进入到沟道内。
条件(1)：扩展层EX在从半导体层SL的上表面到下表面(半导体层SL与绝缘膜BX的界面)的范围内分布。
条件(2)：扩展层EX分布直到栅极电极GE的端部下方的半导体层SL。
条件(3)：扩展层EX不超出绝缘膜BX而分布向半导体基板SB。
如图2(a)所示，根据条件(1)以及条件(2)，偏移隔离部OF的最小宽度根据半导体层SL的厚度Tsi来决定。另外，如图2(b)所示，根据条件(3)，偏移隔离部OF的最大宽度根据半导体层SL的厚度Tsi与绝缘膜BX的厚度Tbox的合计厚度来决定。因此，偏移隔离部OF的宽度Losw被设定为：
Tsi≤Losw≤Tsi+Tbox。
例如如果半导体层SL的厚度为12nm，绝缘膜BX的厚度为10nm，则扩展层EX的宽度Losw在12～22nm的范围内设定即可。
由此，在完全耗尽型SOI晶体管中，能够抑制栅极电极GE与扩展层EX的重叠(栅极重叠)，所以能够实现短沟道效应的降低、漏电流(栅极漏电流以及GIDL)的降低、寄生电容的降低。因此，能够提高具有完全耗尽型SOI晶体管的半导体装置的可靠性以及性能。
<第二完全耗尽型SOI晶体管的构造>
使用图3(a)以及(b)，来说明本实施方式的第二完全耗尽型SOI晶体管的扩展层的结构。图3(a)是放大地示出第二完全耗尽型n沟道SOI晶体管的一部分的概略剖视图，图3(b)是放大地示出第二完全耗尽型p沟道SOI晶体管的一部分的概略剖视图。
在完全耗尽型n沟道SOI晶体管中，将n型杂质例如As(砷)或者P(磷)离子注入到半导体层而形成n型扩展层，在完全耗尽型p沟道SOI晶体管中，将p型杂质例如B(硼)或者BF2(氟化硼)离子注入到半导体层而形成p型扩展层。
但是，这些杂质在Si(硅)中的扩散系数相互不同，例如B(硼)的扩散系数比As(砷)的扩散系数大。因此，如果将偏移隔离部的宽度设为相同而将B(硼)与As(砷)离子注入到半导体层，则即使使As(砷)分布直到栅极电极的端部下方并且不进入到沟道内，B(硼)也有可能进入到沟道内。另外，如果使B(硼)分布直到栅极电极的端部下方并且不进入到沟道内，则As(砷)有可能不分布直到栅极电极的端部下方。
因此，在将完全耗尽型n沟道SOI晶体管与完全耗尽型p沟道SOI晶体管形成于相同的SOI基板时，在各自的栅极电极的侧壁形成宽度相互不同的偏移隔离部，来对n型杂质或者p型杂质进行离子注入。
如图3(a)所示，在完全耗尽型n沟道SOI晶体管中，在栅极电极GE的侧壁形成一层偏移隔离部OFa之后，将n型杂质例如As(砷)离子注入到半导体层SL。偏移隔离部OFa的宽度Losw1被设定为：
Tsi≤Losw1≤Tsi+Tbox。
另外，如图3(b)所示，在完全耗尽型p沟道SOI晶体管中，在栅极电极GE的侧壁形成多层、例如两层偏移隔离部OFa、OFb之后，将p型杂质例如B(硼)离子注入到半导体层SL。偏移隔离部OFa、OFb的宽度Losw2被设定为：
Tsi≤Losw2≤Tsi+Tbox
Losw1<Losw2。
即，分开使用在完全耗尽型n沟道SOI晶体管的栅极电极GE的侧壁形成的偏移隔离部的宽度以及在完全耗尽型p沟道SOI晶体管的栅极电极GE的侧壁形成的偏移隔离部的宽度。由此，在完全耗尽型n沟道SOI晶体管以及完全耗尽型p沟道SOI晶体管中，能够分别进行栅极电极GE与扩展层EX的重叠(栅极重叠)的适当化。
<第三完全耗尽型SOI晶体管的构造>
使用图4(a)以及(b)来说明本实施方式的第三完全耗尽型SOI晶体管的扩展层的构造。图4(a)是放大地示出第三完全耗尽型n沟道SOI晶体管的一部分的概略剖视图，图4(b)是放大地示出第三完全耗尽型p沟道SOI晶体管的一部分的概略剖视图。
在半导体装置中，在相同的半导体基板上，有时形成完全耗尽型SOI晶体管与体晶体管。在这种情况下，为了使各自的动作特性最优化，完全耗尽型SOI晶体管的扩展层和体晶体管的扩展层通过相互不同的制造工序来制造。因此，在形成体晶体管的扩展层时在体晶体管的栅极电极的侧壁形成的偏移隔离部有时形成于完全耗尽型SOI晶体管的栅极电极的侧壁。
因此，在将完全耗尽型SOI晶体管与体晶体管形成在相同的半导体基板上时，需要还考虑在体晶体管的栅极电极的侧壁形成的偏移隔离部的宽度，来设定在完全耗尽型SOI晶体管的栅极电极的侧壁形成的偏移隔离部的宽度。
如图4(a)所示，在完全耗尽型n沟道SOI晶体管中，在栅极电极GE的侧壁形成体晶体管用的偏移隔离部OFc、OFd与完全耗尽型n沟道SOI晶体管用的偏移隔离部OFa之后，对n型杂质例如As(砷)进行离子注入。偏移隔离部OFa、OFc、OFd的宽度Losw3被设定为：
Tsi≤Losw3≤Tsi+Tbox。
另外，如图4(b)所示，在完全耗尽型p沟道SOI晶体管中，在栅极电极GE的侧壁形成体晶体管用的偏移隔离部OFc、OFd与完全耗尽型p沟道SOI晶体管用的偏移隔离部OFa、OFb之后，对p型杂质例如B(硼)进行离子注入。偏移隔离部OFa、OFb、OFc、OFd的宽度Losw4被设定为：
Tsi≤Losw4≤Tsi+Tbox
Losw3<Losw4。
即，在体晶体管用的偏移隔离部形成于完全耗尽型SOI晶体管的栅极电极GE的侧壁的情况下，考虑体晶体管用的偏移隔离部的宽度，来设定完全耗尽型SOI晶体管用的偏移隔离部的宽度。由此，即使体晶体管用的偏移隔离部形成于完全耗尽型SOI晶体管的栅极电极GE的侧壁，也能够进行栅极电极GE与扩展层EX的重叠(栅极重叠)的适当化。
此外，在上述完全耗尽型n沟道SOI晶体管中，在栅极电极GE的侧壁形成三层偏移隔离部OFa、OFc、OFd，在上述完全耗尽型p沟道SOI晶体管中，在栅极电极GE的侧壁形成四层偏移隔离部OFa、OFb、OFc、OFd，但偏移隔离部的层数不限定于此。
<半导体装置的制造方法>
使用图5～图27，按工序顺序说明本实施方式的半导体装置(完全耗尽型SOI晶体管以及体晶体管)的制造方法的一例。图5～图27是本实施方式的半导体装置的制造工序中的主要部分剖视图。在这里，例示使用上述图4(a)以及(b)来说明了的第三完全耗尽型SOI晶体管的制造方法。
在本实施方式中，将形成SOI晶体管(n沟道SOI晶体管或者p沟道SOI晶体管)的区域称为SOI区域1A，将形成体晶体管(n沟道SOI晶体管或者p沟道SOI晶体管)的区域称为体区域1B。在SOI区域1A中，SOI晶体管形成于由半导体基板、半导体基板上的绝缘膜以及绝缘膜上的半导体层构成的SOI基板的主表面，在体区域1B中，体晶体管形成于半导体基板的主表面。在以下的说明中，在图的左侧示出SOI区域1A，图的右侧示出体区域1B。
如图5所示，准备在上方层叠有绝缘膜BX以及半导体层SL的半导体基板SB。半导体基板SB是由单晶Si(硅)构成的支撑基板，半导体基板SB上的绝缘膜BX由氧化硅构成，绝缘膜BX上的半导体层SL由具有1～10Ωcm左右的电阻的单晶硅构成。绝缘膜BX的厚度是例如10～20nm左右，半导体层SL的厚度是例如10～20nm左右。
SOI基板能够通过例如SIMOX(SiliconImplantedOxide，注硅氧化物)法或者贴合法来形成。在SIMOX法中，在由Si(硅)构成的半导体基板的主表面以高的能量对O2(氧)进行离子注入，在其后的热处理中，使Si(硅)与O2(氧)结合，在相比半导体基板的表面稍微更深的位置形成嵌入氧化膜(BOX膜)，从而形成SOI基板。另外，在贴合法中，通过施加高热以及压力来粘结并贴合了在表面形成氧化膜(BOX膜)的由Si(硅)构成的半导体基板、与另一张由Si(硅)构成的半导体基板之后，研磨单侧的半导体基板而使其薄膜化，从而形成SOI基板。
接下来，如图6所示，在半导体基板SB上形成具有STI(ShallowTrenchIsolation，浅沟槽隔离)构造的由绝缘膜构成的元件分离部STI。
在形成元件分离部STI的工序中，首先，在半导体层SL上形成由氮化硅构成的硬掩模图案，将该硬掩模图案作为掩模进行干法蚀刻，从而形成从半导体层SL的上表面到达半导体基板SB的中途深度的多个槽。对半导体层SL、绝缘膜BX以及半导体基板SB进行开口而形成多个槽。接着，在多个槽的内侧形成衬垫氧化膜之后，在包含多个槽的内部的半导体层SL上，通过例如CVD(ChemicalVaporDeposition，化学气相沉积)法形成例如由氧化硅构成的绝缘膜。接着，通过例如CMP(ChemicalMechanicalPolishing，化学机械抛光)法研磨该绝缘膜的上表面，在多个槽的内部残留绝缘膜。其后，去除硬掩模图案。由此，形成元件分离部STI。
元件分离部STI是使SB上的多个活性区域彼此分离的惰性区域。即，活性区域的俯视时的形状通过被元件分离部STI包围来规定。另外，形成多个元件分离部STI，以使得SOI区域1A与体区域1B之间分离，在SOI区域1A以及体区域1B的各区域中，形成多个元件分离部STI，以使得相邻的元件形成区域之间分离。
接下来，如图7所示，通过例如热氧化法，在半导体层SL的上表面形成例如由氧化硅构成的绝缘膜OX。此外，也可以通过残留上述的由氮化硅构成的硬掩模图案的一部分来形成绝缘膜OX。
接着，通过在形成n沟道SOI晶体管的SOI区域1A，隔着绝缘膜OX、半导体层SL以及绝缘膜BX地对杂质进行离子注入，从而在半导体基板SB的所期望的区域选择性形成地p型阱PW1以及阈值电压控制扩散区域E1。同样地，通过在形成p沟道SOI晶体管的SOI区域1A，隔着绝缘膜OX、半导体层SL以及绝缘膜BX地对杂质进行离子注入，从而在半导体基板SB的所期望的区域选择性地形成n型阱NW1以及阈值电压控制扩散区域E2。
接着，通过在形成n沟道体晶体管的体区域1B，隔着绝缘膜OX、半导体层SL以及绝缘膜BX地对杂质进行离子注入，从而在半导体基板SB的所期望的区域选择性地形成p型阱PW2以及阈值电压控制扩散区域E3。同样地，通过在p沟道体晶体管形成的体区域1B，隔着绝缘膜OX、半导体层SL以及绝缘膜BX地对杂质进行离子注入，从而在半导体基板SB的所期望的区域选择性地形成n型阱NW2以及阈值电压控制扩散区域E4。
接下来，如图8所示，例如通过光刻技术，在SOI区域1A形成光致抗蚀剂图案RP1。具体地说，在SOI基板上涂覆光致抗蚀剂膜，形成使体区域1B开口那样的光致抗蚀剂图案RP1。此时，以架到SOI区域1A与体区域1B的边界的元件分离部STI上的方式形成光致抗蚀剂图案RP1。
接下来，如图9所示，例如通过氢氟酸清洗来去除体区域1B的绝缘膜OX。此时，还削去体区域1B的元件分离部STI的上部的一部分，所以在体区域1B中，能够调整半导体基板SB与元件分离部STI的高低差，并且能够使在光致抗蚀剂图案RP1的边界部产生的STI上的高低差变得平坦。
接着，在例如通过干法蚀刻法，将绝缘膜BX作为阻止部来选择性地去除体区域1B的半导体层SL之后，去除光致抗蚀剂图案RP1。其后，如果需要，也可以使用在例如通过氢氟酸清洗来去除体区域1B的绝缘膜BX之后，例如通过热氧化法在半导体基板SB的表面形成例如10nm左右的热氧化膜而去除该形成的热氧化膜的牺牲氧化法。由此，能够通过去除了半导体层SL的干法蚀刻，去除被导入到半导体基板SB的损伤层。
在经过以上的工序而形成的SOI区域1A以及体区域1B中，SOI区域1A的半导体层SL表面与体区域1B的半导体基板SB的表面的高低差小到20nm左右。这使得在成为后面的栅极电极的多晶硅膜的沉积以及加工中，能够在同一工序中形成SOI晶体管与体晶体管，对于高低差部的加工残留或者栅极电极的断路的防止等来说是有效的。
接下来，如图10所示，在SOI区域1A形成SOI晶体管的栅极绝缘膜F1，并且在体区域1B形成体晶体管的栅极绝缘膜F2。栅极绝缘膜F1的厚度为例如2～3nm左右，栅极绝缘膜F2的厚度为例如7～8nm左右。其后，例如通过CVD法，在栅极绝缘膜F1、F2上依次层叠多晶硅膜G1以及氮化硅膜D1。多晶硅膜G1的厚度为例如40nm左右，氮化硅膜D1的厚度为例如30nm左右。此外，在本实施方式中使用的剖视图中，为了容易理解图，并未准确地示出各膜各自的膜厚的大小关系。
具体地说，如下所述地形成SOI晶体管的栅极绝缘膜F1以及体晶体管的栅极绝缘膜F2。首先，例如通过氢氟酸清洗，去除在体区域1B的表面暴露了的绝缘膜BX，使体区域1B的半导体基板SB的表面暴露。接着，例如通过热氧化法，在体区域1B的半导体基板SB上，形成例如7.5nm左右的厚度的热氧化膜。
此时，SOI区域1A也同样地去除在表面暴露了的绝缘膜OX，在半导体层SL上，形成例如7.5nm左右的厚度的热氧化膜。在例如通过光刻技术以及氢氟酸清洗来将其选择性地去除了之后，进行清洗，以去除蚀刻残渣以及蚀刻液等。其后，例如通过热氧化法，在SOI区域1A的半导体层SL上，形成例如2nm左右的厚度的热氧化膜。
通过NO气体，使这些7.5nm左右的厚度的热氧化膜以及2nm左右的厚度的热氧化膜的表面氮化，从而在主表面层叠形成0.2nm左右的氮化膜，将在SOI区域1A的半导体层SL上形成的绝缘膜(氮化膜/热氧化膜)设为栅极绝缘膜F1，将在体区域1B的半导体基板SB上形成的绝缘膜(氮化膜/热氧化膜)设为栅极绝缘膜F2。
通过这样，与SOI晶体管的栅极绝缘膜F1相比，能够将体晶体管的栅极绝缘膜F2形成得更厚。由此，能够提高体晶体管的耐压，能够进行高电压动作。
接下来，如图11所示，例如通过光刻技术以及各向异性干法蚀刻法，对氮化硅膜D1以及多晶硅膜G1进行加工，在SOI区域1A形成SOI晶体管的由氮化硅膜D1构成的栅极保护膜GD以及由多晶硅膜G1构成的栅极电极GE。同时，在体区域1B形成体晶体管的由氮化硅膜D1构成的栅极保护膜GD以及由多晶硅膜G1构成的栅极电极GE。在本实施方式中，如上所述，SOI区域1A的半导体层SL表面与体区域1B的半导体基板SB的表面的高低差低到20nm左右，所以在光刻时，处于焦点深度的容许范围内，能够同时形成SOI晶体管的栅极保护膜GD和栅极电极GE以及体晶体管的栅极保护膜GD和栅极电极GE。
接下来，如图12所示，在例如通过CVD法沉积了例如10nm左右的厚度的氮化硅膜之后，例如通过各向异性干法蚀刻法来选择性地加工该氮化硅膜。由此，在SOI晶体管的栅极电极GE和栅极保护膜GD的侧壁以及体晶体管的栅极电极GE和栅极保护膜GD的侧壁，形成由氮化硅构成的偏移隔离部OF1。
接下来，如图13所示，例如通过光刻技术，在SOI区域1A以及体区域1B的形成p沟道体晶体管的区域中，形成光致抗蚀剂图案RP2。接着，将光致抗蚀剂图案RP2作为掩模，在体区域1B的形成n沟道体晶体管的区域，对p型杂质例如BF2(氟化硼)离子进行离子注入，接着，对n型杂质例如As(砷)离子进行离子注入。由此，自匹配地形成n沟道体晶体管的n型扩展层EBn以及在n型扩展层EBn的沟道侧的p型晕区域(Haloarea)HAp。在n沟道体晶体管中，通过设置p型晕区域HAp，能够抑制n型扩展层EBn向沟道方向的扩散。
其后，去除光致抗蚀剂图案RP2。
接下来，如图14所示，在例如通过CVD法沉积了例如10nm左右的厚度的氧化硅膜之后，例如通过各向异性干法蚀刻法来选择性地加工该氧化硅膜。由此，在SOI晶体管的栅极电极GE和栅极保护膜GD的侧壁以及体晶体管的栅极电极GE和栅极保护膜GD的侧壁，隔着偏移边墙OF1而形成由氧化硅构成的偏移隔离部OF2。
接下来，例如通过光刻技术，在SOI区域1A以及体区域1B的形成n沟道体晶体管的区域，形成光致抗蚀剂图案RP3。接着，将光致抗蚀剂图案RP3作为掩模，在体区域1B的形成p沟道体晶体管的区域对n型杂质例如As(砷)离子进行离子注入，接着，对p型杂质例如BF2(氟化硼)离子进行离子注入。由此，自匹配地形成p沟道体晶体管的p型扩展层EBp以及在p型扩展层EBp的沟道侧的n型晕区域HAn。在p沟道体晶体管中，通过设置n型晕区域HAn，能够抑制p型扩展层EBp向沟道方向的扩散。
其后，去除光致抗蚀剂图案RP3。
接下来，如图15所示，例如通过CVD法沉积了例如40nm左右的厚度的氮化硅膜之后，例如通过各向异性干法蚀刻法来选择性地加工该氮化硅膜。由此，在SOI晶体管的栅极电极GE和栅极保护膜GD的侧壁以及体晶体管的栅极电极GE和栅极保护膜GD的侧壁，隔着偏移边墙OF1、OF2而形成由氮化硅构成的边墙SW1。其后，去除体晶体管的边墙SW1，在SOI晶体管的栅极电极GE和栅极保护膜GD的侧壁残留偏移隔离部OF1、OF2以及边墙SW1。
接下来，如图16所示，在用防护膜PB覆盖体区域1B之后，例如通过选择外延生长法，在SOI区域1A的暴露了的半导体层SL上，选择性地形成由Si(硅)或者SiGe(硅锗)构成的堆叠单晶层，即外延层EP。其后，去除防护膜PB。
使用例如批处理式的纵向外延生长装置，在作为反应室的炉内对配置了多个半导体基板的舟皿(boat)进行外延生长处理，来形成外延层EP。此时，在炉内，作为成膜气体供给例如SiH4(硅烷)气体，并且作为蚀刻气体供给含氯原子的气体，从而进行外延生长处理。作为蚀刻气体的含氯原子的气体能够使用例如HCl(盐酸)气体或者Cl(氯)气等。
接下来，如图17所示，例如通过利用热磷酸的清洗，选择性地去除SOI晶体管的由氮化硅构成的栅极保护膜GD和边墙SW1以及体晶体管的由氮化硅构成的栅极保护膜GD。此时，存在SOI晶体管的由氧化硅构成的偏移隔离部OF2以及体晶体管的由氧化硅构成的偏移隔离部OF2的厚度也变薄的情况。另外，在SOI区域1A中，在栅极电极GE与外延层EP之间，半导体层SL暴露。
接下来，如图18所示，在例如通过CVD法沉积了例如10nm左右的厚度的氮化硅膜之后，例如通过各向异性干法蚀刻法来选择性地加工该氮化硅膜。由此，在SOI晶体管的栅极电极GE的侧壁以及体晶体管的栅极电极GE的侧壁，隔着偏移隔离部OF1、OF2而形成由氮化硅构成的偏移隔离部OF3。
在这里，如使用上述图4来说明了的那样，在n沟道SOI晶体管中，在栅极电极GE的侧壁形成的三层偏移隔离部OF1、OF2、OF3的合计宽度Lo1被设定为半导体层SL的厚度以上且半导体层SL与绝缘膜BX的合计厚度以下。优选的是，上述宽度Lo1被设定为与半导体层SL的厚度相同的值。
接下来，如图19所示，例如通过光刻技术，在SOI区域1A的形成p沟道SOI晶体管的区域以及体区域1B中，形成光致抗蚀剂图案RP4。接着，将光致抗蚀剂图案RP4作为掩模，在形成n沟道SOI晶体管的SOI区域1A中，对n型杂质例如As(砷)离子进行离子注入。由此，在n沟道SOI晶体管中，在将n型杂质离子注入到外延层EP的同时，将n型杂质离子注入到栅极电极GE的两侧的暴露了的半导体层SL、或者在栅极电极GE的两侧暴露了的半导体层SL和绝缘膜BX中，形成n型扩展层EAn。
调整形成于栅极电极GE的侧壁的三层偏移隔离部OF1、OF2、OF3的合计宽度Lo1以及n型杂质的离子注入条件(加速能量以及注入量)，来形成n型扩展层EAn。由此，在n沟道SOI晶体管中，能够进行栅极电极GE与n型扩展层EAn的重叠(栅极重叠)的适当化。
其后，去除光致抗蚀剂图案RP4。
接下来，如图20所示，在例如通过CVD法沉积了例如10nm左右的厚度的氧化硅膜之后，例如通过各向异性干法蚀刻法来选择性地加工该氧化硅膜。由此，在SOI区域1A的栅极电极GE的侧壁以及体区域1B的栅极电极GE的侧壁，隔着偏移隔离部OF1、OF2、OF3而形成由氧化硅构成的偏移隔离部OF4。
在这里，如使用上述图4来说明了的那样，在p沟道SOI晶体管中，在栅极电极GE的侧壁形成的四层偏移隔离部OF1、OF2、OF3、OF4的合计宽度Lo2被设定为半导体层SL的厚度以上且半导体层SL与绝缘膜BX的合计厚度以下。优选的是，上述宽度Lo2被设定为和半导体层SL与绝缘膜BX的合计厚度相同的值。
接下来，如图21所示，例如通过光刻技术，在SOI区域1A的形成n沟道SOI晶体管的区域以及体区域1B中，形成光致抗蚀剂图案RP5。接着，将光致抗蚀剂图案RP5作为掩模，在形成p沟道SOI晶体管的SOI区域1A中，对p型杂质例如B(硼)离子进行离子注入。由此，在p沟道SOI晶体管中，在将p型杂质离子注入到外延层EP的同时，将p型杂质离子注入到栅极电极GE的两侧的暴露了的半导体层SL、或者在栅极电极GE的两侧暴露了的半导体层SL和绝缘膜BX中，形成p型延伸EAp。
调整在栅极电极GE的侧壁形成的四层偏移隔离部OF1、OF2、OF3、OF4的合计宽度Lo2以及p型杂质的离子注入条件(加速能量以及注入量)，来形成p型扩展层EAp。由此，在p沟道SOI晶体管中，能够进行栅极电极GE与p型扩展层EAp的重叠(栅极重叠)的适当化。
其后，去除光致抗蚀剂图案RP5。
接下来，如图22所示，在例如通过CVD法沉积了例如40nm左右的厚度的氮化硅膜之后，例如通过各向异性干法蚀刻法来选择性地加工该氮化硅膜。由此，在SOI晶体管的栅极电极GE的侧壁以及体晶体管的栅极电极GE的侧壁，隔着偏移隔离部OF1、OF2、OF3、OF4而形成由氮化硅构成的边墙SW2。此时，在SOI区域1A中，由边墙SW2覆盖在栅极电极GE与外延层EP之间暴露了的半导体层SL上。
接下来，如图23所示，例如通过光刻技术，在SOI区域1A的形成p沟道SOI晶体管的区域以及体区域1B的形成p沟道体晶体管的区域，形成光致抗蚀剂图案RP6。接着，将光致抗蚀剂图案RP6作为掩模，在SOI区域1A的形成n沟道SOI晶体管的区域以及体区域1B的形成n沟道体晶体管的区域中，对n型杂质例如As(砷)离子进行离子注入。由此，在n沟道SOI晶体管中，在外延层EP以及外延层EP下方的半导体层SL中形成n型扩散层SDn1，在n沟道体晶体管中，在栅极电极GE的两侧的半导体基板SB，形成n型扩散层SDn2。
其后，去除光致抗蚀剂图案RP6。
接下来，如图24所示，例如通过光刻技术，在SOI区域1A的形成n沟道SOI晶体管的区域以及体区域1B的形成n沟道体晶体管的区域，形成光致抗蚀剂图案RP7。接着，将光致抗蚀剂图案RP7作为掩模，在SOI区域1A的形成p沟道SOI晶体管的区域以及体区域1B的形成p沟道体晶体管的区域，对p型杂质例如BF2(氟化硼)离子进行离子注入。由此，在p沟道SOI晶体管中，在外延层EP以及外延层EP下方的半导体层SL中形成n型扩散层SDp1，在p沟道体晶体管中，在栅极电极GE的两侧的半导体基板SB，形成p型扩散层SDp2。
其后，去除光致抗蚀剂图案RP7。
接着，例如通过RTA(RapidThermalAnneal，快速热退火)法使注入了的杂质活化并且热扩散。作为RTA的条件，例如能够例示出氮气气氛、1050℃。
此时，n沟道SOI晶体管的n型扩展层EAn也进行热扩散，但预先考虑由热扩散产生的扩散距离等，来设定在栅极电极GE的侧壁形成的偏移隔离部OF1、OF2、OF3的厚度以及n型杂质的离子注入条件等。由此，能够防止n型扩展层EAn从栅极电极GE的端部下方朝向沟道方向的扩散以及n型扩展层EAn超出了绝缘膜BX的朝向半导体基板SB的扩散。
同样地，p沟道SOI晶体管的p型扩展层EAp也进行热扩散，但预先考虑由热扩散产生的扩散距离等，来设定在栅极电极GE的侧壁形成的偏移隔离部OF1、OF2、OF3、OF4的厚度以及p型杂质的离子注入条件等。由此，能够防止p型扩展层EAp从栅极电极GE的端部下方朝向沟道方向的扩散以及p型扩展层EAp超出了绝缘膜BX的朝向半导体基板SB的扩散。
接下来，如图25所示，在例如通过溅射法沉积了金属膜、例如20nm左右的厚度的Ni(镍)膜之后，通过例如320℃左右的热处理，使Ni(镍)与Si(硅)反应，形成硅化镍层NS。接着，在例如通过HCl(盐酸)与H2O2(过氧化氢溶液)的混合水溶液来去除未反应的Ni(镍)之后，通过例如550℃左右的热处理来控制硅化镍层NS的相位。
由此，在SOI区域1A中，在SOI晶体管的栅极电极GE以及外延层EP各自的上部形成硅化镍层NS，在体区域1B中，在体晶体管的栅极电极GE、n型扩散层SDn2以及p型扩散层SDp2各自的上部形成硅化镍层NS。
通过上述工序，在SOI区域1A中，形成具有源极漏极(n型扩展层EAn与n型扩散层SDn1)与栅极电极GE的n沟道SOI晶体管以及具有源极漏极(p型扩展层EAp与p型扩散层SDp1)与栅极电极GE的p沟道SOI晶体管。另外，在体区域1B中，形成具有源极漏极(n型扩展层EBn与n型扩散层SDn2)与栅极电极GE的n沟道体晶体管以及具有源极漏极(p型扩展层EBp与p型扩散层SDp2)与栅极电极GE的p沟道体晶体管。
接下来，如图26所示，依次沉积被用作由氮化硅膜构成的蚀刻阻止膜的绝缘膜以及由氧化硅膜构成的绝缘膜，形成层间绝缘膜IL，之后，使层间绝缘膜IL的表面平坦化。
接下来，如图27所示，使层间绝缘膜IL贯通，形成到达在SOI晶体管以及体晶体管的栅极电极GE的上部分别形成的硅化镍层NS的接触孔(省略图示)以及到达在SOI晶体管以及体晶体管的源极漏极的上部分别形成的硅化镍层NS的接触孔CNT。
接着，在包含接触孔CNT的内部的层间绝缘膜IL上，例如通过溅射法，依次形成例如包括Ti(钛)的阻挡导体膜与W(钨)膜。其后，例如通过CMP法，去除层间绝缘膜IL上的阻挡导体膜以及W(钨)膜，在接触孔CNT的内部形成将W(钨)膜设为主导体膜的柱状的接触插塞CP。
其后，形成与接触插塞CP电连接的布线层，进而形成上层的布线等，从而大致完成本实施方式的半导体装置。
这样，根据本实施方式，在完全耗尽型SOI晶体管中，能够抑制栅极电极与扩展层的重叠(栅极重叠)，所以能够实现短沟道效应的降低、漏电流(栅极漏电流以及GIDL)的降低、寄生电容的降低。因此，能够提高具有完全耗尽型SOI晶体管的半导体装置的可靠性以及性能。
以上，根据实施方式，具体说明了通过本发明者完成的发明，但本发明并非限定于上述实施方式，在不脱离其主旨的范围内能够进行各种变更，这自不待言。
标号说明
BX绝缘膜(嵌入绝缘膜、嵌入氧化膜、BOX膜)
CNT接触孔
CP接触插塞
D1氮化硅膜
E1～E4阈值电压控制扩散区域
EAnn型扩展层
EApp型扩展层
EBnn型扩展层
EBpp型扩展层
EP外延层
EX扩展层
F1、F2栅极绝缘膜
G1多晶硅膜
GD栅极保护膜
GE栅极电极
GI栅极绝缘膜
Hann型晕区域
Happ型晕区域
IL层间绝缘膜
MS金属硅化物层
NS硅化镍层
NW1、NW2n型阱
OF、OF1～OF4、OFa、OFb、OFc、OFd偏移隔离部
OX绝缘膜
PB防护膜
RP1～RP7光致抗蚀剂图案
PW1、PW2p型阱
SB半导体基板
SD扩散层
SDn1、SDn2n型扩散层
SDp1，SDp2p型扩散层
SL半导体层(SOI层、硅层)
STI元件分离部
SW、SW1、SW2边墙

Claims (17)

1.一种半导体装置，在第一区域具备第一场效应晶体管，
所述半导体装置的特征在于，
所述第一场效应晶体管具有：
SOI基板，具有半导体基板、所述半导体基板上的绝缘膜以及所述绝缘膜上的半导体层；
第一栅极电极，在所述半导体层上隔着第一栅极绝缘膜形成；
第一偏移隔离部，在所述第一栅极电极的侧壁形成；
第一导电类型的第一扩展层，在所述第一栅极电极的两侧的所述半导体层形成；以及
源极漏极用的所述第一导电类型的第一外延层，在未形成所述第一栅极电极以及所述第一偏移隔离部的所述半导体层上形成，
所述第一偏移隔离部的宽度为所述半导体层的厚度以上且所述半导体层与所述绝缘膜的合计厚度以下。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第一扩展层未超出所述绝缘膜与所述半导体基板的界面而分布到所述半导体基板。
3.根据权利要求1所述的半导体装置，其特征在于，
在与所述第一区域不同的第二区域具备第二场效应晶体管，
所述第二场效应晶体管具有：
所述SOI基板；
第二栅极电极，在所述半导体层上隔着第二栅极绝缘膜形成；
第二偏移隔离部，在所述第二栅极电极的侧壁形成；
与所述第一导电类型不同的第二导电类型的第二扩展层，在所述第二栅极电极的两侧的所述半导体层形成；以及
源极漏极用的所述第二导电类型的第二外延层，在未形成所述第二栅极电极以及所述第二偏移隔离部的所述半导体层上形成，
所述第二偏移隔离部的宽度为所述半导体层的厚度以上且所述半导体层与所述绝缘膜的合计厚度以下，
所述第二扩展层的从所述半导体层的上表面起的深度比所述第一扩展层的从所述半导体层的上表面起的深度更深。
4.根据权利要求3所述的半导体装置，其特征在于，
所述第一导电类型为n型，所述第二导电类型为p型。
5.根据权利要求3所述的半导体装置，其特征在于，
所述第二扩展层未超出所述绝缘膜与所述半导体基板的界面而分布到所述半导体基板。
6.根据权利要求1所述的半导体装置，其特征在于，
在与所述第一区域不同的第三区域具备第三场效应晶体管，
所述第三场效应晶体管具有：
所述半导体基板；
第三栅极电极，在所述半导体基板上隔着第三栅极绝缘膜形成；
第三偏移隔离部，在所述第三栅极电极的侧壁形成；以及
所述第一导电类型的第三扩展层，在所述第三栅极电极的两侧的所述半导体基板形成，
在所述第三扩展层的沟道侧形成有与所述第一导电类型不同的第二导电类型的半导体区域。
7.根据权利要求6所述的半导体装置，其特征在于，
所述第三栅极绝缘膜的厚度比所述第一栅极绝缘膜的厚度更厚。
8.一种形成场效应晶体管的半导体装置的制造方法，其特征在于，具有以下工序：
(a)工序，准备具有半导体基板、所述半导体基板上的绝缘膜以及所述绝缘膜上的半导体层的SOI基板；
(b)工序，在所述半导体层上隔着栅极绝缘膜形成栅极电极；
(c)工序，在所述栅极电极的侧壁形成第一宽度的第一边墙；
(d)工序，在所述(c)工序之后，在未被所述栅极电极以及所述第一边墙覆盖而暴露的所述半导体层上形成外延层；
(e)工序，在所述(d)工序之后，去除所述第一边墙；
(f)工序，在所述(e)工序之后，在所述栅极电极的侧壁形成比所述第一宽度小的第二宽度的偏移隔离部；
(g)工序，在所述(f)工序之后，将杂质离子注入到未被所述栅极电极以及所述偏移隔离部覆盖的所述半导体层，在所述栅极电极的两侧的所述半导体层形成第一导电类型的扩展层；
(h)工序，在所述(g)工序之后，在所述栅极电极的侧壁形成第二边墙；以及
(i)工序，在所述(h)工序之后，在所述外延层与所述半导体层的层叠部形成所述第一导电类型的扩散层，
在所述(f)工序中，在所述栅极电极的侧壁形成的所述偏移隔离部的所述第二宽度为所述半导体层的厚度以上且所述半导体层与所述绝缘膜的合计厚度以下。
9.根据权利要求8所述的半导体装置的制造方法，其特征在于，还具有：
(j)工序，在所述(i)工序之后，在所述外延层上形成硅化物层。
10.根据权利要求8所述的半导体装置的制造方法，其特征在于，
所述半导体层的厚度为10～20nm，所述绝缘膜的厚度为10～20nm。
11.根据权利要求8所述的半导体装置的制造方法，其特征在于，
所述扩展层的杂质浓度比所述扩散层的杂质浓度更低。
12.一种半导体装置的制造方法，在第一区域形成第一场效应晶体管，在与所述第一区域不同的第二区域形成第二场效应晶体管，所述半导体装置的制造方法的特征在于，具有以下工序：
(a)工序，准备具有半导体基板、所述半导体基板上的绝缘膜以及所述绝缘膜上的半导体层的SOI基板；
(b)工序，去除所述第二区域的所述绝缘膜以及所述半导体层；
(c)工序，在所述第一区域的所述半导体层上隔着第一栅极绝缘膜形成第一栅极电极，在所述第二区域的所述半导体基板上隔着第二栅极绝缘膜形成第二栅极电极；
(d)工序，在所述第一栅极电极以及所述第二栅极电极各自的侧壁形成第一偏移隔离部；
(e)工序，在所述(d)工序之后，将第一杂质离子注入到所述第二区域的未被所述第二栅极电极以及所述第一偏移隔离部覆盖的所述半导体基板，在所述第二栅极电极的两侧的所述半导体基板形成第一导电类型的第一扩展层；
(f)工序，在所述(e)工序之后，在所述第一区域的所述第一栅极电极的侧壁隔着所述第一偏移隔离部形成第一宽度的第一边墙；
(g)工序，在所述(f)工序之后，在所述第一区域的未被所述第一栅极电极、所述第一偏移隔离部以及所述第一边墙覆盖而暴露的所述半导体层上形成外延层；
(h)工序，在所述(g)工序之后，去除所述第一边墙；
(i)工序，在所述(h)工序之后，在所述第一栅极电极以及所述第二栅极电极各自的侧壁隔着所述第一偏移隔离部形成比所述第一宽度小的第二宽度的第二偏移隔离部；
(j)工序，在所述(i)工序之后，将第二杂质离子注入到所述第一区域的未被所述第一栅极电极、所述第一偏移隔离部以及所述第二偏移隔离部覆盖的所述半导体层，在所述第一栅极电极的两侧的所述半导体层形成所述第一导电类型的第二扩展层；
(k)工序，在所述(j)工序之后，在所述第一栅极电极以及所述第二栅极电极各自的侧壁隔着所述第一偏移隔离部以及所述第二偏移隔离部形成第二边墙；以及
(l)工序，在所述(k)工序之后，在所述第一区域的所述外延层与所述半导体层的层叠部形成所述第一导电类型的第一扩散层，
在所述(i)工序中，覆盖所述第一栅极电极的侧壁的所述第一偏移隔离部与所述第二偏移隔离部的合计宽度为所述半导体层的厚度以上且所述半导体层与所述绝缘膜的合计厚度以下。
13.根据权利要求12所述的半导体装置的制造方法，其特征在于，还具有：
(m)工序，在所述(l)工序之后，在所述外延层上形成硅化物层。
14.根据权利要求12所述的半导体装置的制造方法，其特征在于，
所述半导体层的厚度为10～20nm，所述绝缘膜的厚度为10～20nm。
15.根据权利要求12所述的半导体装置的制造方法，其特征在于，
所述第一栅极绝缘膜的厚度比所述第二栅极绝缘膜的厚度更薄。
16.根据权利要求12所述的半导体装置的制造方法，其特征在于，
在所述(l)工序中，在形成所述第一区域的所述第一扩散层的同时，在所述第二区域的所述第一栅极电极的两侧的所述半导体基板形成所述第一导电类型的第二扩散层。
17.根据权利要求12所述的半导体装置的制造方法，其特征在于，还具有：
(n)工序，在所述(e)工序之前或之后，将第三杂质离子注入到所述第二区域的未被所述第二栅极电极以及所述第一偏移隔离部覆盖的所述半导体基板，在所述第二栅极电极的两侧的所述半导体基板，在所述第一扩展层的沟道侧形成与所述第一导电类型不同的第二导电类型的半导体区域。
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CN108933106B (zh) * 2017-05-29 2023-03-24 瑞萨电子株式会社 制造半导体器件的方法
CN109148564A (zh) * 2017-06-16 2019-01-04 韩国科学技术研究院 场效应晶体管、生物传感器及其制造方法

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