TW201611250A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201611250A
TW201611250A TW104117022A TW104117022A TW201611250A TW 201611250 A TW201611250 A TW 201611250A TW 104117022 A TW104117022 A TW 104117022A TW 104117022 A TW104117022 A TW 104117022A TW 201611250 A TW201611250 A TW 201611250A
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Taiwan
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layer
gate electrode
semiconductor
insulating film
region
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TW104117022A
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English (en)
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Hidekazu Oda
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Renesas Electronics Corp
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    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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Abstract

本發明之課題在於提高具有完全空乏型SOI電晶體之半導體裝置之可靠性及性能。 將形成於閘極電極GE之側壁之補償間隙壁OF之寬度Losw設定為半導體層SL之厚度Tsi以上、且半導體層SL之厚度Tsi與絕緣膜BX之厚度Tbox之合計之厚度以下，且向未被閘極電極GE及補償間隙壁OF覆蓋之半導體層SL離子注入雜質。藉此，使藉由離子注入雜質而形成之延伸層EX不會自閘極電極GE之端部下進入至通道內。

Description

半導體裝置及其製造方法
本發明係關於一種半導體裝置及其製造技術，例如可較佳地利用於使用SOI(Silicon On Insulator，絕緣層上覆矽)基板之半導體裝置及其製造方法。
例如，於日本專利特開2003-100902號公報(專利文獻1)中記載有如下技術：於在低電壓nMOS區域形成nMOS電晶體之延伸層後，於閘極電極之側面形成補償間隙壁，其後，於低電壓pMOS區域形成pMOS電晶體之延伸層。
又，於日本專利特開2014-038878號公報(專利文獻2)中記載有一種半導體裝置，該半導體裝置包括：閘極電極，其係介隔閘極絕緣膜而形成於SOI基板之半導體層上；側牆間隙壁，其形成於閘極電極之側壁上；源極、汲極用半導體層，其係於半導體層上磊晶成長而成；及側牆間隙壁，其形成於源極、汲極用半導體層之側壁上。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2003-100902號公報
[專利文獻2]日本專利特開2014-038878號公報
於完全空乏型SOI電晶體中，伴隨著微細化，閘極電極與源極、 汲極之重疊(閘極重疊)變大，由此有如下顧慮：DIBL(Drain Induced Barrier Lowering，汲極引發能障降低)之劣化、閘極漏電流之增加、GIDL(Gate Induced Drain Leak，閘極誘發汲極洩漏)之增加、寄生電容之增加而導致切換速度下降等。
其他問題與新穎之特徵係根據本說明書之敍述及隨附圖式而變得明確。
根據一實施形態，於使用具有半導體基板、半導體基板上之絕緣膜、絕緣膜上之半導體層之SOI基板的半導體裝置中，將形成於完全空乏型SOI電晶體之閘極電極之側壁之補償間隙壁的寬度設定為半導體層之厚度以上、且半導體層與絕緣膜之合計之厚度以下。而且，藉由向將閘極電極及補償間隙壁作為遮罩之半導體層離子注入雜質而形成完全空乏型SOI電晶體之延伸層。
根據一實施形態，可提高具有完全空乏型SOI電晶體之半導體裝置之可靠性及性能。
1A‧‧‧SOI區域
1B‧‧‧塊狀區域
BX‧‧‧絕緣膜(嵌入絕緣膜、嵌入氧化膜、BOX膜)
CNT‧‧‧接觸孔
CP‧‧‧接觸插塞
D1‧‧‧氮化矽膜
E1‧‧‧臨界電壓控制擴散區域
E2‧‧‧臨界電壓控制擴散區域
E3‧‧‧臨界電壓控制擴散區域
E4‧‧‧臨界電壓控制擴散區域
EAn‧‧‧n型延伸層
EAp‧‧‧p型延伸層
EBn‧‧‧n型延伸層
EBp‧‧‧p型延伸層
EP‧‧‧磊晶層
EX‧‧‧延伸層
F1‧‧‧閘極絕緣膜
F2‧‧‧閘極絕緣膜
G1‧‧‧多晶矽膜
GD‧‧‧閘極保護膜
GE‧‧‧閘極電極
GI‧‧‧閘極絕緣膜
HAn‧‧‧n型環形區域
HAp‧‧‧p型環形區域
IL‧‧‧層間絕緣膜
Lo1‧‧‧寬度
Lo2‧‧‧寬度
Losw‧‧‧寬度
Losw1‧‧‧寬度
Losw2‧‧‧寬度
Losw3‧‧‧寬度
Losw4‧‧‧寬度
MS‧‧‧金屬矽化物層
NS‧‧‧矽化鎳層
NW1‧‧‧n型井
NW2‧‧‧n型井
OF‧‧‧補償間隙壁
OF1‧‧‧補償間隙壁
OF2‧‧‧補償間隙壁
OF3‧‧‧補償間隙壁
OF4‧‧‧補償間隙壁
OFa‧‧‧補償間隙壁
OFb‧‧‧補償間隙壁
OFc‧‧‧補償間隙壁
OFd‧‧‧補償間隙壁
OX‧‧‧絕緣膜
PB‧‧‧保護膜
PW1‧‧‧p型井
PW2‧‧‧p型井
RP1‧‧‧光阻圖案
RP2‧‧‧光阻圖案
RP3‧‧‧光阻圖案
RP4‧‧‧光阻圖案
RP5‧‧‧光阻圖案
RP6‧‧‧光阻圖案
RP7‧‧‧光阻圖案
SB‧‧‧半導體基板
SD‧‧‧擴散層
SDn1‧‧‧n型擴散層
SDn2‧‧‧n型擴散層
SDp1‧‧‧p型擴散層
SDp2‧‧‧p型擴散層
SL‧‧‧半導體層(SOI層、矽層)
STI‧‧‧元件分離部
SW‧‧‧側牆
SW1‧‧‧側牆
SW2‧‧‧側牆
Tbox‧‧‧厚度
Tsi‧‧‧厚度
圖1係說明本實施形態之第1完全空乏型SOI電晶體之構造之主要部分剖視圖。
圖2係說明本實施形態之第1完全空乏型SOI電晶體之延伸層之構成的概略剖視圖。(a)係將具有最小寬度之補償間隙壁之第1完全空乏型SOI電晶體之一部分放大表示之概略剖視圖，(b)係將具有最大寬度之補償間隙壁之第1完全空乏型SOI電晶體之一部分放大表示之概略剖視圖。
圖3係說明本實施形態之第2完全空乏型SOI電晶體之延伸層之構成的概略剖視圖。(a)係將第2完全空乏型n通道SOI電晶體之一部分放 大表示之概略剖視圖，(b)係將第2完全空乏型p通道SOI電晶體之一部分放大表示之概略剖視圖。
圖4係說明本實施形態之第3完全空乏型SOI電晶體之延伸層之構成的概略剖視圖。(a)係將第3完全空乏型n通道SOI電晶體之一部分放大表示之概略剖視圖，(b)係將第3完全空乏型p通道SOI電晶體之一部分放大表示之概略剖視圖。
圖5係表示本實施形態之半導體裝置之製造步驟之主要部分剖視圖。
圖6係繼圖5之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖7係繼圖6之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖8係繼圖7之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖9係繼圖8之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖10係繼圖9之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖11係繼圖10之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖12係繼圖11之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖13係繼圖12之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖14係繼圖13之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖15係繼圖14之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖16係繼圖15之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖17係繼圖16之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖18係繼圖17之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖19係繼圖18之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖20係繼圖19之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖21係繼圖20之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖22係繼圖21之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖23係繼圖22之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖24係繼圖23之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖25係繼圖24之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖26係繼圖25之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
圖27係繼圖26之後之半導體裝置之製造步驟中之與圖5相同部位之主要部分剖視圖。
於以下實施形態中，為了方便起見而於必要時分割成複數個部分或實施形態進行說明，但除了特別明示之情形以外，其等並非相互毫無關係，而處於一者係另一者之一部分或全部之變化例、詳情、補足說明等之關係。
又，於以下實施形態中，於提及要素之數等(包含個數、數值、量、範圍等)之情形時，除了特別明示之情形及原理上明確限定為特定數之情形等以外，並不限定於該特定數，亦可為特定數以上或以下。
又，於以下實施形態中，關於其構成要素(亦包含要素步驟等)，除了特別明示之情形及原理上明確地認為必須之情形等以外，當然未必為必須者。
又，於表述為「包含A」、「包括A」、「具有A」、「含有A」時，除了特別明示僅為該要素之主旨之情形等以外，當然並不排除其以外之要素。同樣地，於以下實施形態中，於提及構成要素等之形狀、位置關係等時，除了特別明示之情形及原理上明確地認為並非如此之情形等以外，設為實質上包含與該形狀等近似或類似者等。該情形對於上述數值及範圍亦同樣。
又，於以下實施形態中，將代表場效電晶體之MISFET(Metal Insulator Semiconductor Field Effect Transistor，金屬絕緣半導體場效應電晶體)簡稱為電晶體。又，於以下實施形態所使用之圖式中，亦存在為了易於觀察圖式而於平面圖中亦附註影線之情形。又，於用以說明以下實施形態之所有圖中，具有相同功能者原則上標註相同符號，且省略其重複說明。以下，基於圖式詳細地說明本實施形態。
(問題之詳細說明)
為了使本實施形態之半導體裝置被認為更明確，而對由本發明 者發現之完全空乏型SOI電晶體中所欲解決之問題進行說明。
於完全空乏型SOI電晶體中，若伴隨著微細化而源極、汲極深入至通道內，則會產生實效通道長變短、汲極電場對源極造成影響而使通道表面之電位下降之被稱為所謂DIBL之現象。
又，若源極、汲極與閘極電極之重疊(閘極重疊)變大，則於重疊部分源極與閘極電極之間及汲極與閘極電極之間之閘極漏電流將會增加。進而，若對閘極電極施加電壓，則上述重疊部分空乏化，產生衝擊離子化而使GIDL增加。
又，若於上述重疊部分源極與閘極電極之間及汲極與閘極電極之間之重疊電容增加，則完全空乏型SOI電晶體之開關速度會下降，進而半導體裝置之電路動作速度下降。
(實施形態) <第1完全空乏型SOI電晶體之構造>
使用圖1對本實施形態之第1完全空乏型SOI電晶體之構造進行說明。圖1係說明本實施形態之第1完全空乏型SOI電晶體之構造之主要部分剖視圖。
完全空乏型SOI電晶體係形成於SOI基板之主面，該SOI基板包含：半導體基板SB，其含有單晶矽；絕緣膜(嵌入絕緣膜、嵌入氧化膜、BOX(Buried Oxide，內埋氧化物)膜)BX，其形成於半導體基板SB上，且含有氧化矽；及半導體層(SOI層、矽層)SL，其形成於絕緣層BX上，且含有單晶矽。半導體基板SB係支持絕緣層BX及較其更靠上之構造的支持基板。絕緣膜BX之厚度例如為10~20nm左右，半導體層SL之厚度例如為10~20nm左右。
於半導體層SL上，介隔閘極絕緣膜GI而形成有閘極電極GE。閘極絕緣膜GI係由例如氧化矽膜或氮氧化矽膜形成。閘極絕緣膜GI之厚度例如為2~3nm左右。作為其他形態，亦可對閘極絕緣膜GI使用介 電常數較氮化矽膜高之高介電常數閘極絕緣膜(例如氧化鉿膜或氧化鋁膜等金屬氧化物膜)。
閘極電極GE係由導電膜、例如多晶矽膜(多晶矽膜、摻雜多晶矽膜)形成。作為其他形態，亦可對閘極電極GE使用金屬膜或顯示金屬傳導之金屬化合物膜。
閘極電極GE之下方之半導體層SL成為形成完全空乏型SOI電晶體之通道之區域。又，於閘極電極GE之側壁，介隔補償間隙壁OF而形成有側牆SW。補償間隙壁OF及側牆SW包含絕緣膜。
於半導體層SL中之未被閘極電極GE、補償間隙壁OF及側牆SW覆蓋之區域上，選擇性地形成有磊晶層EP。因此，於閘極電極GE之兩側(閘極長度方向之兩側)，介隔補償間隙壁OF及側牆SW而形成有磊晶層EP。
於閘極電極GE之兩側(閘極長度方向之兩側)之半導體層SL及磊晶層EP，形成有完全空乏型SOI電晶體之源極、汲極用半導體區域，該源極、汲極用半導體區域係由延伸層EX、及雜質濃度較延伸層EX高之擴散層SD構成。
即，於補償間隙壁OF及側牆SW下方之半導體層SL且隔著通道相互隔開之區域，形成有一對延伸層EX，於延伸層EX之外側(遠離通道之側)，由半導體層SL與磊晶層EP之積層部形成有一對擴散層SD。
延伸層EX鄰接於通道，擴散層SD係形成於自通道隔開延伸層EX之量且與延伸層EX相接之位置。
於擴散層SD之上部(表層部)，形成有作為金屬與擴散層SD之反應層(化合物層)之金屬矽化物層MS。金屬矽化物層MS例如為矽化鈷層、矽化鎳層或矽化鎳鉑層等。又，於閘極電極GE包含多晶矽膜之情形時，於閘極電極GE之上部亦形成有金屬矽化物層MS。
於SOI基板之主面上，以覆蓋閘極電極GE、補償間隙壁OF、側 牆SW及金屬矽化物層MS等之方式，形成有層間絕緣膜IL。於層間絕緣膜IL形成接觸孔，且於該接觸孔之內部形成有接觸插塞，此處省略其等之圖示。又，於層間絕緣膜IL上形成有配線，但此處省略其圖示。
其次，使用上述圖1以及圖2(a)及(b)對本實施形態之第1完全空乏型SOI電晶體之延伸層之構成進行說明。圖2(a)係將具有最小寬度之補償間隙壁之第1完全空乏型SOI電晶體之一部分放大表示之概略剖視圖，圖2(b)係將具有最大寬度之補償間隙壁之第1完全空乏型SOI電晶體之一部分放大表示之概略剖視圖。
如上述之圖1所示，於完全空乏型SOI電晶體之閘極電極GE之側壁形成有補償間隙壁OF，且於該補償間隙壁OF下方之半導體層SL且隔著通道相互隔開之區域，形成有源極、汲極用之一對延伸層EX。
然而，如上所述，於完全空乏型SOI電晶體中，若延伸層EX進入至閘極電極GE下方之通道內，則閘極電極GE與延伸層EX之重疊(閘極重疊)會變大，由此存在如下顧慮：短通道效應、漏電流(閘極漏電流及GIDL)之增加、寄生電容之增加而導致開關速度下降等。因此，於本實施形態中，藉由使閘極電極GE與延伸層EX之重疊(閘極重疊)適當化，而解決該等問題。以下，對用以解決該等問題之方法進行詳細說明。
延伸層EX係藉由在閘極電極GE之側壁形成補償間隙壁OF後向半導體層SL離子注入雜質而形成。因此，藉由以滿足下述條件(1)、條件(2)及條件(3)之方式設定補償間隙壁OF之寬度，而於向半導體層SL離子注入雜質時，使雜質不自閘極電極GE之端部下進入至通道內。
條件(1)：延伸層EX係自半導體層SL之上表面遍及下表面(半導體層SL與絕緣膜BX之界面)而分佈。
條件(2)：延伸層EX分佈至閘極電極GE之端部下之半導體層SL。
條件(3)：延伸層EX不超過絕緣膜BX向半導體基板SB分佈。
如圖2(a)所示，根據條件(1)及條件(2)，補償間隙壁OF之最小寬度係由半導體層SL之厚度Tsi決定。又，如圖2(b)所示，根據條件(3)，補償間隙壁OF之最大寬度係由半導體層SL之厚度Tsi與絕緣膜BX之厚度Tbox之合計厚度決定。因此，補償間隙壁OF之寬度Losw係以如下方式設定。
Tsi≦Losw≦Tsi+Tbox例如，若半導體層SL之厚度為12nm，絕緣膜BX之厚度為10nm，則延伸層EX之寬度Losw只要於12~22nm之範圍內設定即可。
藉此，於完全空乏型SOI電晶體中，可抑制閘極電極GE與延伸層EX之重疊(閘極重疊)，故而可謀求短通道效應降低、漏電流(閘極漏電流及GIDL)降低、寄生電容降低。因此，可提高具有完全空乏型SOI電晶體之半導體裝置之可靠性及性能。
<第2完全空乏型SOI電晶體之構造>
使用圖3(a)及(b)對本實施形態之第2完全空乏型SOI電晶體之延伸層之構成進行說明。圖3(a)係將第2完全空乏型n通道SOI電晶體之一部分放大表示之概略剖視圖，圖3(b)係將第2完全空乏型p通道SOI電晶體之一部分放大表示之概略剖視圖。
於完全空乏型n通道SOI電晶體中，對半導體層離子注入n型雜質、例如As(砷)或P(磷)，而形成n型延伸層，於完全空乏型p通道SOI電晶體中，對半導體層離子注入p型雜質、例如B(硼)或BF2(氟化硼)，而形成p型延伸層。
然而，該等雜質之Si(矽)中的擴散係數互不相同，例如B(硼)之擴散係數大於As(砷)之擴散係數。因此，若將補償間隙壁之寬度設為相同，且對半導體層離子注入B(硼)與As(砷)，則即便使As(砷)分佈至閘極電極之端部下且不進入至通道內，亦有B(硼)進入至通道內之虞。 又，若使B(硼)分佈至閘極電極之端部下且不進入至通道內，則有As(砷)未分佈至閘極電極之端部下之虞。
因此，於將完全空乏型n通道SOI電晶體與完全空乏型p通道SOI電晶體形成於同一SOI基板時，於各者之閘極電極之側壁形成寬度互不相同之補償間隙壁，而離子注入n型雜質或p型雜質。
如圖3(a)所示，於完全空乏型n通道SOI電晶體中，於在閘極電極GE之側壁形成1層補償間隙壁OFa後，向半導體層SL離子注入n型雜質、例如As(砷)。補償間隙壁OFa之寬度Losw1係以如下方式設定。
Tsi≦Losw1≦Tsi+Tbox
又，如圖3(b)所示，於完全空乏型p通道SOI電晶體中，於在閘極電極GE之側壁形成複數層、例如2層之補償間隙壁OFa、OFb後，向半導體層SL離子注入p型雜質、例如B(硼)。補償間隙壁OFa、OFb之寬度Losw2係以如下方式設定。
Tsi≦Losw2≦Tsi+Tbox
Losw1<Lisw2
即，分開使用形成於完全空乏型n通道SOI電晶體之閘極電極GE之側壁的補償間隙壁之寬度、與形成於完全空乏型p通道SOI電晶體之閘極電極GE之側壁的補償間隙壁之寬度。藉此，於完全空乏型n通道SOI電晶體及完全空乏型p通道SOI電晶體中，可進行各個閘極電極GE與延伸層EX之重疊(閘極重疊)之適當化。
<第3完全空乏型SOI電晶體之構造>
使用圖4(a)及(b)對本實施形態之第3完全空乏型SOI電晶體之延伸層之構造進行說明。圖4(a)係將第3完全空乏型n通道SOI電晶體之一部分放大表示之概略剖視圖，圖4(b)係將第3完全空乏型p通道SOI電晶體之一部分放大表示之概略剖視圖。
於半導體裝置中，有時於同一半導體基板上形成完全空乏型SOI 電晶體與塊狀電晶體。於該情形時，為了使各者之動作特性最佳化，完全空乏型SOI電晶體之延伸層與塊狀電晶體之延伸層係以互不相同之製造步驟製造。因此，存在如下情況：於形成塊狀電晶體之延伸層時形成於塊狀電晶體之閘極電極之側壁的補償間隙壁形成於完全空乏型SOI電晶體之閘極電極之側壁。
因此，於將完全空乏型SOI電晶體與塊狀電晶體形成於同一半導體基板上時，必須亦考慮形成於塊狀電晶體之閘極電極之側壁的補償間隙壁之寬度，而設定形成於完全空乏型SOI電晶體之閘極電極之側壁的補償間隙壁之寬度。
如圖4(a)所示，於完全空乏型n通道SOI電晶體中，於在閘極電極GE之側壁形成塊狀電晶體用之補償間隙壁OFc、OFd與完全空乏型n通道SOI電晶體用之補償間隙壁OFa後，離子注入n型雜質、例如As(砷)。補償間隙壁OFa、OFc、OFd之寬度Losw3係以如下方式設定。
Tsi≦Losw3≦Tsi+Tbox
又，如圖4(b)所示，於完全空乏型p通道SOI電晶體中，於在閘極電極GE之側壁形成塊狀電晶體用之補償間隙壁OFc、OFd與完全空乏型p通道SOI電晶體用之補償間隙壁OFa、OFb後，離子注入p型雜質、例如B(硼)。補償間隙壁OFa、OFb、OFc、OFd之寬度Losw4係以如下方式設定。
Tsi≦Losw4≦Tsi+Tbox
Losw3<Losw4
即，於將塊狀電晶體用之補償間隙壁形成於完全空乏型SOI電晶體之閘極電極GE之側壁之情形時，考慮塊狀電晶體用之補償間隙壁之寬度而設定完全空乏型SOI電晶體用之補償間隙壁之寬度。藉此，即便塊狀電晶體用之補償間隙壁形成於完全空乏型SOI電晶體之閘極 電極GE之側壁，亦可進行閘極電極GE與延伸層EX之重疊(閘極重疊)之適當化。
再者，於上述完全空乏型n通道SOI電晶體中，在閘極電極GE之側壁形成3層補償間隙壁OFa、OFc、OFd，於上述完全空乏型p通道SOI電晶體中，在閘極電極GE之側壁形成4層補償間隙壁OFa、OFb、OFc、OFd，但補償間隙壁之層數並不限定於此。
<半導體裝置之製造方法>
使用圖5~圖27按步驟順序說明本實施形態之半導體裝置(完全空乏型SOI電晶體及塊狀電晶體)之製造方法之一例。圖5~圖27係本實施形態之半導體裝置之製造步驟中之主要部分剖視圖。此處，例示使用上述圖4(a)及(b)所說明之第3完全空乏型SOI電晶體之製造方法。
於本實施形態中，將形成SOI電晶體(n通道SOI電晶體或p通道SOI電晶體)之區域稱為SOI區域1A，將形成塊狀電晶體(n通道SOI電晶體或p通道SOI電晶體)之區域稱為塊狀區域1B。於SOI區域1A中，SOI電晶體係形成於包含半導體基板、半導體基板上之絕緣膜、及絕緣膜上之半導體層的SOI基板之主面，於塊狀區域1B中，塊狀電晶體係形成於半導體基板之主面。於以下之說明中，於圖之左側表示SOI區域1A，於圖之右側表示塊狀區域1B。
如圖5所示，準備於上方積層有絕緣膜BX及半導體層SL之半導體基板SB。半導體基板SB係含有單晶Si(矽)之支持基板，半導體基板SB上之絕緣膜BX含有氧化矽，絕緣膜BX上之半導體層SL含有具有1~10Ωcm左右之電阻之單晶矽。絕緣膜BX之厚度例如為10~20nm左右，半導體層SL之厚度例如為10~20nm左右。
SOI基板可藉由例如SIMOX(Silicon Implanted Oxide，注氧隔離)法或貼合法而形成。SIMOX法係對含有Si(矽)之半導體基板之主面以較高之能量離子注入O2(氧)，藉由其後之熱處理使Si(矽)與O2(氧)鍵 結，而於較半導體基板之表面略深之位置形成嵌入氧化膜(BOX膜)，藉此形成SOI基板。又，貼合法係藉由施加高熱及壓力而將於表面形成有氧化膜(BOX膜)之含有Si(矽)之半導體基板、與另一片含有Si(矽)之半導體基板接著並貼合後，對單側之半導體基板進行研磨而薄膜化，藉此形成SOI基板。
其次，如圖6所示，於半導體基板SB上形成包含具有STI(Shallow Trench Isolation，淺槽隔離)構造之絕緣膜之元件分離部STI。
於形成元件分離部STI之步驟中，首先，於半導體層SL上形成含有氮化矽之硬質遮罩圖案，並將該硬質遮罩圖案作為遮罩進行乾式蝕刻，藉此形成自半導體層SL之上表面到達至半導體基板SB之中途深度之複數個槽。複數個槽係使半導體層SL、絕緣膜BX及半導體基板SB開口而形成。繼而，於在複數個槽之內側形成襯墊氧化膜後，於包含複數個槽之內部之半導體層SL上，藉由例如CVD(Chemical Vapor Deposition，化學氣相沈積)法形成例如含有氧化矽之絕緣膜。繼而，藉由例如CMP(Chemical Mechanical Polishing，化學機械拋光)法研磨該絕緣膜之上表面，而於複數個槽之內部殘留絕緣膜。其後，去除硬質遮罩圖案。藉此，形成元件分離部STI。
元件分離部STI係將半導體基板SB上之複數個活性區域彼此分離之非活性區域。亦即，活性區域之俯視下之形狀係藉由被元件分離部STI包圍而規定。又，以將SOI區域1A與塊狀區域1B之間分離之方式形成有複數個元件分離部STI，於SOI區域1A及塊狀區域1B之各者中，以將相鄰之元件形成區域之間分離之方式形成有複數個元件分離部STI。
其次，如圖7所示，例如藉由熱氧化法於半導體層SL之上表面形成例如含有氧化矽之絕緣膜OX。再者，亦可藉由殘留上述含有氮化矽之硬質遮罩圖案之一部分而形成絕緣膜OX。
繼而，於形成n通道SOI電晶體之SOI區域1A，介隔絕緣膜OX、半導體層SL及絕緣膜BX離子注入雜質，藉此，於半導體基板SB之所需區域選擇性地形成p型井PW1及臨界電壓控制擴散區域E1。同樣地，於形成p通道SOI電晶體之SOI區域1A，介隔絕緣膜OX、半導體層SL及絕緣膜BX離子注入雜質，藉此，於半導體基板SB之所需區域選擇性地形成n型井NW1及臨界電壓控制擴散區域E2。
繼而，於形成n通道塊狀電晶體之塊狀區域1B，介隔絕緣膜OX、半導體層SL及絕緣膜BX離子注入雜質，藉此，於半導體基板SB之所需區域選擇性地形成p型井PW2及臨界電壓控制擴散區域E3。同樣地，於形成p通道塊狀電晶體之塊狀區域1B，介隔絕緣膜OX、半導體層SL及絕緣膜BX離子注入雜質，藉此，於半導體基板SB之所需區域選擇性地形成n型井NW2及臨界電壓控制擴散區域E4。
其次，如圖8所示，藉由例如微影技術於SOI區域1A形成光阻圖案RP1。具體而言，於SOI基板上塗佈光阻膜，形成如使塊狀區域1B開口之光阻圖案RP1。此時，以施加於SOI區域1A與塊狀區域1B之邊界之元件分離部STI之方式形成光阻圖案RP1。
其次，如圖9所示，藉由例如氟酸洗淨而去除塊狀區域1B之絕緣膜OX。此時，由於塊狀區域1B之元件分離部STI之上部之一部分亦被削去，故而於塊狀區域1B中，可調整半導體基板SB與元件分離部STI之階差，且可使產生於光阻圖案RP1之邊界部之STI上之階差平緩。
繼而，藉由例如乾式蝕刻法將絕緣膜BX作為終止層而選擇性地去除塊狀區域1B之半導體層SL後，去除光阻圖案RP1。其後，若有必要，亦可使用犧牲氧化法，該犧牲氧化法係於藉由例如氟酸洗淨而去除塊狀區域1B之絕緣膜BX後，藉由例如熱氧化法於半導體基板SB之表面形成例如10nm左右之熱氧化膜，並將該所形成之熱氧化膜去除。藉此，可將因去除半導體層SL之乾式蝕刻而導入至半導體基板 SB之變質層去除。
於經過以上步驟而形成之SOI區域1A及塊狀區域1B中，SOI區域1A之半導體層SL表面與塊狀區域1B之半導體基板SB之表面的階差小至20nm左右。此於其後之成為閘極電極之多晶矽膜之堆積及加工中，能以同一步驟形成SOI電晶體與塊狀電晶體，且對防止階差部之加工殘留或閘極電極之斷線等有效。
其次，如圖10所示，於SOI區域1A形成SOI電晶體之閘極絕緣膜F1且於塊狀區域1B形成塊狀電晶體之閘極絕緣膜F2。閘極絕緣膜F1之厚度為例如2~3nm左右，閘極絕緣膜F2之厚度為例如7~8nm左右。其後，藉由例如CVD法於閘極絕緣膜F1、F2上依序積層多晶矽膜G1及氮化矽膜D1。多晶矽膜G1之厚度為例如40nm左右，氮化矽膜D1之厚度為例如30nm左右。再者，本實施形態中所使用之剖視圖中，為了使圖易於理解，而未正確地表示各膜之各者之膜厚的大小關係。
SOI電晶體之閘極絕緣膜F1及塊狀電晶體之閘極絕緣膜F2具體而言係以下述方式形成。首先，藉由例如氟酸洗淨而去除露出於塊狀區域1B之表面之絕緣膜BX，從而使塊狀區域1B之半導體基板SB之表面露出。繼而，藉由例如熱氧化法於塊狀區域1B之半導體基板SB上形成例如7.5nm左右之厚度之熱氧化膜。
此時，SOI區域1A亦係同樣地去除露出於表面之絕緣膜OX，且於半導體層SL上形成例如7.5nm左右之厚度之熱氧化膜。於藉由例如微影技術及氟酸洗淨選擇性地去除該熱氧化膜後，為了去除蝕刻殘渣及蝕刻液等而進行洗淨。其後，藉由例如熱氧化法於SOI區域1A之半導體層SL上形成例如2nm左右之厚度之熱氧化膜。
藉由利用NO氣體將該等7.5nm左右之厚度之熱氧化膜及2nm左右之厚度之熱氧化膜之表面氮化，而於主表面積層形成0.2nm左右之 氮化膜，將形成於SOI區域1A之半導體層SL上之絕緣膜(氮化膜/熱氧化膜)設為閘極絕緣膜F1，將形成於塊狀區域1B之半導體基板SB上之絕緣膜(氮化膜/熱氧化膜)設為閘極絕緣膜F2。
如此，可將塊狀電晶體之閘極絕緣膜F2形成得較SOI電晶體之閘極絕緣膜F1厚。藉此，可提高塊狀電晶體之耐壓，從而可進行高電壓動作。
其次，如圖11所示，藉由例如微影技術及各向異性乾式蝕刻法對氮化矽膜D1及多晶矽膜G1進行加工，而於SOI區域1A形成SOI電晶體之包含氮化矽膜D1之閘極保護膜GD及包含多晶矽膜G1之閘極電極GE。同時，於塊狀區域1B形成塊狀電晶體之包含氮化矽膜D1之閘極保護膜GD及包含多晶矽膜G1之閘極電極GE。於本實施形態中，如上所述般SOI區域1A之半導體層SL表面與塊狀區域1B之半導體基板SB之表面的階差低至20nm左右，因此於微影時處於焦點深度之容許範圍內，可同時形成SOI電晶體之閘極保護膜GD及閘極電極GE、與塊狀電晶體之閘極保護膜GD及閘極電極GE。
其次，如圖12所示，藉由例如CVD法堆積例如10nm左右之厚度之氮化矽膜後，藉由例如各向異性乾式蝕刻法選擇性地對該氮化矽膜進行加工。藉此，於SOI電晶體之閘極電極GE及閘極保護膜GD之側壁以及塊狀電晶體之閘極電極GE及閘極保護膜GD之側壁，形成含有氮化矽之補償間隙壁OF1。
其次，如圖13所示，藉由例如微影技術於SOI區域1A、及塊狀區域1B之形成p通道塊狀電晶體之區域，形成光阻圖案RP2。繼而，將光阻圖案RP2作為遮罩，於塊狀區域1B之形成n通道塊狀電晶體之區域離子注入p型雜質、例如BF2(氟化硼)離子，繼而離子注入n型雜質、例如As(砷)離子。藉此，自行對準地形成n通道塊狀電晶體之n型延伸層EBn、及於n型延伸層EBn之通道側形成p型環形區域HAp。於n 通道塊狀電晶體中，藉由設置p型環形區域HAp，可抑制n型延伸層EBn向通道方向之擴散。
其後，去除光阻圖案RP2。
其次，如圖14所示，藉由例如CVD法堆積例如10nm左右之厚度之氧化矽膜後，藉由例如各向異性乾式蝕刻法選擇性地加工該氧化矽膜。藉此，於SOI電晶體之閘極電極GE及閘極保護膜GD之側壁以及塊狀電晶體之閘極電極GE及閘極保護膜GD之側壁，介隔補償側牆OF1而形成含有氧化矽之補償間隙壁OF2。
其次，藉由例如微影技術於SOI區域1A、及塊狀區域1B之形成n通道塊狀電晶體之區域，形成光阻圖案RP3。繼而，將光阻圖案RP3作為遮罩，於塊狀區域1B之形成p通道塊狀電晶體之區域離子注入n型雜質、例如As(砷)離子，繼而，離子注入p型雜質、例如BF2(氟化硼)離子。藉此，自行對準地形成p通道塊狀電晶體之p型延伸層EBp、及於p型延伸層EBp之通道側形成n型環形區域HAn。於p通道塊狀電晶體中，藉由設置n型環形區域HAn，可抑制p型延伸層EBp向通道方向擴散。
其後，去除光阻圖案RP3。
其次，如圖15所示，藉由例如CVD法堆積例如40nm左右之厚度之氮化矽膜後，藉由例如各向異性乾式蝕刻法選擇性地加工該氮化矽膜。藉此，於SOI電晶體之閘極電極GE及閘極保護膜GD之側壁以及塊狀電晶體之閘極電極GE及閘極保護膜GD之側壁，介隔補償側牆OF1、OF2而形成含有氮化矽之側牆SW1。其後，去除塊狀電晶體之側牆SW1，而於SOI電晶體之閘極電極GE及閘極保護膜GD之側壁殘留補償間隙壁OF1、OF2及側牆SW1。
其次，如圖16所示，以保護膜PB覆蓋塊狀區域1B後，例如藉由選擇磊晶成長法於SOI區域1A之露出之半導體層SL上選擇性地形成含 有Si(矽)或SiGe(矽鍺)之堆疊單晶層、即磊晶層EP。其後，去除保護膜PB。
磊晶層EP係藉由使用例如分批式之縱型磊晶成長裝置，將配置有複數個半導體基板之晶舟於作為反應室之爐內進行磊晶成長處理而形成。此時，於爐內供給例如SiH4(矽烷)氣體作為成膜氣體，並且供給含有氯原子之氣體作為蝕刻氣體，藉此進行磊晶成長處理。作為蝕刻氣體之含有氯原子之氣體係可使用例如HCl(鹽酸)氣體或Cl(氯)氣體等。
其次，如圖17所示，藉由例如利用熱磷酸之洗淨而選擇性地去除SOI電晶體之含有氮化矽之閘極保護膜GD及側牆SW1、以及塊狀電晶體之含有氮化矽之閘極保護膜GD。此時，存在SOI電晶體之含有氧化矽之補償間隙壁OF2及塊狀電晶體之含有氧化矽之補償間隙壁OF2之厚度亦變薄之情況。又，於SOI區域1A中，半導體層SL於閘極電極GE與磊晶層EP之間露出。
其次，如圖18所示，藉由例如CVD法堆積例如10nm左右之厚度之氮化矽膜後，藉由例如各向異性乾式蝕刻法選擇性地對該氮化矽膜進行加工。藉此，於SOI電晶體之閘極電極GE之側壁及塊狀電晶體之閘極電極GE之側壁，介隔補償間隙壁OF1、OF2而形成含有氮化矽之補償間隙壁OF3。
此處，如使用上述圖4所說明般，於n通道SOI電晶體中，形成於閘極電極GE之側壁之3層補償間隙壁OF1、OF2、OF3之合計之寬度Lo1係設定為半導體層SL之厚度以上、且半導體層SL與絕緣膜BX之合計之厚度以下。較佳為上述寬度Lo1係設定為與半導體層SL之厚度相同之值。
其次，如圖19所示，藉由例如微影技術於SOI區域1A之形成p通道SOI電晶體之區域及塊狀區域1B，形成光阻圖案RP4。繼而，將光 阻圖案RP4作為遮罩，向形成n通道SOI電晶體之SOI區域1A離子注入n型雜質、例如As(砷)離子。藉此，於n通道SOI電晶體中，於向磊晶層EP離子注入n型雜質之同時，向閘極電極GE之兩側之露出之半導體層SL、或露出於閘極電極GE之兩側之半導體層SL及絕緣膜BX離子注入n型雜質，而形成n型延伸層EAn。
n型延伸層EAn係調整形成於閘極電極GE之側壁之3層補償間隙壁OF1、OF2、OF3之合計之寬度Lo1及n型雜質之離子注入條件(加速能力及注入量)而形成。藉此，於n通道SOI電晶體中，可進行閘極電極GE與n型延伸層EAn之重疊(閘極重疊)之適當化。
其後，去除光阻圖案RP4。
其次，如圖20所示，藉由例如CVD法堆積例如10nm左右之厚度之氧化矽膜後，藉由例如各向異性乾式蝕刻法選擇性地對該氧化矽膜進行加工。藉此，於SOI區域1A之閘極電極GE之側壁及塊狀區域IB之閘極電極GE之側壁，介隔補償間隙壁OF1、OF2、OF3而形成含有氧化矽之補償間隙壁OF4。
此處，如使用上述圖4所說明般，於p通道SOI電晶體中，形成於閘極電極GE之側壁之4層補償間隙壁OF1、OF2、OF3、OF4之合計之寬度Lo2係設定為半導體層SL之厚度以上、且半導體層SL與絕緣膜BX之合計之厚度以下。較佳為上述寬度Lo2係設定為和半導體層SL與絕緣膜BX之合計之厚度相同之值。
其次，如圖21所示，藉由例如微影技術於SOI區域1A之形成n通道SOI電晶體之區域及塊狀區域1B，形成光阻圖案RP5。繼而，將光阻圖案RP5作為遮罩，向形成p通道SOI電晶體之SOI區域1A離子注入p型雜質、例如B(硼)離子。藉此，於p通道SOI電晶體中，於向磊晶層EP離子注入p型雜質之同時，向閘極電極GE之兩側之露出之半導體層SL、或露出於閘極電極GE之兩側之半導體層SL及絕緣膜BX離子注入 p型雜質，而形成p型延伸層EAp。
p型延伸層EAp係調整形成於閘極電極GE之側壁之4層補償間隙壁OF1、OF2、OF3、OF4之合計之寬度Lo2及p型雜質之離子注入條件(加速能力及注入量)而形成。藉此，於p通道SOI電晶體中，可進行閘極電極GE與p型延伸層EAp之重疊(閘極重疊)之適當化。
其後，去除光阻圖案RP5。
其次，如圖22所示，藉由例如CVD法堆積例如40nm左右之厚度之氮化矽膜後，藉由例如各向異性乾式蝕刻法選擇性地對該氮化矽膜進行加工。藉此，於SOI電晶體之閘極電極GE之側壁及塊狀電晶體之閘極電極GE之側壁，介隔補償間隙壁OF1、OF2、OF3、OF4而形成含有氮化矽之側牆SW2。此時，於SOI區域1A中，於閘極電極GE與磊晶層EP之間露出之半導體層SL上由側牆SW2覆蓋。
其次，如圖23所示，藉由例如微影技術於SOI區域1A之形成p通道SOI電晶體之區域及塊狀區域1B之形成p通道塊狀電晶體之區域，形成光阻圖案RP6。繼而，將光阻圖案RP6作為遮罩，向SOI區域1A之形成n通道SOI電晶體之區域及塊狀區域1B之形成n通道塊狀電晶體之區域離子注入n型雜質、例如As(砷)離子。藉此，於n通道SOI電晶體中，在磊晶層EP及磊晶層EP下之半導體層SL形成n型擴散層SDn1，於n通道塊狀電晶體中，在閘極電極GE之兩側之半導體基板SB形成n型擴散層SDn2。
其後，去除光阻圖案RP6。
其次，如圖24所示，藉由例如微影技術於SOI區域1A之形成n通道SOI電晶體之區域及塊狀區域1B之形成n通道塊狀電晶體之區域，形成光阻圖案RP7。繼而，將光阻圖案RP7作為遮罩，向SOI區域1A之形成p通道SOI電晶體之區域及塊狀區域1B之形成p通道塊狀電晶體之區域離子注入p型雜質、例如BF2(氟化硼)離子。藉此，於p通道SOI 電晶體中，在磊晶層EP及磊晶層EP下之半導體層SL形成n型擴散層SDp1，於p通道塊狀電晶體中，在閘極電極GE之兩側之半導體基板SB形成p型擴散層SDp2。
其後，去除光阻圖案RP7。
繼而，使利用例如RTA(Rapid Thermal Anneal，快速高熱退火)法而注入之雜質活化且熱擴散。作為RTA之條件，例如可例示氮氣氛圍、1050℃。
此時，n通道SOI電晶體之n型延伸層EAn亦進行熱擴散，但預先考慮熱擴散之擴散距離等而設定形成於閘極電極GE之側壁之補償間隙壁OF1、OF2、OF3之厚度及n型雜質之離子注入條件等。藉此，可防止n型延伸層EAn自閘極電極GE之端部下向通道方向之擴散、及n型延伸層EAn超過絕緣膜BX向半導體基板SB之擴散。
同樣地，p通道SOI電晶體之p型延伸層EAp亦進行熱擴散，但預先考慮熱擴散之擴散距離等而設定形成於閘極電極GE之側壁之補償間隙壁OF1、OF2、OF3、OF4之厚度及p型雜質之離子注入條件等。藉此，可防止p型延伸層EAp自閘極電極GE之端部下向通道方向之擴散、及p型延伸層EAp超過絕緣膜BX向半導體基板SB之擴散。
其次，如圖25所示，藉由例如濺鍍法堆積金屬膜、例如20nm左右之厚度之Ni(鎳)膜後，藉由例如320℃左右之熱處理使Ni(鎳)與Si(矽)反應，而形成矽化鎳層NS。繼而，藉由例如HCl(鹽酸)與H2O2(雙氧水)之混合水溶液去除未反應之Ni(鎳)後，藉由例如550℃左右之熱處理控制矽化鎳層NS之相位。
藉此，於SOI區域1A中，在SOI電晶體之閘極電極GE及磊晶層Ep各自之上部形成矽化鎳層NS，於塊狀區域1B中，在塊狀電晶體之閘極電極GE、n型擴散層SDn2及p型擴散層SDp2各自之上部形成矽化鎳層NS。
藉由上述步驟，而於SOI區域1A，形成具有源極、汲極(n型延伸層EAn與n型擴散層SDn1)與閘極電極GE之n通道SOI電晶體、以及具有源極、汲極(p型延伸層EAp與p型擴散層SDp1)與閘極電極GE之p通道SOI電晶體。又，於塊狀區域1B，形成具有源極、汲極(n型延伸層EBn與n型擴散層SDn2)與閘極電極GE之n通道塊狀電晶體、以及具有源極、汲極(p型延伸層EBp與p型擴散層SDp2)與閘極電極GE之p通道塊狀電晶體。
其次，如圖26所示，依序堆積被用作包含氮化矽膜之蝕刻終止膜之絕緣膜、及包含氧化矽膜之絕緣膜，而形成層間絕緣膜IL後，使層間絕緣膜IL之表面平坦化。
其次，如圖27所示，將層間絕緣膜IL貫通，而形成到達至分別形成於SOI電晶體及塊狀電晶體之閘極電極GE之上部之矽化鎳層NS的接觸孔(省略圖示)、以及到達至分別形成於SOI電晶體及塊狀電晶體之源極、汲極之上部之矽化鎳層NS的接觸孔CNT。
繼而，於包含接觸孔CNT之內部之層間絕緣膜IL上，藉由例如濺鍍法依序形成含有例如Ti(鈦)之障壁導體膜與W(鎢)膜。其後，藉由例如CMP法去除層間絕緣膜IL上之障壁導體膜及W(鎢)膜，而於接觸孔CNT之內部形成將W(鎢)膜作為主導體膜之柱狀之接觸插塞CP。
其後，形成電性連接於接觸插塞CP之配線層，進而形成上層之配線等，藉此大致完成本實施形態之半導體裝置。
如此，根據本實施形態，由於在完全空乏型SOI電晶體中，可抑制閘極電極與延伸層之重疊(閘極重疊)，故而可謀求短通道效應降低、漏電流(閘極漏電流及GIDL)降低、寄生電容降低。因此，可提高具有完全空乏型SOI電晶體之半導體裝置之可靠性及性能。
以上，雖基於實施形態對由本發明者完成之發明具體進行了說明，但本發明並不限定於上述實施形態，當然可於不脫離其主旨之範 圍內進行各種變更。
BX‧‧‧絕緣膜
EX‧‧‧延伸層
GE‧‧‧閘極電極
Losw‧‧‧寬度
OF‧‧‧補償間隙壁
SB‧‧‧半導體基板
SL‧‧‧半導體層
Tbox‧‧‧厚度
Tsi‧‧‧厚度

Claims (17)

  1. 一種半導體裝置，其係於第1區域具備第1場效電晶體者，且上述第1場效電晶體包括：SOI基板，其具有半導體基板、上述半導體基板上之絕緣膜、及上述絕緣膜上之半導體層；第1閘極電極，其係介隔第1閘極絕緣膜而形成於上述半導體層上；第1補償間隙壁，其形成於上述第1閘極電極之側壁；第1導電型之第1延伸層，其形成於上述第1閘極電極之兩側之上述半導體層；及源極、汲極用之上述第1導電型之第1磊晶層，其形成於未形成上述第1閘極電極及上述第1補償間隙壁之上述半導體層上；且上述第1補償間隙壁之寬度為上述半導體層之厚度以上、且上述半導體層與上述絕緣膜之合計之厚度以下。
  2. 如請求項1之半導體裝置，其中上述第1延伸層未超過上述絕緣膜與上述半導體基板之界面而分佈於上述半導體基板。
  3. 如請求項1之半導體裝置，其中於與上述第1區域不同之第2區域具備第2場效電晶體；上述第2場效電晶體包括：上述SOI基板；第2閘極電極，其係介隔第2閘極絕緣膜而形成於上述半導體層上；第2補償間隙壁，其形成於上述第2閘極電極之側壁； 與上述第1導電型不同之第2導電型之第2延伸層，其形成於上述第2閘極電極之兩側之上述半導體層；及源極、汲極用之上述第2導電型之第2磊晶層，其形成於未形成上述第2閘極電極及上述第2補償間隙壁之上述半導體層上；且上述第2補償間隙壁之寬度為上述半導體層之厚度以上、且上述半導體層與上述絕緣膜之合計之厚度以下；上述第2延伸層距上述半導體層之上表面之深度較上述第1延伸層距上述半導體層之上表面之深度更深。
  4. 如請求項3之半導體裝置，其中上述第1導電型為n型，上述第2導電型為p型。
  5. 如請求項3之半導體裝置，其中上述第2延伸層未超過上述絕緣膜與上述半導體基板之界面而分佈於上述半導體基板。
  6. 如請求項1之半導體裝置，其中於與上述第1區域不同之第3區域具備第3場效電晶體；上述第3場效電晶體包括：上述半導體基板；第3閘極電極，其係介隔第3閘極絕緣膜而形成於上述半導體基板上；第3補償間隙壁，其形成於上述第3閘極電極之側壁；及上述第1導電型之第3延伸層，其形成於上述第3閘極電極之兩側之上述半導體基板；且於上述第3延伸層之通道側形成有與上述第1導電型不同之第2導電型之半導體區域。
  7. 如請求項6之半導體裝置，其中 上述第3閘極絕緣膜之厚度較上述第1閘極絕緣膜之厚度更厚。
  8. 一種半導體裝置之製造方法，其係形成場效電晶體者，且包括如下步驟：(a)準備具有半導體基板、上述半導體基板上之絕緣膜、及上述絕緣膜上之半導體層的SOI基板；(b)於上述半導體層上介隔閘極絕緣膜而形成閘極電極；(c)於上述閘極電極之側壁，形成第1寬度之第1側牆；(d)於上述(c)步驟之後，在未被上述閘極電極及上述第1側牆覆蓋而露出之上述半導體層上，形成磊晶層；(e)於上述(d)步驟之後，去除上述第1側牆；(f)於上述(e)步驟之後，在上述閘極電極之側壁形成較上述第1寬度更小之第2寬度之補償間隙壁；(g)於上述(f)步驟之後，向未被上述閘極電極及上述補償間隙壁覆蓋之上述半導體層離子注入雜質，而於上述閘極電極之兩側之上述半導體層形成第1導電型之延伸層；(h)於上述(g)步驟之後，在上述閘極電極之側壁形成第2側牆；(i)於上述(h)步驟之後，在上述磊晶層與上述半導體層之積層部形成上述第1導電型之擴散層；且於上述(f)步驟中，形成於上述閘極電極之側壁之上述補償間隙壁之上述第2寬度為上述半導體層之厚度以上、且上述半導體層與上述絕緣膜之合計之厚度以下。
  9. 如請求項8之半導體裝置之製造方法，其中進而包括如下步驟：(j)於上述(i)步驟之後，在上述磊晶層上形成矽化物層。
  10. 如請求項8之半導體裝置之製造方法，其中上述半導體層之厚度為10~20nm，上述絕緣膜之厚度為10~ 20nm。
  11. 如請求項8之半導體裝置之製造方法，其中上述延伸層之雜質濃度低於上述擴散層之雜質濃度。
  12. 一種半導體裝置之製造方法，其係於第1區域形成第1場效電晶體，且於與上述第1區域不同之第2區域形成第2場效電晶體者，且包括如下步驟：(a)準備具有半導體基板、上述半導體基板上之絕緣膜、及上述絕緣膜上之半導體層的SOI基板；(b)去除上述第2區域之上述絕緣膜及上述半導體層；(c)於上述第1區域之上述半導體層上介隔第1閘極絕緣膜而形成第1閘極電極，且於上述第2區域之上述半導體基板上介隔第2閘極絕緣膜而形成第2閘極電極；(d)於上述第1閘極電極及上述第2閘極電極之各者之側壁形成第1補償間隙壁；(e)於上述(d)步驟之後，向未被上述第2區域之上述第2閘極電極及上述第1補償間隙壁覆蓋之上述半導體基板離子注入第1雜質，而於上述第2閘極電極之兩側之上述半導體基板形成第1導電型之第1延伸層；(f)於上述(e)步驟之後，在上述第1區域之上述第1閘極電極之側壁介隔上述第1補償間隙壁而形成第1寬度之第1側牆；(g)於上述(f)步驟之後，在未被上述第1區域之上述第1閘極電極、上述第1補償間隙壁及上述第1側牆覆蓋而露出之上述半導體層上，形成磊晶層；(h)於上述(g)步驟之後，去除上述第1側牆；(i)於上述(h)步驟之後，在上述第1閘極電極及上述第2閘極電極之各者之側壁，介隔上述第1補償間隙壁而形成較上述第1寬 度更小之第2寬度之第2補償間隙壁；(j)於上述(i)步驟之後，向未被上述第1區域之上述第1閘極電極、上述第1補償間隙壁及上述第2補償間隙壁覆蓋之上述半導體層離子注入第2雜質，而於上述第1閘極電極之兩側之上述半導體層形成上述第1導電型之第2延伸層；(k)於上述(j)步驟之後，在上述第1閘極電極及上述第2閘極電極之各者之側壁，介隔上述第1補償間隙壁及上述第2補償間隙壁而形成第2側牆；及(l)於上述(k)步驟之後，在上述第1區域之上述磊晶層與上述半導體層之積層部形成上述第1導電型之第1擴散層；且於上述(i)步驟中，覆蓋上述第1閘極電極之側壁之上述第1補償間隙壁與上述第2補償間隙壁之合計之寬度為上述半導體層之厚度以上、且上述半導體層與上述絕緣膜之合計之厚度以下。
  13. 如請求項12之半導體裝置之製造方法，其中進而包括如下步驟：(m)於上述(l)步驟之後，在上述磊晶層上形成矽化物層。
  14. 如請求項12之半導體裝置之製造方法，其中上述半導體層之厚度為10~20nm，上述絕緣膜之厚度為10~20nm。
  15. 如請求項12之半導體裝置之製造方法，其中上述第1閘極絕緣膜之厚度較上述第2閘極絕緣膜之厚度更薄。
  16. 如請求項12之半導體裝置之製造方法，其中於上述(l)步驟中，與形成上述第1區域之上述第1擴散層之同時，於上述第2區域之上述第1閘極電極之兩側之上述半導體基板形成上述第1導電型之第2擴散層。
  17. 如請求項12之半導體裝置之製造方法，其中進而包括如下步驟：(n)於上述(e)步驟之前或之後，向未被上述第2區域之上述第2閘極電極及上述第1補償間隙壁覆蓋之上述半導體基板離子注入第3雜質，而於上述第2閘極電極之兩側之上述半導體基板，在上述第1延伸層之通道側形成與上述第1導電型不同之第2導電型之半導體區域。
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