JP2016004845A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2016004845A JP2016004845A JP2014122894A JP2014122894A JP2016004845A JP 2016004845 A JP2016004845 A JP 2016004845A JP 2014122894 A JP2014122894 A JP 2014122894A JP 2014122894 A JP2014122894 A JP 2014122894A JP 2016004845 A JP2016004845 A JP 2016004845A
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Abstract
【解決手段】ゲート電極GEの側壁に形成されたオフセットスペーサOFの幅Loswを、半導体層SLの厚さTsi以上、半導体層SLの厚さTsiと絶縁膜BXの厚さTboxとの合計の厚さ以下に設定して、ゲート電極GEおよびオフセットスペーサOFで覆われていない半導体層SLへ不純物をイオン注入する。これにより、不純物のイオン注入により形成されるエクステンション層EXがゲート電極GEの端部下からチャネル内へ入り込まないようにする。
【選択図】図2
Description
本実施の形態による半導体装置がより明確となると思われるため、本発明者によって見いだされた完全空乏型SOIトランジスタにおける解決しようとする課題について説明する。
<第1の完全空乏型SOIトランジスタの構造>
本実施の形態による第1の完全空乏型SOIトランジスタの構造について図1を用いて説明する。図1は、本実施の形態による第1の完全空乏型SOIトランジスタの構造を説明する要部断面図である。
Tsi≦Losw≦Tsi+Tbox
となるように設定する。例えば半導体層SLの厚さが12nm、絶縁膜BXの厚さが10nmであれば、エクステンション層EXの幅Loswは、12〜22nmの範囲で設定すればよい。
本実施の形態による第2の完全空乏型SOIトランジスタのエクステンション層の構成について図3(a)および(b)を用いて説明する。図3(a)は、第2の完全空乏型nチャネルSOIトランジスタの一部を拡大して示す概略断面図、図3(b)は、第2の完全空乏型pチャネルSOIトランジスタの一部を拡大して示す概略断面図である。
Tsi≦Losw1≦Tsi+Tbox
となるように設定する。
Tsi≦Losw2≦Tsi+Tbox
Losw1<Losw2
となるように設定する。
本実施の形態による第3の完全空乏型SOIトランジスタのエクステンション層の構造について図4(a)および(b)を用いて説明する。図4(a)は、第3の完全空乏型nチャネルSOIトランジスタの一部を拡大して示す概略断面図、図4(b)は、第3の完全空乏型pチャネルSOIトランジスタの一部を拡大して示す概略断面図である。
Tsi≦Losw3≦Tsi+Tbox
となるように設定する。
Tsi≦Losw4≦Tsi+Tbox
Losw3<Lose4
となるように設定する。
本実施の形態による半導体装置(完全空乏型SOIトランジスタおよびバルクトランジスタ)の製造方法の一例を図5〜図27を用いて工程順に説明する。図5〜図27は、本実施の形態による半導体装置の製造工程中の要部断面図である。ここでは、前記図4(a)および(b)を用いて説明した第3の完全空乏型SOIトランジスタの製造方法を例示する。
CNT コンタクトホール
CP コンタクトプラグ
D1 窒化シリコン膜
E1〜E4 しきい電圧制御拡散領域
EAn n型エクステンション層
EAp p型エクステンション層
EBn n型エクステンション層
EBp p型エクステンション層
EP エピタキシャル層
EX エクステンション層
F1,F2 ゲート絶縁膜
G1 多結晶シリコン膜
GD ゲート保護膜
GE ゲート電極
GI ゲート絶縁膜
HAn n型ハロー領域
HAp p型ハロー領域
IL 層間絶縁膜
MS 金属シリサイド層
NS ニッケルシリサイド層
NW1,NW2 n型ウェル
OF,OF1〜OF4,OFa,OFb,OFc,OFd オフセットスペーサ
OX 絶縁膜
PB プロテクション膜
RP1〜RP7 フォトレジストパターン
PW1,PW2 p型ウェル
SB 半導体基板
SD 拡散層
SDn1,SDn2 n型拡散層
SDp1,SDp2 p型拡散層
SL 半導体層(SOI層、シリコン層)
STI 素子分離部
SW,SW1,SW2 サイドウォール
Tsi≦Losw4≦Tsi+Tbox
Losw3<Losw4
となるように設定する。
Claims (17)
- 第1電界効果トランジスタを第1領域に備える半導体装置であって、
前記第1電界効果トランジスタは、
半導体基板、前記半導体基板上の絶縁膜、および前記絶縁膜上の半導体層を有するSOI基板と、
前記半導体層上に第1ゲート絶縁膜を介して形成された第1ゲート電極と、
前記第1ゲート電極の側壁に形成された第1オフセットスペーサと、
前記第1ゲート電極の両側の前記半導体層に形成された第1導電型の第1エクステンション層と、
前記第1ゲート電極および前記第1オフセットスペーサが形成されていない前記半導体層上に形成されたソース・ドレイン用の前記第1導電型の第1エピタキシャル層と、
を有し、
前記第1オフセットスペーサの幅は、前記半導体層の厚さ以上、前記半導体層と前記絶縁膜との合計の厚さ以下である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1エクステンション層は、前記絶縁膜と前記半導体基板との界面を超えて、前記半導体基板に分布していない、半導体装置。 - 請求項1記載の半導体装置において、
第2電界効果トランジスタを前記第1領域とは異なる第2領域に備え、
前記第2電界効果トランジスタは、
前記SOI基板と、
前記半導体層上に第2ゲート絶縁膜を介して形成された第2ゲート電極と、
前記第2ゲート電極の側壁に形成された第2オフセットスペーサと、
前記第2ゲート電極の両側の前記半導体層に形成された前記第1導電型と異なる第2導電型の第2エクステンション層と、
前記第2ゲート電極および前記第2オフセットスペーサが形成されていない前記半導体層上に形成されたソース・ドレイン用の前記第2導電型の第2エピタキシャル層と、
を有し、
前記第2オフセットスペーサの幅は、前記半導体層の厚さ以上、前記半導体層と前記絶縁膜との合計の厚さ以下であり、
前記第2エクステンション層の前記半導体層の上面からの深さは、前記第1エクステンション層の前記半導体層の上面からの深さよりも深い、半導体装置。 - 請求項3記載の半導体装置において、
前記第1導電型はn型、前記第2導電型はp型である、半導体装置。 - 請求項3記載の半導体装置において、
前記第2エクステンション層は、前記絶縁膜と前記半導体基板との界面を超えて、前記半導体基板に分布していない、半導体装置。 - 請求項1記載の半導体装置において、
第3電界効果トランジスタを前記第1領域とは異なる第3領域に備え、
前記第3電界効果トランジスタは、
前記半導体基板と、
前記半導体基板上に第3ゲート絶縁膜を介して形成された第3ゲート電極と、
前記第3ゲート電極の側壁に形成された第3オフセットスペーサと、
前記第3ゲート電極の両側の前記半導体基板に形成された前記第1導電型の第3エクステンション層と、
を有し、
前記第3エクステンション層のチャネル側に、前記第1導電型とは異なる第2導電型の半導体領域が形成されている、半導体装置。 - 請求項6記載の半導体装置において、
前記第3ゲート絶縁膜の厚さは、前記第1ゲート絶縁膜の厚さよりも厚い、半導体装置。 - 電界効果トランジスタを形成する半導体装置の製造方法であって、
(a)半導体基板、前記半導体基板上の絶縁膜、および前記絶縁膜上の半導体層を有するSOI基板を準備する工程、
(b)前記半導体層上にゲート絶縁膜を介してゲート電極を形成する工程、
(c)前記ゲート電極の側壁に、第1幅の第1サイドウォールを形成する工程、
(d)前記(c)工程の後、前記ゲート電極および前記第1サイドウォールで覆われずに露出する前記半導体層上に、エピタキシャル層を形成する工程、
(e)前記(d)工程の後、前記第1サイドウォールを除去する工程、
(f)前記(e)工程の後、前記ゲート電極の側壁に、前記第1幅よりも小さい第2幅のオフセットスペーサを形成する工程、
(g)前記(f)工程の後、前記ゲート電極および前記オフセットスペーサで覆われていない前記半導体層に不純物をイオン注入して、前記ゲート電極の両側の前記半導体層に第1導電型のエクステンション層を形成する工程、
(h)前記(g)工程の後、前記ゲート電極の側壁に第2サイドウォールを形成する工程、
(i)前記(h)工程の後、前記エピタキシャル層と前記半導体層との積層部に前記第1導電型の拡散層を形成する工程、
を有し、
前記(f)工程において、前記ゲート電極の側壁に形成される前記オフセットスペーサの前記第2幅は、前記半導体層の厚さ以上、前記半導体層と前記絶縁膜との合計の厚さ以下である、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
(j)前記(i)工程の後、前記エピタキシャル層上に、シリサイド層を形成する工程、
をさらに有する、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記半導体層の厚さは10〜20nm、前記絶縁膜の厚さは10〜20nmである、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記エクステンション層の不純物濃度は、前記拡散層の不純物濃度よりも低い、半導体装置の製造方法。 - 第1領域に第1電界効果トランジスタを形成し、前記第1領域とは異なる第2領域に第2電界効果トランジスタを形成する半導体装置の製造方法であって、
(a)半導体基板、前記半導体基板上の絶縁膜、および前記絶縁膜上の半導体層を有するSOI基板を準備する工程、
(b)前記第2領域の前記絶縁膜および前記半導体層を除去する工程、
(c)前記第1領域の前記半導体層上に第1ゲート絶縁膜を介して第1ゲート電極を形成し、前記第2領域の前記半導体基板上に第2ゲート絶縁膜を介して第2ゲート電極を形成する工程、
(d)前記第1ゲート電極および前記第2ゲート電極のそれぞれの側壁に第1オフセットスペーサを形成する工程、
(e)前記(d)工程の後、前記第2領域の前記第2ゲート電極および前記第1オフセットスペーサで覆われていない前記半導体基板に第1不純物をイオン注入して、前記第2ゲート電極の両側の前記半導体基板に第1導電型の第1エクステンション層を形成する工程、
(f)前記(e)工程の後、前記第1領域の前記第1ゲート電極の側壁に前記第1オフセットスペーサを介して、第1幅の第1サイドウォールを形成する工程、
(g)前記(f)工程の後、前記第1領域の前記第1ゲート電極、前記第1オフセットスペーサおよび前記第1サイドウォールで覆われずに露出する前記半導体層上に、エピタキシャル層を形成する工程、
(h)前記(g)工程の後、前記第1サイドウォールを除去する工程、
(i)前記(h)工程の後、前記第1ゲート電極および前記第2ゲート電極のそれぞれの側壁に前記第1オフセットスペーサを介して、前記第1幅よりも小さい第2幅の第2オフセットスペーサを形成する工程、
(j)前記(i)工程の後、前記第1領域の前記第1ゲート電極、前記第1オフセットスペーサおよび前記第2オフセットスペーサで覆われていない前記半導体層に第2不純物をイオン注入して、前記第1ゲート電極の両側の前記半導体層に前記第1導電型の第2エクステンション層を形成する工程、
(k)前記(j)工程の後、前記第1ゲート電極および前記第2ゲート電極のそれぞれの側壁に前記第1オフセットスペーサおよび前記第2オフセットスペーサを介して第2サイドウォールを形成する工程、
(l)前記(k)工程の後、前記第1領域の前記エピタキシャル層と前記半導体層との積層部に前記第1導電型の第1拡散層を形成する工程、
を有し、
前記(i)工程において、前記第1ゲート電極の側壁を覆う前記第1オフセットスペーサと前記第2オフセットスペーサとの合計の幅は、前記半導体層の厚さ以上、前記半導体層と前記絶縁膜との合計の厚さ以下である、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
(m)前記(l)工程の後、前記エピタキシャル層上に、シリサイド層を形成する工程、
をさらに有する、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記半導体層の厚さは10〜20nm、前記絶縁膜の厚さは10〜20nmである、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記第1ゲート絶縁膜の厚さが前記第2ゲート絶縁膜の厚さよりも薄い、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記(l)工程において、前記第1領域の前記第1拡散層を形成すると同時に、前記第2領域の前記第1ゲート電極の両側の前記半導体基板に前記第1導電型の第2拡散層を形成する、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
(n)前記(e)工程の前または後に、前記第2領域の前記第2ゲート電極および前記第1オフセットスペーサで覆われていない前記半導体基板に第3不純物をイオン注入して、前記第2ゲート電極の両側の前記半導体基板に、前記第1エクステンション層のチャネル側に前記第1導電型と異なる第2導電型の半導体領域を形成する工程、
をさらに有する、半導体装置の製造方法。
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TWI748098B (zh) * | 2017-05-29 | 2021-12-01 | 日商瑞薩電子股份有限公司 | 半導體裝置之製造方法 |
KR102416132B1 (ko) | 2017-05-29 | 2022-07-04 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치의 제조 방법 |
JP2019207971A (ja) * | 2018-05-30 | 2019-12-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR20190136953A (ko) * | 2018-05-30 | 2019-12-10 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
JP7034834B2 (ja) | 2018-05-30 | 2022-03-14 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US11742199B2 (en) | 2018-05-30 | 2023-08-29 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
KR102669420B1 (ko) * | 2018-05-30 | 2024-05-28 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
JP7385540B2 (ja) | 2020-09-03 | 2023-11-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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US20170040226A1 (en) | 2017-02-09 |
US10050122B2 (en) | 2018-08-14 |
CN105185785B (zh) | 2020-11-27 |
US9508598B2 (en) | 2016-11-29 |
KR20150143333A (ko) | 2015-12-23 |
CN105185785A (zh) | 2015-12-23 |
KR102340048B1 (ko) | 2021-12-16 |
EP2955746A1 (en) | 2015-12-16 |
US20150364490A1 (en) | 2015-12-17 |
TW201611250A (zh) | 2016-03-16 |
JP6275559B2 (ja) | 2018-02-07 |
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