JP6591347B2 - 半導体装置の製造方法 - Google Patents
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Description
<半導体装置の製造工程について>
本実施の形態の半導体装置の製造工程を図面を参照して説明する。図1および図2は、本発明の一実施の形態である半導体装置の製造工程を示すプロセスフロー図である。図3〜図38は、本発明の一実施の形態である半導体装置の製造工程中の要部断面図または要部平面図である。なお、図3〜図38のうち、図3〜図23および図26〜図38は要部断面図であり、図24および図25は要部平面図である。
本発明者が検討した第1検討例について、図39および図40を参照して説明する。図39および図40は、第1検討例の半導体装置の製造工程中の要部断面図である。
本実施の形態の主要な特徴のうちの一つは、ステップS11のエッチング工程を行うことである。
1A SOI領域
1B バルク領域
1C 基板
BX 絶縁層
CP1,CP2 キャップ絶縁膜
CPZ 絶縁膜
CT コンタクトホール
DT ディボット
EP 半導体層
EX1,EX2 n−型半導体領域
GE1,GE2 ゲート電極
GF1,GF2 ゲート絶縁膜
GP 半導体領域
IL1,IL2 絶縁膜
LM,LM1 積層膜
LT1,LT2 積層体
M1 配線
P1 イオン注入
PG プラグ
PS シリコン膜
PR1,PR2,PR3,PR4,PR5 フォトレジストパターン
PW p型ウエル
SB 半導体基板
SD1,SD2 n+型半導体領域
SL 金属シリサイド層
SM,SM1 半導体層
ST 素子分離領域
SW1,SW2,SW3 サイドウォールスペーサ
SZ1,SZ2 絶縁膜
TR 溝
ZM1,ZM2,ZM3 絶縁膜
Claims (11)
- (a)半導体基板と、第1材料から成り、かつ、前記半導体基板上に形成された絶縁層と、前記第1材料とは異なる第2材料から成り、かつ、前記絶縁層上に形成された半導体層と、前記第1材料から成り、かつ、前記半導体層上に形成された第1絶縁膜と、前記半導体層および前記絶縁層を介して前記半導体基板に達する溝と、前記第1材料から成り、かつ、前記溝内に埋め込まれた素子分離領域と、を有する基板を準備する工程と、
(b)前記(a)工程後、前記基板の第1領域における前記第1絶縁膜をエッチングにより除去し、前記第1領域における前記半導体層を露出させ、前記基板の前記第1領域とは異なる第2領域における前記第1絶縁膜を残す工程と、
(c)前記(b)工程後、前記第1領域における前記半導体層をエッチングにより除去し、前記第1領域における前記絶縁層を露出させる工程と、
(d)前記(c)工程後、前記第1領域における前記絶縁層と前記第2領域における前記第1絶縁膜とをエッチングし、前記第1領域における前記絶縁層の厚さと前記第2領域における前記第1絶縁膜の厚さとを薄くする工程と、
(e)前記(d)工程後、前記第2領域における前記半導体基板に不純物を注入し、前記第2領域における前記半導体基板に第1半導体領域を形成する工程と、
(f)前記(e)工程後、前記第1領域における前記絶縁層と前記第2領域における前記第1絶縁膜とをエッチングにより除去し、前記第1領域における前記半導体基板と前記第2領域における前記半導体層とを露出させる工程と、
(g)前記(f)工程後、前記第1領域における前記半導体基板上に第1トランジスタを形成し、前記第2領域における前記半導体層上に第2トランジスタを形成する工程と、
を含む半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程では、前記第1領域における前記半導体層は、第1エッチング液を用いたウェットエッチングにより除去され、
前記(d)工程では、前記第1領域における前記絶縁層および前記第2領域における前記第1絶縁膜は、前記第1エッチング液とは異なる第2エッチング液を用いたウェットエッチングにより除去され、
前記第1エッチング液を用いた場合の前記第1絶縁膜および前記絶縁層のエッチング速度は、前記第1エッチング液を用いた場合の前記半導体層のエッチング速度よりも小さく、
前記第2エッチング液を用いた場合の前記第1絶縁膜および前記絶縁層のエッチング速度は、前記第1エッチング液を用いた場合の前記第1絶縁膜および前記絶縁層のエッチング速度よりも大きい、半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記第1材料は、酸化シリコンから成り、
前記第2材料は、単結晶シリコンから成る、半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記第1エッチング液は、APM液であり、
前記第2エッチング液は、フッ酸である、半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記(f)工程では、前記第1領域における前記絶縁層と前記第2領域における前記第1絶縁膜を、前記第2エッチング液と同種の第3エッチング液を用いたウェットエッチングにより除去する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(b)工程では、前記第2領域における前記第1絶縁膜を覆い、かつ、前記第1領域における前記第1絶縁膜を露出する第1マスク層をエッチングマスクとして用いて、前記第1領域における前記半導体層が露出するように、前記第1領域における前記第1絶縁膜をエッチングにより除去する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程は、
(a1)前記半導体基板と、前記半導体基板上に形成された前記絶縁層と、前記絶縁層上に形成された前記半導体層と、前記半導体層上に形成された前記第1絶縁膜と、前記第1絶縁膜上に形成された第2絶縁膜と、を有する前記基板を準備する工程と、
(a2)前記(a1)工程後、前記第2絶縁膜、前記第1絶縁膜、前記半導体層および前記絶縁層を介して前記半導体基板に達する前記溝を形成する工程と、
(a3)前記(a2)工程後、前記第2絶縁膜上に第3絶縁膜を形成し、前記溝内を前記第3絶縁膜で塞ぐ工程と、
(a4)前記(a3)工程後、前記溝外の前記第3絶縁膜を除去し、前記第3絶縁膜からなる前記素子分離領域を前記溝内に形成する工程と、
(a5)前記(a4)工程後、前記第2絶縁膜をエッチングにより除去する工程と、
を有し、
前記第2絶縁膜は、前記第1絶縁膜とは異なる材料からなる、半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記絶縁層、前記第1絶縁膜および前記第3絶縁膜は、酸化シリコンから成り、
前記第2絶縁膜は、窒化シリコンから成り、
前記(a4)工程では、前記第3絶縁膜を研磨することにより、前記溝の外部の前記第3絶縁膜を除去し、前記溝内に前記第3絶縁膜から成る前記素子分離領域を形成する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1半導体領域は、前記第2トランジスタのしきい値電圧を制御するために形成される、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記素子分離領域は、前記第1領域と前記第2領域との境界に配置されており、
前記(e)工程では、平面視において前記第2領域における前記半導体層に隣接する前記素子分離領域の領域にも、前記不純物が注入される、半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(d)工程後、かつ、前記(e)工程前に、
前記第1領域における前記絶縁層を覆い、かつ、前記第2領域における前記第1絶縁膜を露出する第2マスク層を形成し、
前記(e)工程後、かつ、前記(f)工程前に、前記第2マスク層を除去する、半導体装置の製造方法。
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