CN1264217C - 多重栅极结构及其制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 80
- 238000000034 method Methods 0.000 claims description 61
- 229910052710 silicon Inorganic materials 0.000 claims description 43
- 239000010703 silicon Substances 0.000 claims description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 42
- 230000004888 barrier function Effects 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000009413 insulation Methods 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000007654 immersion Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052914 metal silicate Inorganic materials 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical group [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims 2
- 230000000694 effects Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229960001866 silicon dioxide Drugs 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
本发明是关于一种多重栅极结构及其制造方法,其结构包括:多个鳍型半导体层,沿一第一方向大体平行地排列,且由多个位于一绝缘层上的绝缘台地所支撑,其中上述鳍型半导体层的底面大于与其与绝缘台地的接触面;以及一栅极导电层,沿一第二方向延伸且覆盖于上述鳍型半导体层的部分表面上,且于栅极导电层与其所覆盖的上述鳍型半导体层之间更设置有一栅极介电层,其中此栅极介电层更包覆于该栅极导电层所覆盖部分表面内的此等鳍型半导体层的底面。
Description
技术领域
本发明是有关于一种半导体制程技术,且特别有关于一种高性能的多重栅极结构及其制造方法,特别适合应用在深次微米以下的CMOS组件。
背景技术
金属氧化半导体场效应晶体管(Metal-Oxide-Semiconductor FieldEffect Transistors,以下简称MOSFET)是在集成电路技术技术中相当重要的一种基本电子组件,其由三种基本的材料,即金属导体层、氧化层与半导体层等组成位于半导体基底上的栅极晶体管。此外,还包括了两个位于栅极晶体管两旁,且电性与半导体基底相反的半导体区,称为源极与漏极。目前制作栅极晶体管时,金属导电层多由经掺杂的多晶硅(Polysilicon)与金属共同组成,此结构又称为多晶硅化金属(Polycide)。氧化层多由热氧化法所形成的氧化硅作为闸氧化层。此外,在栅极的侧壁多以氮化硅作为间隔物(spacer)。
虽然上述传统的MOSFET长久以来已被广泛的使用,然而随着半导体技术对积集度要求的提高,传统的MOSFET尺寸及其沟道长度(channellength)亦相对地缩减。当MOSFET组件的沟道长度缩减至低于100nm时,于传统位于半导体硅基底上的MOSFET作用时,便容易由于源极与漏极与其间的沟道相互作用,进而影响了栅极对于其沟道的开启/关闭状态的控制能力,而进一步引起的所谓的短沟道效应(short channel effects;SCE)。
因此,为了使MOSFET于CMOS组件上的应用可以配合MOSFET尺寸缩小化的发展与提高MOSFET积集度的需求,实有必要针对MOSFET于组件缩小化过程中对于其闸沟道开启/关闭状态的控制能力谋求改善之道。
发明内容
有鉴于此,本发明的主要目的就是提供一种多重栅极结构,适合应用于闸沟道长度低于100nm的深次微米以下的CMOS组件上。利用本发明的多重栅极结构以增加对于闸沟道的控制并抑制短沟道效应的产生。除此之外,本发明的多重栅极结构可提供足够的驱动电流,有助于MOSFET作用原理于半导体组件上的继续应用,而不受到组件尺寸缩减的影响。
为达上述目的,本发明提供了一种多重栅极结构,包括:多个鳍型半导体层,沿一第一方向大体平行地排列,且由多个位于一绝缘层上的绝缘台地所支撑,其中上述鳍型半导体层的底面大于与其与绝缘台地的接触面;以及一栅极导电层,沿一第二方向延伸且覆盖于上述鳍型半导体层的部分表面上,且于栅极导电层与其所覆盖的上述鳍型半导体层之间更设置有一栅极介电层,其中此栅极介电层更包覆于该栅极导电层所覆盖部分表面内的此等鳍型半导体层的底面。其中上述绝缘层是位于一半导体基底上,且上述的第一方向是大体正交于第二方向,而上述的鳍型半导体层具有圆滑化的上部边角,以避免尖端放电现象。
此外,上述多重栅极更包括多个源极/漏极区,位于此多重栅极两侧未为该栅极导电层所覆盖的该等鳍型半导体层内,以构成一具有多重栅极(multiple-gate)的多重栅极晶体管(multiple-gate transistor)。而此多重栅极晶体管(multiple-gate transistor)内更包括多个轻掺杂源极/漏极区连接于上述的源极/漏极区,其中此等轻掺杂源极/漏极区是位于源极/漏极区间的鳍型半导体层内。
简言之,本发明的多重栅极的制造方法,其步骤包括:提供一绝缘层上有半导体层的半导体基底;定义上述半导体层以于绝缘层上形成多个鳍型半导体层,其中上述鳍型半导体层沿一第一方向大体平行地排列;蚀刻上述绝缘层,以于绝缘层上形成多个突悬的绝缘台地以支撑鳍型半导体层,其中鳍型半导体层的底面大于与绝缘台地的接触面;形成一保形性的介电层于上述鳍型半导体层表面,其中介电层并覆盖于上述鳍型半导体层未接触该等绝缘台地的底面;形成一导电层覆盖于介电层上;以及分别定义导电层与介电层以分别形成一栅极导电层与一栅极介电层,其中栅极导电层与栅极介电层是沿一第二方向延伸且覆盖于此等鳍型半导体层的部分表面上,以构成一多重栅极结构。
此外,上述多重栅极的制造方法,更包括下列步骤:形成轻掺杂源极/漏极区于上述多重栅极内的此等鳍型半导体层内;形成一绝缘侧壁于栅极导电层的两侧;以及形成源极/漏极区于上述多重栅极两侧的该等鳍型半导体层内,以构成一具有多重栅极(multiple-gate)的多重栅极晶体管(multiple-gate transistor)。
本发明的多重栅极结构,是形成于多个位于绝缘台地上的半导体层内,具有可同时开启或关闭的多个平行于第一方向的闸沟道(gatechannel),且借由栅极介电层与栅极导电层沿第二方向延伸且覆盖于此等闸沟道所在的半导体层的两对应面及上表面外,更覆盖于其未接触绝缘台地的底面,对于此等闸沟道的控制可较习知的栅极结构为佳,而上述的第一方向与第二方向间具有一大体正交的连接关系。
此外,本发明的多重栅极结构可搭配高介电常数介电材料(high-kgate dielectric)的使用以及可应用于绝缘层上有硅(SOI)的半导体基底,有助于降低多重栅极晶体管所消耗的功率及相关有害的电气效应。
本发明是利用增加晶体管上闸沟道的数量,并将此等闸沟道并联以形成一共构的多重栅极晶体管,此等多重栅极晶体管可同时开启更多的闸沟道,借此纾解电流的压力,以提供通过晶体管的较大电子流量,并改善驱动电流。而借由本发明的多重栅极晶体管可解决前述尺寸缩小所衍生的问题,并提升半导体组件的效能。
附图说明
图1A至图1I为一系列剖面图,用以说明本发明一较佳实施例中所制作多重栅极的结构及其制造方法。
图2A至图2F为一系列俯视图,用以说明对应于剖面图1a至图1k中的相对俯视情形。
符号说明:
100~半导体基底
102~绝缘层
102a~绝缘台地
104、104a、104b~硅层
106、106a~氧化层
108、108a~掩模层
110~光阻层
112~凹处
114~介电层
116~导电层
114a~栅极介电层
116a~栅极导电层
118~光阻图案
120~轻掺杂离子植入
122~轻掺杂源极/漏极区
124~间隔物
126~离子植入
128~源极/漏极区
130~金属硅化物层
HM~硬掩模
G~多重栅极
具体实施方式
本发明将配合剖面图1A至图1I作说明本发明的多重栅极结构的制作流程,并配合俯视图2A至图2F以辅助说明其俯视情形。
首先如图1A所示,其显示本发明的起始步骤,在该图中,首先提供一基底,例如为一绝缘层上有半导体层的半导体基底,其来源可为绝缘层上有硅(silicon on insulator;SOI)或绝缘层上有硅锗材料(SiGe)的半导体基底100。于此半导体基底100上具有一绝缘层102以及一半导体层104,而此绝缘层的材质例如为二氧化硅,其厚度介于10~10000埃,而半导体层104的材质可为硅或硅锗材料,其厚度介于5~5000埃,在此则以一半导体材料的硅层104表示,以说明本发明的实施例。
接着于此硅层104上依序形成一氧化层106以及一掩模层108,形成此氧化层106的方法例如为热氧化法(thermal oxidation),其材质例如为二氧化硅(SiO2),而形成掩模层108的方法例如为化学气相沉积法(CVD),其材质例如为氮化硅材料(Si3N4)。接着涂布一光阻材料(PR)于上述掩模层108上,并经由一微影及显影程序以形成多个图案化的光阻层110于掩模层108上。此时,图1A中剖面结构是对应于如俯视图2A中A~A’切线内的剖面情形,而此时的俯视情形则如图2A中所示,于绝缘层102上(未显示)为掩模层108所覆盖且具有多个图案化的光阻层110于掩模层108上,而此等图案化的光阻层110则沿图2A中平行于y轴的第一方向大体平行地排列。
接着,请参照图1B,沿着上述图案化的光阻层110,分别蚀刻掩模层108及氧化层106,以分别形成图案化的掩模层108a及氧化层106a,以构成多个硬掩模HM,并于去除光阻层110后,再以此图案化的硬掩模HM作为蚀刻硬掩模,接着于硅层104上定义出多个图案化硅层104a,并蚀刻停止于绝缘层102上。此时,图1B中的剖面结构是对应于俯视图2B内A~A’切线中的剖面情形,其俯视结构如图2B中所示,于绝缘层102上显现出多个图案化的掩模层108a及其间所露出的部分绝缘层102,其中,于此等图案化的掩模层108a及其下方的氧化层106a与硅层104a亦沿先前光阻层110所定义方向,大体平行地于图2B中y轴的第一方向排列。
请参照图1C,接着蚀刻去除此等硬掩模HM(即掩模层108a与氧化层106a),以留下多个硅层104a。接着,更进行一圆滑化程序以圆滑化硅层104a的上部边角,上述圆滑化程序例如为(a)于制程温度介于200~1000℃的氢气气氛下单一步骤的高温氢气热退火程序(high temperature H2annealing)或为(b)利用一热氧化程序于此等硅层104a表面形成一薄氧化层后再配合一蚀刻程序去除表面的薄氧化层,以达到圆滑化其上部边角功效的两步骤程序。经由上述圆滑化程序所形成的多个上部边角圆滑化且具有鳍型外观(fin shape)的硅层104b后,接着进行一蚀刻程序以蚀刻绝缘层102,于绝缘层102内蚀刻出多个凹处(recess)112并同时形成多个突悬(overhang)的绝缘台地102a一体成形于绝缘层102上以支撑其上的多个硅层104b,且硅层104b的底面大于与绝缘台地102a接触的接触面而露出部分未接触绝缘台地102a的硅层104b底面。上述的绝缘台地102a距绝缘层102约5~500埃的深度,而此蚀刻程序则例如为一湿蚀刻程序。
请参照图1D,接着形成一保形性的介电层114覆盖于绝缘层102、绝缘台地102a及硅层104b表面,其中介电层114并覆盖于硅层104b露出于绝缘台地102a的底面部分,介电层114的形成方法例如为溅镀法、热氧化法或化学气相沉积法(CVD),其中较佳方法为衍生自化学气相沉积法的原子层化学气相沉积法(ALCVD)或热氧化法,其厚度约介于5~50埃。而介电层114的材质可选自一般常见的介电材料中二氧化硅(silicondioxide)或氮氧化硅(oxynitride)材料,亦可自相对电容率(relativepermittivity)大于5的高介电常数材料(high k dielectric)如氧化锆(ZrO2)、氧化铪(HfO2)、五氧化二钽(Ta2O5)、氧化钛(TiO2)以及氧化铝(Al2O3)等中选用。值得注意地,在此若采用热氧化法以形成此介电层114,则此保形性的介电层将仅形成于硅层104b的周围,而与图1D中的图示略有出入,在此图1D中的介电层114则以采用化学气相沉积法(CVD)所形成的保形性介电层114表示。
接着形成一毯覆性导电层116覆盖于介电层114上及一栅极的光阻图案118于导电层116上,导电层116的材质例如为多晶硅(polysilicon)、多晶硅锗(poly-SiGe)或金属,其形成方法例如为等离子体加强型化学气相沉积法(PECVD)或溅镀法,其厚度约高于硅层104b表面500~2000埃。此时,于图1D中的剖面结构是对应于俯视图图2C内A~A’切线中的剖面情形,其俯视结构则如图2C中所示,为导电层116所覆盖而仅显现出位于导电层116上的沿一第二方向延伸的一栅极的光阻图案118,此第二方向大体正交于此等硅层104b所排列的第一方向。
接着,请参照图1E,沿着此栅极的光阻图案118分别定义其下的导电层116与介电层114以分别形成一栅极导电层116a与一栅极介电层114a,并去除未为光阻图案118所覆盖区域内的导电层116与介电层114材料后,再行去除此光阻图案118,由上述部分覆盖于此等硅层104b上的栅极导电层116a与栅极介电层114a以构成一多重栅极G,此多重栅极G在此以图1E中一横跨于三独立的硅层104b的三栅极结构表示,实际多重栅极G所跨越的硅层的数量则可依照组件需求而作改变,而不在此加以限定其数量。
因整体结构关系,在此更采用视角正交于图1E的剖面图1F以作说明。接着进行一斜角度的轻掺杂离子植入120,利用适当的离子源植入于多重栅极G两侧的硅层104b表面,并经由一快速热回火程序以形成轻掺杂源极/漏极区122于硅层104b内及多重栅极G下方部分的硅层104b内,以作为防止短沟道效应(short channel effects;SCE)之用,而上述轻掺杂源极/漏极区122的形成方法亦可采用如等离子体浸入式离子植入法(plasma immersion ion implantation)完成。
此时,于图1E中的剖面结构是对应于俯视图2D内A~A’切线中的剖面情形,其俯视结构如图2D中所示,显现出一多重栅极G沿图2D中x方向的第二方向延伸,而于图1F中的剖面结构是对应于俯视图2D内B~B’切线中的剖面情形,借由先前的轻掺杂离子植入120及一快速热回火程序,于此多重栅极G两侧的多个硅层104b内形成了轻掺杂源极/漏极区122。
请参阅图1G,采用视角正交于多重栅极G的剖面图以作说明,接着依照沉积-回蚀刻的方式,在多重栅极G的两侧壁形成一间隔物124,以作为栅极导电层116a的绝缘侧壁,一般为二氧化硅层,此外,间隔物112亦可为氮化硅(Si3N4)层或氮氧化硅层(Oxynitride;SiOxNy)。
随后,对多重栅极G两侧的硅层104b进行高浓度的离子植入126,即重掺杂,以更形成多个源极/漏极区128于多重栅极G两侧的硅层104b内,并连接于多重栅极G下方的硅层104b内的多个轻掺杂源极/漏极区122,以构成一多重栅极晶体管,而位于多重栅极G下方介于多个源极/漏极区128间的硅层104b,即为此多重栅极的闸沟道(gate channel)。此时,图1G中的剖面结构是对应于俯视图2E内沿B~B’切线内的剖面情形,而此时的俯视结构则如图2E中所示,仅显现出多重栅极G(栅极导电层116a)与其两侧之间隔物124以及多个位于多重栅极G两侧硅104b层内的源极/漏极区128及绝缘层102。而于图2E中A~A’切线内的剖面结构则同于图1E内的剖面结构,故不在于此另行图示。
请参照俯视图2F,当先前制程所选用的栅极导电层116a材质为多晶硅(polysilicon)时,在此可更进行一自对准金属硅化物制程(self-aligned sicilide)以于栅极导电层116a与源极/漏极区128的表面上形成金属硅化物层(salicide)130,以降低栅极导电层116a与此等源极/漏极区128的阻值(resistance),而上述金属硅化物层材质则例如为硅化钴(CoSi2)、硅化镍(NiSi)等耐火金属的硅化物。
而对应于俯视图2F中A~A’及B~B’切线内的剖面结构则分别如图1H及图1I中所示,原先表面上的硅材料部分形成了自对准金属硅化物层130。
本发明的多重栅极G内多个为栅极导电层116a与门极介电层104b所覆盖且环绕的多个闸沟道(硅层104b),于依实际的组件设计定义出实际的多个源极及漏极后(各位于多重栅极G的同侧),配合适当的接触结构与此等漏极以及多重栅极G接触后,即可借由MOSFET的操作原理,借由多重栅极G的运作同时开启或关闭此等闸沟道,以提供适当的驱动电流,并利用本发明多重栅极G的环绕结构,以达成对于此等闸沟道良好的控制效果。
Claims (42)
1.一种多重栅极结构,其特征在于所述多重栅极结构包括:
多个鳍型半导体层,沿一第一方向平行地排列,且由多个位于一绝缘层上的绝缘台地所支撑,其中该鳍型半导体层的底面大于与该绝缘台地的接触面;以及
一栅极导电层,沿一第二方向延伸且覆盖于该鳍型半导体层的部分表面上,且于该栅极导电层与其所覆盖的该鳍型半导体层之间更设置有一栅极介电层,其中该栅极介电层更包覆于该栅极导电层所覆盖部分表面内的该鳍型半导体层的底面。
2.根据权利要求1所述的多重栅极结构,其特征在于:该绝缘层是位于一半导体基底上。
3.根据权利要求1所述的多重栅极结构,其特征在于:该第一方向正交于该第二方向。
4.根据权利要求1所述的多重栅极结构,其特征在于:该鳍型半导体层具有圆滑化的上部边角。
5.根据权利要求1所述的多重栅极结构,其特征在于:更包括多个源极/漏极区,位于该多重栅极结构两侧未为该栅极导电层所覆盖的该鳍型半导体层内,以构成一具有多重栅极的多重栅极晶体管。
6.根据权利要求5所述的多重栅极结构,其特征在于:更包括多个轻掺杂源极/漏极区连接于该源极/漏极区,其中该轻掺杂源极/漏极区是位于该源极/漏极区间的该鳍型半导体层内。
7.根据权利要求1所述的多重栅极结构,其特征在于:于该栅极导电层两侧更包括一绝缘侧壁。
8.根据权利要求6所述的多重栅极结构,其特征在于:于该绝缘侧壁材质为氮化硅或二氧化硅。
9.根据权利要求1所述的多重栅极结构,其特征在于:该鳍型半导体层材质为硅或硅锗材料。
10.根据权利要求1所述的多重栅极结构,其特征在于:该栅极介电层材质为二氧化硅或氮氧化硅材质。
11.根据权利要求1所述的多重栅极结构,其特征在于:该栅极介电层的厚度介于5~50埃。
12.根据权利要求1所述的多重栅极结构,其特征在于:该栅极介电层材质为相对电容率大于5的材质。
13.根据权利要求12所述的多重栅极结构,其特征在于:该相对电容率大于5的材质为五氧化二钽、氧化铪、氧化锆、氧化钛或氧化铝。
14.根据权利要求1所述的多重栅极结构,其特征在于:该栅极导电层材质为多晶硅、多晶硅锗或金属。
15.根据权利要求1所述的多重栅极结构,其特征在于:该绝缘台地是一体成形于该绝缘层上。
16.根据权利要求15所述的多重栅极结构,其特征在于:该绝缘台地与该绝缘层的材质为二氧化硅。
17.根据权利要求1所述的多重栅极结构,其特征在于:于该栅极导电层上更包括一金属硅化物层。
18.根据权利要求5所述的多重栅极结构,其特征在于:位于该多重栅极结构两侧未为该栅极导电层所覆盖的该鳍型半导体层内的该源极/漏极区表面上更包括一金属硅化物层。
19.根据权利要求17或18所述的多重栅极结构,其特征在于:该金属硅化物层材质为硅化钴或硅化镍。
20.一种多重栅极结构的制造方法,包括下列步骤:
提供一绝缘层上有半导体层的半导体基底;
定义该半导体层以于该绝缘层上形成多个鳍型半导体层,其中该鳍型半导体层沿一第一方向平行地排列;
蚀刻该绝缘层,以于该绝缘层上形成多个突悬的绝缘台地以支撑该鳍型半导体层,其中该鳍型半导体层的底面大于与该绝缘台地的接触面;
形成一保形性的介电层于该鳍型半导体层表面,其中该介电层并覆盖于该鳍型半导体层未接触该绝缘台地的该底面;
形成一导电层覆盖于该介电层上;以及
分别定义该导电层与该介电层以分别形成一栅极导电层与一栅极介电层,其中该栅极导电层与该栅极介电层是沿一第二方向延伸且覆盖于该鳍型半导体层的部分表面上,以构成一多重栅极结构。
21.根据权利要求20所述的多重栅极的制造方法,其中该介电层更覆盖于该绝缘层及该绝缘层台地表面。
22.根据权利要求20所述的多重栅极的制造方法,其中于蚀刻该绝缘层前,更包括一圆滑化程序,以圆滑化该鳍型半导体层的上部边角。
23.根据权利要求20所述的多重栅极的制造方法,其中该第一方向正交于该第二方向。
24.根据权利要求20所述的多重栅极的制造方法,其中该半导体层材质为硅或硅锗材料。
25.根据权利要求20所述的多重栅极的制造方法,其中该半导体基底为一绝缘层上有硅的半导体基底。
26.根据权利要求20所述的多重栅极的制造方法,其中该栅极介电层材质为二氧化硅或氮氧化硅材质。
27.根据权利要求20所述的多重栅极的制造方法,其中该栅极介电层的厚度介于5~50埃。
28.根据权利要求20所述的多重栅极的制造方法,其中该栅极介电层材质为相对电容率大于5的材质。
29.根据权利要求28所述的多重栅极的制造方法,其中该相对电容率大于5的材质为五氧化二钽、氧化铪、氧化锆、氧化钛或氧化铝。
30.根据权利要求20所述的多重栅极的制造方法,其中该栅极导电层材质为多晶硅、多晶硅锗或金属。
31.根据权利要求20所述的多重栅极的制造方法,其中蚀刻该绝缘层的方法为湿蚀刻法。
32.根据权利要求20所述的多重栅极的制造方法,其中形成该保形性的介电层的方法为热氧化法或原子层化学气相沉积法。
33.根据权利要求20所述的多重栅极的制造方法,其中形成该导电层的方法为等离子体加强型化学气相沉积法或溅镀法。
34.根据权利要求20所述的多重栅极的制造方法,更包括下列步骤:
形成一对轻掺杂源极/漏极区于为该多重栅极结构所覆盖的该鳍型半导体层内;
形成一绝缘侧壁于该栅极导电层的两侧;以及
形成一对源极/漏极区于该栅极介电层与该栅极导电层所覆盖的部分表面两侧的该鳍型半导体层内,以构成一具有多重栅极的多重栅极晶体管。
35.根据权利要求34所述的多重栅极的制造方法,其中该轻掺杂源极/漏极区是连接于该源极/漏极区。
36.根据权利要求34所述的多重栅极的制造方法,其中形成该轻掺杂源极/漏极区的方法为斜角度离子植入或等离子体浸入式离子植入法。
37.根据权利要求34所述的多重栅极的制造方法,其中该绝缘侧壁材质为氮化硅或二氧化硅。
38.根据权利要求34所述的多重栅极的制造方法,其中形成该源极/漏极区的方法为离子植入法。
39.根据权利要求34所述的多重栅极的制造方法,更包括下列步骤:
进行一自对准金属硅化物制程,以于该多重栅极晶体管的该源极/漏极区及该栅极导电层的表面上形成一金属硅化物层。
40.根据权利要求39所述的多重栅极的制造方法,其中该金属硅化物层材质为硅化钴或硅化镍。
41.根据权利要求22所述的多重栅极的制造方法,其中该圆滑化程序的步骤包括:
进行一高温氢气热退火程序,于200~1000℃的氢气气氛下,圆滑化该鳍型半导体层的上部边角。
42.根据权利要求22所述的多重栅极的制造方法,其中该圆滑化程序的步骤包括:
进行一热氧化程序以于该鳍型半导体层表面形成薄氧化层;以及
进行一蚀刻程序去除该薄氧化层,以圆滑化该鳍半导体层的上部边角。
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US10/314,249 US7728360B2 (en) | 2002-12-06 | 2002-12-06 | Multiple-gate transistor structure |
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