CN1251317C - 多栅极晶体管的结构及其制造方法 - Google Patents
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Abstract
本发明提供一种多栅极晶体管的结构及其制造方法，此结构包括一垂直半导体鳍状体、一栅极介电层、一栅极电极与一源极与一漏极。半导体鳍状体位于一衬底上方，衬底包括覆盖于一蚀刻终止层上方的一第一绝缘层，第一绝缘层在半导体鳍状体底部形成一底切，栅极介电层位于半导体鳍状体表面，栅极电极位于栅极介电层表面，而源极与漏极分别座落于栅极电极两侧，并位于半导体鳍状体中。
Description
技术领域
本发明涉及一种栅极晶体管的结构及其制造方法，特别涉及一种多栅极(multiple-gate)晶体管的结构及其制造方法，此结构对于晶体管的开或关状态具有更佳的控制能力，还能抑制短沟道效应(short channel effect)。
背景技术
数十年来金氧半场效应晶体管(metal-oxide-semiconductor field effecttransistor，MOSFET)不断向缩小尺寸的趋势发展，这是为了增加速度、提高组件集成度与降低集成电路的成本。当栅极宽度不断缩短时，意味着源极与漏极对于信道(channel)的电位所造成的影响程度渐渐增加，因此，当栅极宽度缩短至某一程度以下时，栅极上所施加的电压实质上已无法控制信道的开或关状态，这种因为缩短栅极宽度所衍生的问题就是“短沟道效应”。传统上用来解决短沟道效应的方式包括增加半导体衬底本体的掺杂浓度、减少栅极氧化层厚度与使用浅源/漏极接合。然而，当栅极宽度缩短至50nm以下时，上述方式已渐渐难以抑制短沟道效应，渐渐取而代之的是形成多栅极的晶体管结构，例如双栅极或三栅极的晶体管结构，多栅极的晶体管结构可改善栅极与信道间的电容耦合效果、增加栅极对信道电位的控制能力、抑制短沟道效应与使晶体管尺寸往不断缩小趋势发展。
请同时参照图1A、图1B，图1A为现有技术的双栅极晶体管结构的上视图，图1B为沿图1A中1B-1B剖面线的剖面结构示意图。现有双栅极晶体管是先提供表面具有一绝缘层11的硅衬底10，然后以蚀刻遮罩14定义并形成此半导体鳍状体13，再在半导体鳍状体13侧壁形成栅极介电层12，最后，在栅极介电层12表面形成栅极电极15。此结构是在半导体鳍状体13两对向侧壁处形成两栅极，因此为一双栅极晶体管。
请同时参照图2A、图2B，图2A为现有技术的三栅极晶体管结构的上视图，图2B为沿图2A中2B-2B剖面线的剖面结构示意图。现有三栅极晶体管是先提供在表面具有一绝缘层11的硅衬底10，然后以蚀刻遮罩(未显示于图中)定义并形成此半导体鳍状体13，去除蚀刻遮罩后，再在半导体鳍状体13侧壁形成栅极介电层12，最后，在栅极介电层12表面形成栅极电极15。此结构是在半导体鳍状体13顶部表面与两对向侧壁处形成有三个栅极，因此为一三栅极晶体管。对于晶体管的开或关状态，因为三栅极晶体管比双栅极晶体管多形成一栅极，因此三栅极晶体管比双栅极晶体管有更佳的控制能力，还能抑制短沟道效应，然而，无论是双栅极晶体管还是三栅极晶体管的结构，对于控制晶体管的开或关状态而言，仍有改良空间。
发明内容
为改进现有技术的缺陷，本发明的目的是提供一种双栅极晶体管的结构及其制造方法，此结构对于晶体管的开或关状态具有更佳的控制能力。
本发明的另一目的就是提供一种三栅极晶体管的结构及其制造方法，此结构对于晶体管的开或关状态具有更佳的控制能力。
根据上述目的，本发明一方面提供一种多栅极晶体管的制造方法，此制造方法先形成一半导体层于一绝缘堆栈层上方，绝缘堆栈层包括覆盖于一蚀刻终止层上方的一第一绝缘层，然后图案化半导体层，借以形成一半导体鳍状体，接着形成一底切于半导体鳍状体底部的第一绝缘层，再形成一栅极介电层于半导体鳍状体表面，沉积一栅极材料层于栅极介电层表面，图案化栅极材料层，借以形成一栅极电极而跨接于半导体鳍状体侧壁与顶部表面，最后，形成一源极与一漏极于半导体鳍状体中。
本发明另一方面提供一种多栅极晶体管的结构，此结构包括一垂直半导体鳍状体、一栅极介电层、一栅极电极与一源极与一漏极。半导体鳍状体位于一衬底上方，衬底包括覆盖于一蚀刻终止层上方的一第一绝缘层，第一绝缘层在半导体鳍状体底部形成一底切，栅极介电层位于半导体鳍状体表面，栅极电极位于栅极介电层表面，而源极与漏极分别座落于栅极电极两侧，并位于半导体鳍状体中。
本发明提供的多栅极晶体管的结构，对于晶体管的开或关状态具有更佳的控制能力，还能抑制短沟道效应。
附图简要说明
下面结合附图对本发明的具体实施方式作进一步详细的描述。
附图中，
图1A为现有技术的双栅极晶体管结构的上视图；
图1B为沿图1A中1B-1B剖面线的剖面结构示意图；
图2A为现有技术的三栅极晶体管结构的上视图；
图2B为沿图2A中2B-2B剖面线的剖面结构示意图；
图3为本发明的三栅极晶体管的立体结构示意图；
图4A～4C为本发明制作三栅极晶体管的剖面结构流程示意图；
图5A～5E为本发明另一实施例制作三栅极晶体管的剖面结构流程示意图；
图6为本发明的三栅极晶体管的上视图(未形成导体层)；
图7为本发明另一实施例制作三栅极晶体管的过程中，在半导体鳍状体形成圆滑的顶部顶点的剖面结构示意图；
图8为本发明的三栅极晶体管的立体结构示意图(尚未形成间隙壁与源极、漏极)；
图9为沿图8中D-D剖面线的剖面结构示意图；
图10A为沿图6中B-B剖面线的剖面结构示意图；以及
图10B为沿图6中C-C剖面线的剖面结构示意图。
具体实施方式
由于现有技术的双栅极晶体管(图1B)或三栅极晶体管(图2B)的结构仍有改良空间，因此，本发明提供一种多栅极晶体管的结构，对于晶体管的开或关状态具有更佳的控制能力，还能抑制短沟道效应。
以下以本发明三栅极晶体管为例，说明本发明对于现有技术的双栅极晶体管或三栅极晶体管改良的结构，请参照图3，其为本发明的三栅极晶体管的立体结构示意图，三栅极晶体管的结构包括一垂直半导体鳍状体33、一栅极介电层32、一栅极电极35与一源极361与一漏极362。半导体鳍状体33位于一衬底30上方，衬底30在表面具有一绝缘层31，绝缘层31在半导体鳍状体33底部形成一底切37，栅极介电层32位于半导体鳍状体33表面，栅极电极35位于栅极介电层32表面，而源极361与漏极362分别座落于栅极电极35两侧，并位于半导体鳍状体33中。由于结构上形成底切37，使得此改良的三栅极晶体管，也称为Omega-场效应晶体管(Ω-FET)，近似于”E.Leobandung etal.，“Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effecttransistors with a significant reduction of short channel effects，”J.Vacuum Scienceand Technology B，vol.15，no.6，pp.2791-2794”中所提出的包覆栅极晶体管(Gate-All-Around)的结构，实际上，形成底切时的横蚀量越大造成此Ω-场效应晶体管的结构越近似于包覆栅极晶体管(Gate-All-Around)，因此，对于晶体管的开或关状态具有更佳的控制能力，另外，制造此改良的三栅极晶体管使用了与现有的三栅极晶体管相近的工艺。
请参照图4A～4C，为本发明制作三栅极晶体管的剖面结构流程示意图。首先，如图4A所示，形成一半导体层鳍状体42于一衬底40上方，衬底表面具有一绝缘层41。
接着，图4B中，借由蚀刻形成一底切43于半导体鳍状体42底部的绝缘层41。例如，当绝缘层41的材料为氧化硅时，可以用稀释氢氟酸(水∶浓氢氟酸的量约为25∶1)在摄氏25℃下进行湿蚀刻60秒，以达到约100的下蚀量R。由于湿蚀刻有侧向蚀刻，因此得以在半导体鳍状体42底部的绝缘层41形成底切43。然而，工艺上在控制湿蚀刻时间有一定困难，致使片与片、批与批之间的下蚀量R有所差异。
最后，图4C中，形成一栅极介电层44、一栅极电极45于半导体鳍状体42表面，并形成一源极与一漏极(未显示于图中)于半导体鳍状体42中，至此则完成三栅极晶体管的制作。
如前所述，下蚀量R并不易控制，因此，本发明另外提供一种可容易控制下蚀量R的工艺。请参照图5A～5E，为本发明另一实施例制作三栅极晶体管的剖面结构流程示意图，其为沿图6中A-A剖面线的剖面结构。首先，如图5A所示，提供一衬底50，并形成一半导体层52于一绝缘堆栈层上方，其中半导体层52之材料选自硅或者锗。衬底50表面具有一绝缘堆栈层51，绝缘堆栈层51包括第一绝缘层513、蚀刻终止层512与第二绝缘层511，其中第一绝缘层513覆盖于蚀刻终止层512上方，蚀刻终止层512覆盖于第二绝缘层511上方。第一绝缘层513的材料可以为任何一第一介电材料，例如氧化硅，第一绝缘层513的厚度介于20～1000之间为较佳。第二绝缘层511的材料可以为任何相同于第一介电材料的材料，第二绝缘层511的厚度介于20～1000之间为较佳。蚀刻终止层512的材料可以为任何蚀刻速率低于第一介电材料的一第二介电材料，蚀刻终止层512的厚度介于20～1000之间为较佳。如果第一介电材料为氧化硅而第二介电材料为氮化硅，则可以用稀释氢氟酸湿蚀刻第一介电材料。
图5B中，再以蚀刻遮罩53定义并形成一半导体鳍状体54，蚀刻遮罩53的材料可以为任何作为蚀刻罩幕的材料，例如光致抗蚀剂、氧化硅、氮化硅，蚀刻遮罩53的较佳材料为氧化硅。半导体鳍状体54的材料选自硅或者锗。根据本发明，可以移除蚀刻遮罩53或不移除蚀刻遮罩53，若移除蚀刻遮罩53则形成三栅极晶体管，若不移除蚀刻遮罩53则形成双栅极晶体管。根据本发明，形成半导体鳍状体54时，还可选择性的包括平滑化半导体鳍状体54表面的步骤，平滑化半导体鳍状体54可使得半导体鳍状体54中载子达到良好移动能力，平滑化可以先经由一牺牲式氧化步骤，然后再经一侧壁处理步骤(例如在1000℃的氢气环境中加热)。若蚀刻遮罩53的材料为氧化硅，则可在平滑化之前或之后移除蚀刻遮罩53，之后移除则半导体鳍状体54最后会具有尖角的顶部顶点，之前移除则半导体鳍状体54最后会具有圆滑的顶部顶点56(如图7所示)。若蚀刻遮罩53的材料为光致抗蚀剂，则光致抗蚀剂必须在平滑化前移除，借以避免平滑化过程中的高温造成破坏。
图5C中，移除蚀刻遮罩53。
图5D中，借由蚀刻形成一底切55于半导体鳍状体54底部的第一绝缘层513。其中一种方式，是使用稀释氢氟酸(水∶浓氢氟酸的量约为25∶1)在摄氏25℃下进行湿蚀刻30～600秒，以达到约50～1000的下蚀量R，其中湿蚀刻时间影响横蚀量E。另一种方式，是先进行干蚀刻，再进行湿蚀刻。干蚀刻为一非等向性蚀刻，可使用含氟的等离子体气体进行干蚀刻，而停止于蚀刻终止层512，之后的湿蚀刻过程仅有侧向蚀刻，湿蚀刻时间影响横蚀量E，较佳的横蚀量E介于20～500之间。若在平滑化之前移除蚀刻遮罩53，则半导体鳍状体54最后会具有圆滑的顶部顶点56(如图7所示)。
图5E中，形成一栅极介电层59于半导体鳍状体54表面，可借由热氧化、化学气相沉积或溅镀方式形成此栅极介电层59。一般来说，栅极介电层59位于半导体鳍状体54顶部表面的厚度比位于半导体鳍状体54侧壁的厚度薄，栅极介电层59位于半导体鳍状体54顶部表面的厚度低于20。栅极介电层59的材料可以为传统材料，例如氧化硅或氮氧化硅，其厚度介于3～100之间，较佳者为小于10。栅极介电层59的材料也可以为高介电常数材料(介电常数高于5)，例如氧化镧、氧化铝、氧化铪、氮氧化铪与氧化锆，其厚度介于3～100之间。
接着，沉积一栅极材料层于栅极介电层59表面，栅极材料层的材料可以为多晶硅、多晶硅化锗、回火金属(例如钼、钨)、化合物(例如氮化钛)或其它导电材料。接着，图案化栅极材料层，借以形成一栅极电极60而跨接于半导体鳍状体54侧壁与顶部表面。栅极材料层较佳的材料为多晶硅，栅极介电层59的材料为氮氧化硅，可使用含氯与溴的等离子体气体进行干蚀刻，而停止于栅极介电层59。然后，再移除未被栅极电极60覆盖住的栅极介电层59，至此，所形成的结构(尚未形成间隙壁与源极、漏极)的立体示意图如图8所示。
之后的工艺，请参照图9，其为沿图8中D-D剖面线的剖面结构示意图。再经由离子植入、等离子体含浸离子植入(plasma immersion ion implantation，PIII)或其它传统方式形成轻掺杂区域(lightly-doped drain)61。再以传统方式在栅极电极60侧壁形成间隙壁58，例如先沉积一间隙壁材料层，然后回蚀刻此间隙壁材料层，间隙壁材料层的材料可以为介电材料，例如氮化硅或二氧化硅，较佳的间隙壁材料层的材料为氮化硅与氧化硅的复合层。然后，经由离子植入、等离子体含浸离子植入、气体或固体源扩散或其它传统方式形成一源极621与一漏极622于半导体鳍状体54。任何因离子植入而造成的晶格破坏可在此时再经一加热步骤修复缺陷，至此，如图6所示，其为本发明的三栅极晶体管的上视图(尚未形成导体层)。最后，栅极电极60、源极621与漏极622可再在其表面形成一导体层63，借以降低阻值，导体层63的材料可以为金属硅化物(例如硅化钛、硅化钴、硅化镍)、金属氮化物(例如氮化钛、氮化铊)、金属(例如钨、铜)或重掺杂半导体(例如n+重掺杂硅)。较佳的导体层63的材料为硅化镍，可以经由自我对准金属硅化物(self-aligned silicide，salicide)工艺形成硅化镍。如图10A、图10B所示，其分别为沿图6中B-B与C-C剖面线的剖面结构示意图，所形成的导体层63位于半导体鳍状体54侧壁与顶部表面。至此，则完成三栅极晶体管的制作。
可以理解的是，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (21)
1、一种多栅极晶体管的制造方法，其特征在于，该制造方法至少包括下列步骤：
形成一半导体层于一绝缘堆栈层上方，该绝缘堆栈层包括覆盖于一蚀刻终止层上方的一第一绝缘层；
图案化该半导体层，借以形成一半导体鳍状体；
形成一底切于该半导体鳍状体底部的该第一绝缘层；
形成一栅极介电层于该半导体鳍状体表面；
沉积一栅极材料层于该栅极介电层表面；
图案化该栅极材料层，借以形成一栅极电极而跨接于该半导体鳍状体侧壁与顶部表面；以及
形成一源极与一漏极于该半导体鳍状体中。
2、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该半导体层的材料选自硅或者锗。
3、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该第一绝缘层的材料为氧化硅，其厚度介于20～1000之间。
4、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该蚀刻终止层的材料为氮化硅，其厚度介于20～1000之间。
5、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，形成该半导体鳍状体还包括平滑化该半导体鳍状体表面的步骤，其中平滑化该半导体鳍状体表面，先进行牺牲式氧化，然后再在氢气环境中加热。
6、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，以一湿蚀刻程序形成该底切，该湿蚀刻程序蚀刻该第一绝缘层，而停止于该蚀刻终止层。
7、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，先以一干蚀刻程序，再以一湿蚀刻程序形成该底切，其中该干蚀刻程序蚀刻该第一绝缘层，而停止于该蚀刻终止层，其中以氢氟酸进行该湿蚀刻程序。
8、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，形成该底切于该半导体鳍状体下方，造成介于50～1000之间的下蚀量，而且造成介于20～500之间的横蚀量。
9、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该栅极介电层的材料选自于氧化硅、氮氧化硅与介电常数高于5的介电常数材料之一，其厚度介于3～100之间。
10、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该栅极材料层的材料选自于多晶硅或者多晶硅化锗。
11、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该源极与该漏极包括一轻掺杂区域。
12、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该源极与该漏极表面形成有一导体层，该导体层的材料选自金属、金属硅化物与金属氮化物群组之一。
13、一种多栅极晶体管的结构，其特征在于，该结构至少包括：
一垂直半导体鳍状体，位于一衬底上方，该衬底包括覆盖于一蚀刻终止层上方的一第一绝缘层，该第一绝缘层在该半导体鳍状体底部形成一底切；
一栅极介电层，位于该半导体鳍状体表面；
一栅极电极，位于该栅极介电层表面；以及
一源极与一漏极，分别座落于该栅极电极两侧，并位于该半导体鳍状体中。
14、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该半导体鳍状体的材料选自于硅或者锗。
15、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该半导体鳍状体具有圆滑的顶部顶点。
16、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该第一绝缘层的材料为氧化硅，其厚度介于20～1000之间。
17、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该蚀刻终止层的材料为氮化硅，其厚度介于20～1000之间。
18、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该栅极介电层的材料选自于氧化硅、氮氧化硅与介电常数高于5的介电常数材料群组之一，其厚度介于3～100之间。
19、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该栅极电极的材料选自于多晶硅或者多晶硅化锗。
20、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该源极与该漏极包括一轻掺杂区域。
21、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该源极与该漏极表面形成有一导体层，该导体层的材料选自于金属与金属硅化物之一。
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- 2003-07-01 TW TW092118009A patent/TW594990B/zh not_active IP Right Cessation
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| TW594990B (en) | 2004-06-21 |
| US20040198003A1 (en) | 2004-10-07 |
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