CN1713395A - 能够调整阈值电压的半导体器件及其制造方法 - Google Patents

能够调整阈值电压的半导体器件及其制造方法 Download PDF

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CN1713395A
CN1713395A CNA2005100082977A CN200510008297A CN1713395A CN 1713395 A CN1713395 A CN 1713395A CN A2005100082977 A CNA2005100082977 A CN A2005100082977A CN 200510008297 A CN200510008297 A CN 200510008297A CN 1713395 A CN1713395 A CN 1713395A
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silicon substrate
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dielectric film
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金一旭
赵俊熙
朴圣彦
安进弘
李相敦
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SK Hynix Inc
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Abstract

提供了一种具有硅衬底的半导体器件，其中有源区形成在两个器件隔离膜之间并且栅极形成在有源区的表面上。所述硅衬底具有在靠近所述器件隔离膜侧的所述有源区的表面下方的所述有源区中的横向蚀刻部分。绝缘膜形成在所述硅衬底的横向蚀刻部分上。导电电极形成在所述绝缘膜上，通过该导电电极施加外部电压以调整阈值电压。所述器件隔离膜形成在导电电极上。在所述器件隔离膜和所述导电电极之间不存在或存在一些空腔的袋状物。

Description

能够调整阈值电压的半导体器件及其制造方法
技术领域
本发明涉及一种能调整阈值电压而使器件操作最佳化的半导体器件，尤其涉及一种能够通过施加外部电压调整阈值电压的半导体器件及其制造方法，经由该方法能实现部分的SOI结构。
背景技术
一般所知，半导体器件中的MOSFET，敏锐地响应阈值电压(Vt)而操作。在半导体制造工艺领域中，为获得MOSFET的最佳阈值电压值，杂质注入的优化和/或热处理等相关课题已变成重要课题。
当半导体器件由于高集成度而缩小时，通常需要极大量的杂质注入，以调整阈值电压至适当值。由于不希望的杂质扩散，这种用于调整阈值电压的过量的杂质注入不可避免地导致器件刷新特性的变差以及器件可靠性的下降。因此，过量注入杂质以调整阈值电压的传统技术不能产生令人满意的结果，尤其是对于高集成度的器件。
另一种传统方法将反偏压施加到器件的本体以调整阈值电压。然而，这种传统技术也有其限制，因为当半导体器件的尺寸变小，反偏压对于本体的影响将愈来愈小。尤其是，当沟道和本体区域被多栅极结构(例如：双栅极、三栅极或环绕栅极结构)中的栅极围绕时，反偏压对于本体将没有影响。因此，不可能使用反偏压来调整阈值电压。
总之，通过使用杂质注入的传统技术或者热处理或其他传统工艺，很难在高集成度的半导体器件中获得最佳的阈值电压，这在确保与半导体器件的高集成度相符的最佳器件特性方面存在挑战。
发明内容
因此，为了解决现有技术中出现的上述问题而提出本发明，本发明的一个目的是提供一种半导体器件及其制造方法，其中能够获得适当的阈值电压。
本发明的另一目的是提供一种半导体器件及其制造方法，其中通过调整适当的阈值电压能够确保预期的器件特性。
为了达到上述目的，根据本发明的一个方面，提供了一种半导体器件，其包括：具有用于界定有源区的器件隔离膜的硅衬底；形成于硅衬底的有源区上的栅极；以及形成于栅极两侧的衬底表面上的结区，其中硅衬底包括与有源区内的器件隔离膜邻接的空白空间(vacant space)，该空白空间的表面形成有导电电极，用于调整衬底本体区电势的电压从外部施加到该导电电极，同时在本体区衬底和导电电极之间插入绝缘膜。
根据本发明的另一方面，提供了一种制造半导体器件的方法，该方法包括以下步骤：在具有器件隔离区和有源区的硅衬底上形成垫氧化膜和垫氮化物膜；蚀刻所述垫氧化膜、垫氮化物膜及硅衬底，以在器件隔离区中形成沟槽；在包括被蚀刻的垫氧化膜和垫氮化物膜的沟槽侧壁上形成绝缘膜间隙壁；从沟槽暴露的底表面的硅衬底部分朝向有源区进行横向蚀刻，从而在硅衬底的有源区内形成空白空间；去除绝缘膜间隙壁；通过在空白空间的表面上插入绝缘膜而形成导电电极；用氧化膜填满沟槽以形成器件隔离膜；在硅衬底上形成栅极；以及在栅极两侧的衬底表面上形成结区。
优选地，根据本发明的半导体器件的制造方法还包括以下步骤：在形成绝缘膜间隙壁的步骤之后以及在于硅衬底的有源区内形成空白空间的步骤之前，在800至1000℃的温度下、在氢气氛中进行热处理。
另外，优选地，根据本发明的制造方法还包括以下步骤：在于硅衬底的有源区内形成空白空间的步骤之后以及在去除绝缘膜间隙壁的步骤之前，在暴露的沟槽底表面的衬底表面上进行场停止注入(field stopimplantation)。
附图说明
通过以下结合附图的详细描述，本发明的以上及其他目的、特征和优点将变得更加明显，附图中：
图1是根据本发明优选实施例的半导体器件的横截面图；
图2A至2H是用于解释根据本发明优选实施例制造半导体器件的方法的各个工序的横截面图。
具体实施方式
以下，将参照附图说明根据本发明的半导体器件及其制造方法的优选实施例。在以下描述和附图中，相同的附图标记用来表示相同或相似的部件，因此对于相同或相似部件的重复描述将予以省略。
在本发明的一实施例中，提供了一种表现出绝缘体上覆硅(Silicon onInsulator，SOI)特性的MOSFET，其中通过在以前的工艺中淀积其上能够施加外部电压的电极材料以调整阈值电压，来获得适当的阈值电压。本发明的这种技术能够使本体区的电势通过施加到所淀积的电极材料上的外部电压而被直接调整。
更具体而言，在沟槽蚀刻工艺之后，在特定的横向方向执行横向蚀刻工艺，以形成部分的SOI结构。在横向蚀刻表面上，形成绝缘膜和导电电极。电压从外部施加到导电电极上以调整本体区的电势，由此调整MOSFET的阈值电压。
以下将详细说明本发明的这些及其他方面。
如图1所示，该图为根据本发明优选实施例形成的半导体器件的横截面图，半导体器件包括具有用于界定有源区的器件隔离膜13的硅衬底1，形成于硅衬底1上的栅极20，以及形成于栅极20两侧的衬底表面上的结区(未示出)。所述有源区、即硅衬底1的本体区配置有在有源区内的与器件隔离膜13邻接的空白空间8。该空白空间8的表面形成有导电电极11a，用于调整衬底本体区电势的电压从外部施加到该导电电极，同时在衬底本体区和导电电极11a之间插入绝缘膜10。
因为导电电极11a与本体区相邻，同时由绝缘膜10分隔，所以能够很容易地调整本体区的电势以及阈值电压。因此，本发明的半导体器件能够以高速工作，这是集成于SOI晶片中的半导体器件的典型特性，并且能够很容易地调整MOSFET的阈值电压。
现在，将参照图2A至2H详细说明根据本发明优选实施例的制造半导体器件的方法。
参照图2A，通过例如传统STI(浅沟槽隔离)工艺在硅衬底1上形成垫氧化膜2和垫氮化物膜3。在垫氮化物膜3上形成有机抗反射膜4。之后，通过例如光致抗蚀剂膜的涂敷、曝光及显影工艺的相继应用，在抗反射膜4上形成暴露器件隔离区的光致抗蚀剂膜图案5。在形成感光膜时可使用聚合物，如COMA(Cycloolefin-Maleic Anhydride)(环烯-马来酐)或丙烯酸盐系列(acrylate series)。
在器件隔离区中的抗反射膜4的暴露部分中，使用光致抗蚀剂膜图案5作为蚀刻阻挡，蚀刻在其下的垫氧化膜和垫氮化物膜以及硅衬底1，以形成如图2B所示的沟槽6。接着，用于间隙壁的绝缘膜7被淀积在具有沟槽6的所得衬底上。
当形成沟槽6时，可使用CF4/CHF3/O2的气体混合物，蚀刻垫氧化膜2和氮化物膜3。CF4气、CHF3气和O2气的流速分别设定为约10～100sccm、10～300sccm，以及10～70sccm。可使用Cl2/HBr的气体混合物，蚀刻硅衬底1。Cl2气和HBr气体的流速分别设定为约10～100sccm。此外，不同器件中的沟槽6可具有不同的深度，因为沟槽深度在很大程度上依赖于器件集成度。通常，沟槽6形成为约1000至3000埃的深度，但需注意的是，本发明中沟槽深度有可能为任何值，甚至不在以上给出的范围内。
通过氧化膜或氮化物膜形成绝缘膜7(用于间隙壁)，但也可以用其他通常用于半导体制造工艺中的绝缘材料来替代。特别是，如果氮化物膜用于绝缘膜7，可以将氧化膜淀积在氮化物膜之下。
参照图2C，蚀刻绝缘膜7，从而在包括衬底1和被蚀刻的垫氧化膜2和垫氮化物膜3的暴露表面的沟槽侧壁上形成绝缘膜间隙壁7a。
以下将描述在特定横向方向蚀刻硅衬底1的后续工艺，在该工艺中绝缘膜间隙壁7a用作蚀刻阻挡。也就是说，进一步进行暴露沟槽底表面的衬底部分的开口工艺(opening process)，为本发明的制造方法中后续的干式或湿式蚀刻以及氧化工艺作准备。
在使用间隙壁7a作为蚀刻阻挡进行横向蚀刻而形成沟槽6之后，通过执行例如侧壁氧化工艺、氮化物淀积工艺、衬垫氧化工艺(liner oxidationprocess)和沟槽填充工艺来形成器件隔离膜13。
参照图2D，图2C所示的所得衬底在800至1000℃下、氢气氛中经受热处理，从而去除衬底表面上的外部杂质。之后，在特定横向方向朝向绝缘膜间隙壁7a的内侧进行横向蚀刻。使用垫氮化物膜3和绝缘膜间隙壁7a作为蚀刻阻挡，暴露本体区的硅衬底1。这样，在硅衬底1的有源区中提供了空白空间8。再参照图1，绝缘膜10以及用于调整阈值电压的导电电极11a将在空白空间8中形成。
用以提供空白空间8的横向蚀刻可经由下列工艺进行：使用等离子的干式蚀刻工艺；使用化学制品的湿式蚀刻工艺；或者使用气体混合物的干式蚀刻工艺，在该气体混合物中包括如F、Cl、Br等VIIA族元素所构成的组中的元素以及氢。
例如，使用HCl和H2的气体混合物在700至1000℃的温度下进行用于提供空白空间8的横向蚀刻，其中HCl气体和H2气体的流速分别设定为0.1～1slm和10～50slm，以调整蚀刻速度和硅衬底1的蚀刻轮廓(etchprofile)。
参照图2E，所得衬底经受场停止注入(field stop implantation)，以在沟槽底表面的衬底表面之内形成离子注入层9。离子注入层9的形成意在防止单元之间的漏电流，将电压施加到用于调整阈值电压的电极材料上会引起所述漏电流。
参照图2F，去除绝缘膜间隙壁7a，然后在所得衬底上淀积绝缘膜10(用于和后面将要形成的导电电极11a一起调整阈值电压)。绝缘膜10可以是任何绝缘膜材料，如SiO2、NO、ONO以及HfO膜，它们通常也用作栅极氧化物材料。
接着，在绝缘膜10上淀积用于施加外部电压的电极材料膜11。优选使用掺杂多晶硅作为电极材料膜11，不过，也可以使用不同于多晶硅的金属，例如铝、铜等。
参照图2G，为了去除硅衬底1的有源区周围的电极材料膜，用光致抗蚀剂膜12涂敷所得衬底。接着，回蚀刻光致抗蚀剂膜12，使得光致抗蚀剂膜12只保留在空白空间8的横向蚀刻区域。此后，使用剩余的光致抗蚀剂膜12作为蚀刻阻挡，通过干式或湿式蚀刻技术去除电极材料膜11的暴露部分。这样，形成了用以将电压从外部施加到本体区的导电电极11a。
此处，可使用Cl2/HBr的气体混合物蚀刻电极材料膜11，其中Cl2气和HBr气体的流速分别设定为约10～100sccm。也可使用乙酸、硝酸和NH4OH的溶液混合物蚀刻电极材料膜11。
虽然在本实施例中光致抗蚀剂膜12用作用于去除衬底有源区周围的电极材料膜11的蚀刻阻挡材料，但也可以使用如SOG、HTO、LTO、热氧化物(thermal oxide)和/或BPGS膜等氧化膜来代替光致抗蚀剂膜。
参照图2H，剩余的光致抗蚀剂膜12经由剥离工艺而被去除，接着进行STI工艺以形成器件隔离膜13。在用氧化膜或其他合适的材料填满沟槽以形成器件隔离膜13的工艺中，由于结构的特质，会在沟槽的横向蚀刻部分8中形成空隙(void)，然而即使存在空隙，也并不影响阈值电压的调整。
接着，在硅衬底1上形成栅极20。在此需注意的是，栅极20具有如图1和图2H所示的栅极氧化膜14、栅极导电膜15和硬掩模膜16的多层结构。栅极20还设置有栅极间隙壁17。此后，在栅极20两侧的衬底表面上形成结区(未示出)。这样，构造成MOSFET。
接着，进行一系列已知的DRAM制造工艺，从而完成半导体器件。
如以上在本发明的实施例中所述，通过在横向空白空间8中形成绝缘膜10(以及导电电极11a)，在硅衬底1内实现部分SOI结构，如图1和2H所示。通过将外部电压施加到独立的导电电极11a，能够容易地调整衬底本体区的电势。由此，能够容易地调整阈值电压以得到预期值。
因此，由于通过外部电压而无需杂质注入就可调整阈值电压，所以结区和沟道区中的电磁场减小。这显著提高了DRAM的刷新特性，并允许实现器件的高速和低电压操作。
虽然为了说明的目的描述了本发明的优选实施例，本领域技术人员应理解的是，可在不偏离所附权利要求公开的本发明的主旨和范围的前提下进行各种修改、添加和替换。

Claims (20)

1.一种半导体器件，其具有硅衬底，所述硅衬底具有在两个器件隔离膜之间的有源区和形成在所述有源区的表面上的栅极，所述半导体器件包括：
所述硅衬底，其具有在靠近所述器件隔离膜侧的所述有源区的表面下方的所述有源区中的横向蚀刻部分；
绝缘膜，其形成在所述硅衬底的所述横向蚀刻部分上；
导电电极，其形成在所述绝缘膜上，其中外部电压施加到所述导电电极以调整阈值电压；以及
所述器件隔离膜，其位于所述导电电极上，其中在所述器件隔离膜和所述导电电极之间不存在或存在一些袋状空腔。
2.如权利要求1所述的半导体器件，还包括场停止注入层，其形成在所述有源区外部所述绝缘膜下方的所述衬底中。
3.一种制造半导体器件的方法，该半导体器件具有栅极和结区，该方法包括以下步骤：
在具有器件隔离区和有源区的硅衬底上形成垫氧化膜和垫氮化物膜；
蚀刻所述垫氧化膜、所述垫氮化物膜以及所述硅衬底，以在所述器件隔离区中形成沟槽；
在包括所述被蚀刻的垫氧化膜和垫氮化物膜的沟槽侧壁上形成绝缘膜间隙壁；
使用所述垫氧化膜、所述垫氮化物膜和所述绝缘膜间隙壁作为蚀刻阻挡，横向蚀刻所述硅衬底中的所述有源区的一部分；
去除所述绝缘膜间隙壁；
在所述有源区中与所述横向蚀刻的部分邻接的表面上以及在所述隔离区中所述沟槽的表面上形成导电电极；以及
用氧化膜填充所述沟槽和所述横向蚀刻部分从而形成器件隔离膜，其中在所述器件隔离膜和所述导电电极之间不存在或存在一些袋状空腔。
4.如权利要求3所述的方法，其中使用CF4/CHF3/O2的气体混合物执行蚀刻所述垫氧化膜和所述垫氮化物膜的步骤。
5.如权利要求4所述的方法，其中所述CF4气体、CHF3气体和O2气体的流速分别为10～100sccm、10～300sccm以及10～70sccm。
6.如权利要求3所述的方法，其中使用Cl2/HBr的气体混合物执行蚀刻所述硅衬底以形成所述沟槽的步骤。
7.如权利要求6所述的方法，其中所述Cl2气体和HBr气体的流速分别为10～100sccm。
8.如权利要求3所述的方法，其中所述沟槽形成为具有1000～3000埃的深度。
9.如权利要求3所述的方法，还包括以下步骤：在形成所述绝缘膜间隙壁的步骤之后并且在横向蚀刻所述硅衬底的有源区内的部分的步骤之前，在800至1000℃的温度下、在氢气氛中进行热处理。
10.如权利要求3所述的方法，其中通过下面(1)、(2)、(3)中的任何一种工艺执行横向蚀刻所述硅衬底的有源区中的部分的步骤，(1)使用等离子的干式蚀刻工艺；(2)使用化学制品的湿式蚀刻工艺；(3)干式蚀刻工艺，其使用来自于包括F、Cl、Br的VIIA族元素和氢的组中的元素的气体混合物。
11.如权利要求3所述的方法，其中使用HCl和H2的气体混合物执行横向蚀刻所述硅衬底的有源区中的部分的步骤。
12.如权利要求10所述的方法，其中所述HCl气体和H2气体的流速分别为0.1slm和10～50slm。
13.如权利要求11所述的方法，其中在700至1000℃的温度下执行横向蚀刻所述硅衬底的有源区中的部分的步骤。
14.如权利要求3所述的方法，还包括以下步骤：在横向蚀刻所述硅衬底的有源区中的部分的步骤之后并且在去除所述绝缘膜间隙壁的步骤之前，在暴露的沟槽底表面的衬底表面上进行场停止注入。
15.如权利要求3所述的方法，其中形成所述导电电极的步骤包括下列步骤：
在包括所述垫氧化膜和所述垫氮化物膜的表面的所述隔离区中所述沟槽的表面上以及在所述有源区中所述横向蚀刻部分的表面上，形成绝缘膜；
在所述绝缘膜上形成电极材料膜；
回蚀刻形成于所述垫氧化膜和所述垫氮化物膜的表面上所述沟槽中的所述电极材料，暴露所述绝缘膜的一部分；以及
去除所述绝缘膜的暴露部分。
16.如权利要求15所述的方法，其中所述绝缘膜为SOG膜或光致抗蚀剂膜。
17.如权利要求15所述的方法，其中使用Cl2/HBr的气体混合物执行回蚀刻所述电极材料的步骤。
18.如权利要求17所述的方法，其中所述Cl2气体和HBr气体的流速分别为10～100sccm。
19.如权利要求15所述的方法，其中使用乙酸、硝酸和NH4OH的溶液混合物执行回蚀刻所述电极材料的步骤。
20.如权利要求3所述的方法，其中形成所述栅极从而提供栅极氧化膜、栅极导电膜和硬掩模膜的多层结构，所述栅极在其两个侧壁上具有栅极间隙壁。
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US20050280113A1 (en) 2005-12-22
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