CN1333462C - 层压片、用于制造半导体器件的方法和半导体器件 - Google Patents

层压片、用于制造半导体器件的方法和半导体器件 Download PDF

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Publication number
CN1333462C
CN1333462C CNB2004100552484A CN200410055248A CN1333462C CN 1333462 C CN1333462 C CN 1333462C CN B2004100552484 A CNB2004100552484 A CN B2004100552484A CN 200410055248 A CN200410055248 A CN 200410055248A CN 1333462 C CN1333462 C CN 1333462C
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layer
wafer
laminate
resin
semiconductor device
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CN1577821A (zh
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野吕弘司
赤泽光治
山本雅之
山本康彦
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Nitto Denko Corp
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Nitto Denko Corp
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    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B27/08—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
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    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/18—Layered products comprising a layer of synthetic resin characterised by the use of special additives
    • B32B27/26—Layered products comprising a layer of synthetic resin characterised by the use of special additives using curing agents
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    • B32B27/00—Layered products comprising a layer of synthetic resin
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Abstract

一种层压片，用于在研磨晶片背部的步骤中粘附到安装了凸出电极的晶片的电路侧面上，其中该层压片至少包括与电路侧面接触、由热固性树脂制成的层A，直接层压在层A上、由在40℃至80℃时具有1至300MPa的拉伸模量的热塑性树脂制成的层B，以及由在最低25℃的温度时无塑性的热塑性树脂制成的最外层C；一种用于制造半导体器件的方法，该方法包括以下步骤：研磨安装凸出电极的晶片的背部，其中层压片粘附到晶片的电路侧面上，除去层压片的层A之外的其他层，以及将晶片切割为单个芯片；以及一种可通过该方法获得的半导体器件。

Description

层压片、用于制造半导体器件的方法和半导体器件
技术领域
本发明涉及可用于半导体器件的制造的层压片，用于使用该层压片制造半导体器件的方法，以及可以通过该方法制造的半导体器件。
背景技术
随着由半导体器件的多功能性和微型化伴随的最新需求，已经实现了倒装芯片安装，其中半导体元件以面朝下的结构安装在布线电路板上。
一般，在倒装芯片安装中，在半导体元件和布线电路之间的间隙处进行树脂包封，以便保护半导体元件。利用倒装芯片安装的常规制造方法包括以下步骤：在晶片上产生图形，形成凸块，将晶片研磨至给定的厚度，将晶片切割为单个半导体元件，以及将半导体元件安装在布线电路板上和进行树脂包封。
存在的缺陷是经受研磨的薄晶片对外力具有低的机械强度。作为它的改进措施，已提出了通过先树脂包封安装凸出电极的晶片，以及此后进行晶片的背部研磨来弥补研磨之后晶片的机械强度的不足(例如，日本专利特许-公开JP2001-144123)。但是，为了形成用于在布线电路板上安装半导体器件的电极，产生了需要在对应于树脂包封层中晶片的电极位置开孔，将焊料嵌入到开孔，以及此后在孔中形成焊球的复杂步骤的问题。
此外，已提出了包括以下步骤的方法：形成粘附膜层，以便完全覆盖安装凸出电极的晶片上的电极，使用粘附膜作为凸出电极-保护层使晶片经历背部研磨，此后将晶片分为单个芯片并安装在电路板上(例如，日本专利特许-公开JP2001-144140)。在此情况下，由于粘附膜层完全覆盖凸出电极，在与电路板电连接中绝缘的粘附膜层被机械地推开，所以必须使电连接安全，由此引起连接可靠性的问题。此外，由于粘附膜层完全覆盖凸出电极，以超过填充半导体元件和电路板之间的间隙需要的量涂敷树脂，因而在安装芯片之后在半导体元件周围的宽范围中过量的树脂被压出，由此在高-密度安装中引起某些问题。
另一方面，已提出了一种方法，该方法包括以露出晶片的凸出电极侧的电极顶部的量涂敷热塑性树脂，此后将具有粘附层的带粘附到热塑性树脂上以及使晶片经历背部研磨(例如，日本专利特许-公开2000-223602)。在该提出的方法中，在背部研磨之后，剥离具有粘附层的带，将晶片分为单个芯片，以及此后用熔融的热塑性树脂将芯片安装在电路板上。在该方法中，为了均匀地涂敷热塑性树脂需要足够的活性。由于优选实施方案提出滴落在约150℃塑化的热塑性树脂，同时加热到240℃至260℃，因此由研磨之后的晶片中的热塑性树脂的剩余应力而随之产生的弯曲引起传送晶片失败的问题。
发明内容
由此，本发明的目的是提供一种可以适用于倒装芯片安装的层压片，且在树脂包封之后凸块的包装性能优良，给予晶片优良的可加工性以及提供优良的电连接可靠性，以及提供一种使用该层压片制造半导体器件的方法和可以通过该方法制造的半导体器件。
从下面描述将明白本发明的这些及其他目的。
根据本发明，提供：
(1)一种层压片，用于在研磨晶片背部的步骤中粘附到安装了凸出电极的晶片的电路侧面上，其中该层压片至少包括：
与电路测面接触、由热固性树脂制成的层A；
直接层压在层A上、由在40℃至80℃时具有1至300MPa的拉伸模量的热塑性树脂制成的层B；以及
由至少在25℃的温度时无塑性的热塑性树脂制成的最外层C；
(2)一种用于制造半导体器件的方法，包括以下步骤：研磨安装凸出电极的晶片的背部，其中上述(1)的层压片粘附到晶片的电路侧面上，除去除层压片的层A之外的其他层，以及将晶片切割为单个芯片；以及
(3)一种可通过上述(2)的方法获得的半导体器件。
附图说明
图1图示了本发明的层压片的一个例子；
图2是安装凸出电极的晶片的剖面图的一个例子；
图3是图示用于制造本发明的半导体器件的方法步骤的说明性视图的一个例子；
图4是图示用于制造本发明的半导体器件的方法步骤的说明性视图的另一个例子；
图5是图示用于制造本发明的半导体器件的方法步骤的说明性视图的又一个例子；
图6是图示用于制造本发明的半导体器件的方法步骤的说明性视图的又一个例子；
图7是图示用于制造本发明的半导体器件的方法步骤的说明性视图的又一个例子；以及
图8是图示用于制造本发明的半导体器件的方法步骤的说明性视图的又一个例子；
图1至8中使用的附图标记如下。
1指层A，2指层B，3指层C，4指晶片，5指凸出电极，6指切割带，7指单个芯片以及8指布线电路板。
具体实施方式
在研磨安装凸出电极的晶片背部的步骤中，通过将层压片粘附到晶片的电路侧面上使用本发明的层压片，其中层压片的一个显著的特点在于该层压片至少包括：
与电路侧面接触、由热塑性树脂制成的层(层A)，
直接层压在层A上、由在40℃至80℃时具有1至300MPa的拉伸模量的热塑性树脂制成的层(层B)，以及
至少包括在25℃时无塑性的热塑性树脂层的最外层(层C)。
利用倒装芯片安装的方法包括以下步骤：将形成凸出电极的晶片研磨至给定的厚度，将晶片切割为单个半导体元件，将获得的半导体元件安装在布线电路板上，以及进行树脂包封。当本发明的层压片粘附到其上存在凸出电极的电路侧面上时，凸出电极通常穿过层A并到达层B。但是，层B具有凸出电极可以嵌入其中的塑性且利用包封保护电极，由此防止晶片在工作期间凸出电极的损坏等。此外，由于本发明的层压片可以令人满意地紧密粘附到电路侧面上，因此在凸出电极和片之间基本上不产生空隙，以致层压片具有优良的凸块包装性能。
经历研磨的晶片对外力具有低的机械强度，但是通过层A将本发明的层压片粘附到晶片电路侧面上，可以充分地增加晶片的机械强度，本发明的层压片具有显示出对晶片的电路侧面有确定机械强度的层C，以便研磨之后晶片基本上不断裂。此外，可以防止研磨之后晶片的弯曲。因此，获得具有优良的晶片可加工性的晶片。
此外，通常通过在晶片的研磨之后除去(剥离)除层A之外的其他层使用本发明的层压片。具有包封功能的层A能在半导体元件和布线电路板之间进行树脂包封。当通过使用该层压片制造半导体器件时，通过层A进行树脂包封。由于层A通常包括按适于在半导体元件和布线电路板之间进行树脂包封而不覆盖凸出电极(通常，凸出电极穿过层A)的量的热固性树脂混合物，因此在安装芯片之后，过量树脂不会被推到芯片的周围，以及不抑制凸出电极和布线板电路之间的电连接，由此获得的半导体器件具有优良的电连接可靠性。
在此使用的术语“最外层”指面对最外侧的层，形成与本发明的层压片的层A相对的侧面。每一对术语“凸出电极”和“凸块”，术语“切削”和“切割”，以及术语“芯片”、“半导体芯片”和“半导体元件”分别用于相同的含义。
本发明的层压片中的层A是在使用时与安装凸出电极的晶片的电路侧面接触的热固性树脂层。在层A的形成中，可以使用，例如，仅包含有机成分的树脂组合物、包含有机成分和无机成分的树脂组合物、包含有机成分和金属颗粒的树脂组合物、包含有机成分、无机成分以及金属颗粒的树脂组合物等。
在这些组合物中，作为构成层A的热固性树脂组合物，从改进耐热性、耐湿性以及粘附性的观点，优选使用包括(i)在一个分子中具有两个或更多个环氧基的环氧树脂；(ii)固化剂；(iii)潜在固化催化剂；以及(iv)热塑性树脂的树脂组合物。之后将描述树脂组合物的细节。
层A的厚度没有特别的限制，该厚度优选10至180μm，更优选20至160μm。
本发明的层压片中的层B是在层A上直接层压的层，层B是具有用于嵌入凸出电极的塑性的热塑性树脂。在层B的形成中，例如可以使用聚氯乙烯、聚偏氯乙烯、聚乙基醋酸乙烯酯、聚乙烯醋酸乙烯酯、聚乙烯丙烯酸甲酯、聚乙烯丙烯酸乙酯、聚乙烯丙烯酸丁酯、聚四氟乙烯、聚氨酯、聚酯基骤氨酯、聚醚基聚氨酯、丙烯酸-尿烷复合聚合物等。这些材料可以单独使用或以两种或更多种的混合物使用。
此外，从改进凸块的包装性能和它的释放(releasing)性能的观点，层B在40℃至80℃时具有1到300MPa的拉伸模量，优选2到250MPa，更优选3到200MPa。通过以上述例示的材料的适当组合形成层B，层B可以具有希望的拉伸模量。因此，构成层B的热塑性树脂层具有这样的塑性，以致当本发明的层压片粘附到晶片电路侧面上时凸出电极可以令人满意地嵌入，即凸出电极可以被挤入层B。
层B的厚度没有特别的限制，该厚度优选25μm至200μm，更优50至150μm。
此外，作为本发明的层压片，优选满足下列公式：
At＜h
(At+Bt)＞h
其中h表示凸出电极的高度，由At表示层A的厚度，由Bt表示层B的厚度。这里，h优选约10至约200μm。
本发明的层压片中的层C是至少在25℃的温度下无塑性的热塑性树脂层。由于层C至少在25℃的温度下无塑性，因此在倒装芯片安装中的研磨步骤中可以保持令人满意晶片的可加工性。在层C的形成中，可以使用，例如，聚对苯二甲酸乙二醇酯、聚丙烯、双轴定向的聚丙烯、聚对苯二甲酸丁二酯、聚碳酸酯、聚酰亚胺等。这些材料可以单独使用或以两种或更多种的混合物使用。
此外，作为层C，从切割晶片时保持层压片本身的切割可加工性，以及防止研磨之后晶片的断裂和弯曲的观点，希望其在40℃至80℃时具有优选1000至3000MPa的拉伸模量，更优选1500至2500MPa。通过以上述例示的材料的适当组合形成层C，层C可以具有希望的拉伸模量。
层C的厚度不具体限制，从切割晶片时保持层压片本身的切割可加工性以及防止研磨之后晶片的断裂和弯曲的观点，该厚度优选25至150μm，更优选50至100μm。
例如，可以利用从RHEOMETRIC SCIENTIFIC可买到的RSAII在1Hz的频率条件下确定在此使用的拉伸模量。
本发明的层压片至少包括如上所述的层A、层B和层C，且没有特别的限制，只要层B直接层压在层A上。在层B和层C之间可以提供由任意已知材料制成的一个或更多其他层，只要不抑制本发明的希望效果。顺便提及，本发明的层压片的厚度优选50至500μm，更优选75至450μm，愈加优选100至400μm。
下面将详细描述可以适用于上述层A的形成的树脂组合物，该树脂组合物包括如上所述的组分(i)至(iv)。
在一个分子具有两个或更多个环氧基的环氧树脂包括双酚A环氧树脂、双酚F环氧树脂、酚醛清漆环氧树脂如苯酚酚醛清漆环氧树脂和甲酚酚醛清漆环氧树脂、脂环族环氧树脂、含氮的环状环氧树脂如三缩水甘油基异氰脲酸酯和脲基环氧树脂、氢化双酚A环氧树脂、脂肪族环氧树脂、氢化双酚A环氧树脂、脂肪族环氧树脂、缩水甘油醚环氧树脂、双酚S环氧树脂、由联苯环氧树脂主要制备的低供水率固化的产品、双环环氧树脂、萘环氧树脂等。可单独使用或以两种或更多种的混合物形式使用这些环氧树脂。
在环境温度下上述环氧树脂可以是固体或液体。从控制层A的机械强度和玻璃态转化温度的观点，优选一般具有优选90至1000g/eq的环氧当量的那些环氧树脂。从改进耐热性和固化性的观点，热固性树脂混合物中的环氧树脂的含量优选5至80重量％，更优选10至70重量％。
对作为上述成分(ii)的固化剂没有特别的限制，只要该固化剂用作环氧树脂的固化剂，可以使用各种固化剂。从具有优良的耐湿可靠性的观点通常使用酚类固化剂，也可以使用各种酸酐基固化剂、胺、双氰胺、苯并嗪环状化合物等。可单独使用或以两种或更多种的混合物形式使用这些固化剂。
上二述酚类固化剂包括，例如，甲酚酚醛清漆树脂、苯酚酚醛清漆树脂、包含二聚环戊二烯环的酚醛树脂、苯酚芳烷基树脂、苯二甲基酚树脂、萘酚等。可单独使用或以两种或更多种的混合物形式使用这些固化剂。
从保证固化性、耐热性和耐湿性的观点，如上所述的环氧树脂和酚类固化剂的组成比优选是在环氧树脂中的每1g/eq的环氧当量，酚类固化剂中的反应羟基当量通常是0.5至1.5g/eq的比率，优选0.7至1.2g/eq。顺便提及，即使在使用酚类固化剂以外的固化剂的情况下，组成比对应于使用酚类固化剂的情况中的组成比(当量比)。
作为上述成分(iii)的潜在固化催化剂指其中层A包含的潜在固化催化剂，该潜在固化催化剂具有80℃或更高的反应初始温度，这通过示差扫描热量计(从Perkin-Elmer可买到的“PYR1S1”)以10℃/分钟中的编程速率确定。潜在固化催化剂包括例如咪唑基潜在固化催化剂、胺加合物基潜在固化催化剂、含磷潜在固化催化剂、含硼潜在固化催化剂、含磷硼潜在固化催化剂、有机金属络合物基潜在固化催化剂等。此外，更优选使用其中在微胶囊中包封潜在固化催化剂的微胶囊化固化催化剂。这是因为在包含微胶囊化固化催化剂的层A中，外壳部分防止中心部分(潜在固化催化剂)和固化剂之间物理接触，以便在焊接步骤中抑制层A的凝胶化，由此表现出优良的焊接性能。此外，可以抑制在储藏等过程中层A的不希望固化，由此大大地延伸可用时间，因此得到优良的储藏稳定性的优点。
这里，根据例如日本专利特许公开号2000-309682中描述的方法制备上述微胶囊化固化催化剂。
上述潜在固化催化剂可以单独使用或以两种或更多种的混合物的形式使用。
可以按比率适当地设置适于形成层A的热固性树脂组合物中的潜在固化催化剂的含量，以便获得希望的固化速率而不降低焊接性能和粘附力。该设置方法包括例如，在加热板上测量包含各种量的潜在固化催化剂的层A的胶凝时间(固化速率的系数)，由此将获得希望胶凝时间的量定义为它的含量。一般，基于100重量份的固化剂，热固性树脂组合物中的潜在固化催化剂的含量优选0.1至40重量份，更优选1至20重量份。
作为上述成分(iv)的热塑性树脂包括例如丙烯酸共聚物的烷基酯、丙烯腈-丁二烯共聚物、氢化丙烯腈-丁二烯共聚物、苯乙烯-丁二烯-苯乙烯共聚物、环氧改性的苯乙烯-丁二烯-苯乙烯共聚物等。此外，热固性树脂组合物中的这些热塑性树脂的含量没有特别的限制，只要适于形成层A的上述树脂组合物可以形成为片材。从保证与晶片的粘附性能、切割可加工性和芯片安装性能的观点，热固性树脂组合物中的这些热塑性树脂的含量优选1至50重量％，更优选3至30重量％。
此外，依照要求可以将无机填料、偶联剂、颜料、染料等添加到构成层A的热固性树脂组合物中。无机填料包括氧化铝、硅石、氮化硅、二氧化钛、氧化锆等。热固性树脂混合物中的无机填料的含量没有特别的限制。从控制热固性树脂组合物的粘度和保证半导体元件和布线电路板之间的电键合的观点，热固性树脂混合物中的无机填料的含量优选0至70重量％，更优选0至65重量％。
例如，可以如下通过使用如上所述的适合的树脂组合物形成层A。具体地，按给定的量混合各种组分如环氧树脂、固化剂、潜在固化催化剂和热塑性树脂，混合获得的混合物并溶于有机溶剂如甲苯、甲基乙基酮或乙酸乙酯中，以及将这些混合的溶液涂敷到包括如之后所述设置的层B和层C(和根据需要存在的附加的其他层)的剥离片(stripping sheet)上。接下来，在约80℃至约160℃的温度下干燥该片，此后除去有机溶剂，由此在该片上形成层A。另外，以给定量混合各种组分如环氧树脂、固化剂、潜在固化催化剂和热塑性树脂，混合获得的混合物并溶于有机溶剂如甲苯、甲基乙基酮或乙酸乙酯，且将这些混合的溶液涂敷到经历释放处理的基底薄膜如聚酯薄膜上。接下来，在约80℃至约160℃的温度下干燥该涂敷的基底，由此在基底薄膜上形成层A。
顺便提及，可以通过常规的已知方法如压延(calendar)方法、浇铸方法、充气挤压法或下型模挤压法形成构成上述剥离片的层B和层C(和根据需要存在的附加的其他层)。
此外，按照要求如上所述形成的剥离片的表面可以经历常规采用的物理或化学处理，如镜面处理，电晕放电处理、底漆(primer)处理或交联处理。
至于如上所述形成的层A的性能，其熔体粘度在80℃时优选1至500Pas，更优选10至3000Pas，在175℃时胶凝时间优选2至120秒、更优选3至90秒。如上所述范围内的熔体粘度是优选的，因为包装性能变得优良。如上所述范围内的胶凝时间是优选的，因为模制可操作性变得优良。
使用E-型粘度计(从HAAKE可买到的RS1)，将板的直径设为20mm、间距设为100μm和剪切速率设为10(1/s)，确定80℃时1g的层A的上述熔体粘度。
此外，根据下列步骤(1)至(5)确定上述胶凝时间：
(1)用表面温度计确定加热板的表面温度，并设置在给定的温度。
(2)取待测定的200至400mg样品(层A)并放置在加热板上，使样品迅速展开。
(3)在熔化样品的同时，用计时表启动胶凝时间的测定。
(4)搅拌样品5秒，此后在10秒的周期中薄薄地展开。
(5)用针尖牵曳线条，线条展开和散开的点定义为终点，在该点停止计时表，并读出时间。该时间周期被定义为胶凝时间。
通过在如上所述的剥离片上形成层A，或另外使用辊层压装置将基底薄膜上形成的层A粘附到上述剥离片上，并除去基底薄膜可以获得本发明的层压片。粘附条件没有特别的限制，根据已知条件层A可以粘附到剥离片。
如上所述，获得了本发明的层压片。图1中示出了包括层A、层B和层C的片的一个例子，其中在层A1上层压层B2，以及在层B2上层压层C3。
接下来，将描述用于制造本发明的半导体器件的方法。用于制造本发明的半导体器件的方法包括以下步骤：研磨安装凸出电极的晶片的背部，其中本发明的层压片粘附到晶片的电路侧面上，除去层压片的层A之外的其他层，将晶片切割为单个芯片。图3至8每一个示出了用于制造本发明的半导体器件的方法中的每个步骤的一个例子。下面通过参考这些附图说明用于制造本发明的半导体器件的方法。
图2中示出了安装凸出电极的晶片的一个例子，其中在晶片4上形成凸出电极5。
在本发明中可用的晶片4的材料包括但不特别局限于硅、镓-砷等。晶片4的厚度没有特别的限制，例如，优选约200至约1000μm。
凸出电极5例如包括，但是不特别局限于通过焊接获得的低熔点和高熔点凸块、锡凸块、银-锡凸块、银-锡-铜凸块、金凸块、铜凸块等。凸出电极5的高度没有特别的限制，优选10至200μm。
图3中示出了其中本发明的层压片(图1图示)粘附到上述晶片的电路侧面上的一个例子，其中晶片4的电路侧面和层A1彼此接触，凸出电极5穿透层A1，嵌入层B2。凸出电极5未到达层C3。
当层压片粘附到上述晶片时，使用辊型粘附装置和真空型粘附装置。从减小砂眼、提高晶片的紧密接触和防止研磨之后晶片弯曲的观点，粘附温度优选25℃至100℃，更优选40℃至80℃。此外，根据粘附方法、粘附时间等适当地设置粘附压力。
图4中示出了研磨之后晶片的一个例子，晶片上粘附着上述层压片，其中晶片4的背部经历研磨时保持层压片粘附在晶片4上。
在背部的研磨中，使用具有研磨台研磨装置，没有特别的限制。研磨装置包括已知的装置如从DISCOK.K可买到的“DFG-840”。此外，研磨条件没有特别的限制。研磨之后晶片的厚度优选约50至约600μm。
图5中示出研磨之后(研磨侧面)切割带粘附到晶片的背部的一个例子，其中切割带6粘附到经历研磨的晶片4的背部。
可用于本发明中的切割带没有特别的限制，只要切割带是所述领域中通常的切割带。
用于切割带的粘附装置和粘附条件没有特别的限制，可以采用已知的装置和条件。
图6示出了除去剥离片之后晶片的一个例子，其中仅除去粘附到晶片4的层压片的剥离片(层B2和层C3)，由此在晶片4上仅留下层A1。
通过使用，例如，可从Nitto Denko有限公司买到的“HR-8500-II”进行剥离片的去除。
图7中示出了晶片的切割(切削)之后的一个例子，其中粘附着层A1的晶片4被切割为单个芯片，保持晶片4粘附到切割带6上。
晶片的切割没有特别的限制，用普通的切割装置进行切割。
在另一个实施例中，在晶片的切割中，当层A的透明度低以及不能识别晶片的电路侧面的图形等时，通过将切割带粘附到层C而不是粘附到晶片的背部以及使用红外照相机进行图形识别来进行切割。
图8中示出用于安装芯片的方法的一个例子，其中从切割带取下单个芯片7，并安装在布线电路板8上。通过层A1树脂包封晶片4和布线电路板8之间的间隙。
布线电路板8没有特别的限制，且粗略地分为陶瓷板和塑料板。塑料板包括例如环氧板、双马来酰亚胺基三嗪板、聚酰亚胺板、玻璃环氧板等。
用于将单个芯片7安装在布线电路板上的方法包括这样一种方法，该方法包括首先从切割带拾起并移动单个芯片，以及将单个芯片放置在芯片托盘中或将单个芯片传送到倒装芯片键合器的芯片安装喷嘴；以及此后(i)在将半导体元件安装到布线电路板的同时获得电连接，同时以凸块键合形式利用加热加压(热压安装)；(ii)在使用加热、加压和超声作用将半导体元件安装到布线电路板的同时获得电连接；(iii)将半导体元件安装到布线电路板上，此后通过回流焊等获得电连接；等等。
从芯片和布线电路板的退化的观点，上述加热温度优选500℃或更低，更优选400℃或更低。尽管上述加压条件取决于连接电极的数目等，但是该压力优选9.8×10-3至1.96N/芯片，更优选1.96×10-2至9.8×10-1N/芯片。加热方法包括使用红外回流炉、干燥器、热气供应器、加热板等的已知方法。
根据上述方法，可以有效地获得具有优良的电连接可靠性和耐用性的半导体器件。本发明包括获得的半导体器件。
实施例
通过下列实施例更具体描述本发明，而不打算限制本发明的范围。
下面一并地列出了实施例中使用的原材料和部件。
在层A的形成中，使用萘环氧树脂(环氧当量：141g/eq.)作为环氧树脂、苯二甲基酚醛树脂(羟基当量：174g/eq.)作为固化剂、微胶囊化的三苯基膦(TPP)(外壳：聚脲，中心/外壳比3/7(wt/wt))作为潜在固化催化剂，丙烯腈-丁二烯共聚物(丙烯腈键合度：27，莫尼粘度：70ML1+4/100℃)作为热塑性树脂以及球形硅石(平均颗粒尺寸：2μm，最大颗粒尺寸：5μm)作为无机填料。
在层B的形成中，使用丙烯酸-尿烷复合聚合物、聚氯乙烯或聚乙烯醋酸乙烯酯。
在层C的形成中，使用聚对苯二甲酸乙二醇酯、聚丙烯或聚氯乙烯。
至于安装凸出电极的晶片，使用以下晶片。
尺寸：8英寸(约200毫米)；
厚度：525μm；
布线：铝；
凸出电极：金柱凸块；
凸出电极的高度：85±10μm；
凸出电极的数目：240/10mm2(单个芯片)；
电极间距：135μm；以及
钝化膜：聚酰亚胺。
至于布线电路板，使用下列布线电路板。
材料：玻璃环氧树脂；
布线：铜-镍-金；
布线厚度：35μm
下面概述评价方法。
(1)厚度
利用从PEACOCK可买到的DG205测定每个层的厚度。
(2)胶凝时间
用表面温度计测定热板的表面温度，设置该表面温度以便具有175℃的表面温度。取待测定的200至400毫克样品，并放置在热板上使样品快速展开。在熔化样品的同时用计时表开始测定。搅拌样品5秒，此后在10秒的周期中薄薄地展开。用针尖牵曳线条，线条展开和分开处的点定义为终点，在该点停止计时表并读出时间。该时间周期定义为胶凝时间。
(3)熔体粘度
使用E-型粘度计(从RS1可买到的HAAKE)测定80℃时1g的层A的熔体粘度。刀片的直径设为20mm，间隙设为100μm以及剪切率设为10(l/s)。
(4)拉伸模量
每个层被切割为5mm宽和25mm长的尺寸，并在40至80℃时用可从RHEOMETRIC SCIENTIFIC买到的RSAII测定拉伸模量。频率设在1Hz。
(5)凸块的包装性能
视觉上证实在将层压片粘附到晶片之后凸块周围中的空隙。根据下列评价标准评价包装性能。
[评价标准]
无砂眼：○
砂眼：×
(6)晶片的背部研磨(BG)之后的断裂
视觉上证实研磨晶片的背部之后晶片的断裂，根据下列评价标准评价：
[评价标准]
无断裂：○
断裂：×
(7)晶片的弯曲量
用直尺测量研磨晶片的背部之后晶片的最大弯曲量，根据下列评价标准评价：
[评价标准]
弯曲量小于3mm：○
弯曲量是3mm或更多：×
(8)安装芯片之后的电导率
在-40℃下保持半导体器件5分钟的步骤，此后用热震动设备(可从ESPEC公司可买到的TSB-5)在100℃下保持半导体器件5分钟。在该步骤之后，评价半导体器件的电导率，并且用20个半导体器件中不能接受产品的数目来表示。在电导率的评价中，用daisychain(从ADVANTEST可买到的DIGITAL MULTIMETERTR6847)测定半导体器件的电阻，而未指示电阻的那些算作不能接受产品。
(9)树脂展开量
测定从半导体器件中的芯片安装区构成层A的热固性树脂组合物的展开，根据下列评价标准评价：
[评价标准]
小于1.5毫米：○
1.5毫米或更多：×
(10)回流焊的评价
根据JEDEC标准3测定260℃时回流焊之后半导体器件的电阻，并且用20个半导体器件20中不能接受的数目来表示。在该评价中，用daisy chain(从ADVANTEST可买到的DIGITAL MULTIMETER TR6847)测定半导体器件的电阻，并将它的电阻与初始值(进行上述步骤之前的半导体器件的电阻)相比。具有初始值的1.5倍的电阻算作是不能接受的产品。
(11)热循环测试
在-55℃下保持半导体器件30分钟的步骤，此后进行在125℃下保持半导体器件30分钟。该步骤的每100次循环，用daisy chain(从ADVANTEST可买到的DIGITAL MULTIMETER TR6847)测定半导体器件的电阻，将它的电阻与初始值相比(进行上述步骤之前的半导体器件的电阻)。热循环测试表示为该电阻维持在初始值的1.5倍或更小值的热循环的最大数目。
实施例1至8和比较例1至5
如下形成实施例1至8和比较例1至5的层压片。该层压片具有与图1中所示相同的形状。
(1)层A的形成
混合列表1中所示的每种原材料并按同一列表中所示的比率溶于甲基乙基酮，以及将这些混合溶液涂敷到经历释放处理的聚酯薄膜。接下来，在120℃下干燥聚酯薄膜上的溶液5分钟，以除去甲基乙基酮，由此在上述聚酯薄膜上形成具有30μm或90μm厚度的每一需要的层A(A1至A3)。测定该层的性能。
表1
               层A
    A1     A2     A3
    原材料环氧树脂(g)固化剂(g)潜在固化催化剂(g)热塑性树脂(g)硅石(g) 18.823.2260 18.823.2260 9.411.61325
    性能厚度(μm)胶凝时间/175℃(sec)熔体粘度/80℃(Pa·s) 3013550 9013550 30131100
(2)层B的形成
使用表2所示的原材料形成层B(B1至B6)。测定该层的性能。
表2
                                 层B
B1 B2 B3 B4 B5   B6
       原材料 丙烯酸-聚氨酯复合聚合物 丙烯酸-聚氨酯复合聚合物 丙烯酸-聚氨酯复合聚合物 丙烯酸-聚氨酯复合聚合物 聚氯乙烯   聚氯乙烯
      性能厚度(μm) 100480390280 100220150- 100124- 10043- 100506- 1007010-
拉伸弹性(Mpa)   40℃80℃150℃
(3)层C的形成
使用表3所示的原材料形成层C(C1至C3)。测定该层的性能。
表3
                       层C
    C1   C2     C3
       原材料     聚对苯二甲酸乙二醇酯   聚丙烯     聚氯乙烯
      性能厚度(μm) 5022002200 5015001500 50800750
拉伸弹性(Mpa)   40℃80℃
(4)剥离片的形成
将具有20μm厚度的丙烯酸基粘附层作为锚固层粘附到如上所述形成的层C的一侧，由此通过丙烯酸基粘附层粘附B和层C，以产生剥离片。
(5)层压片的形成
在60℃将层A粘附到如上所述形成的剥离片的层B的侧面上，以产生层压片。顺便提及，表4和5中示出了实施例和比较例的每个层压片中的层A、B和C的组合。
表4
  实施例1     实施例2     实施例3    实施例4   实施例5     比较例1   比较例2
  层A   A1     A1     A1    A1   A1     A1   A1
  层B   B2     B3     B4    B5   B6     B1   B1
  层C   C1     C1     C1    C1   C1     C1   C1
表5
    实施例6     实施例7     实施例8    比较例3     比较例4     比较例5
    层A     A3     A1     A1    A1     A2     A1
    层B     B2     B2     B2    B1     B1     B1
    层C     C1     C1     C2    C3     C1     C1
实施例9至16和比较例6至10
如下制造实施例9至16和比较例6至10的半导体器件。在40℃、80℃或150℃下(参见表6和7)用辊粘结设备(从Nitto Denko有限公司可买到的DR-8500-II)将如上所述形成的实施例1至8和比较例1至5的每—层压片粘附到安装凸出电极的晶片的电路板侧面上。用研磨设备(从DISCO可买到的DFG-840)使获得的晶片经研磨至50μm的厚度。此后，切割带(从Nitto Denko有限公司可买到的DU-300)被粘附到晶片上。接下来，除去条形薄片，此后用切割设备(从DISCO可买到的DFD-651)将获得的晶片切割为单个芯片，以产生具有层A的芯片。
表6
实施例9 实施例10 实施例11 实施例2 实施例13 比较例6 比较例7
层压片 实施例1 实施例2 实施例3 实施例4 实施例5 比较例1 比较例2
粘附到电路板侧面的温度(℃) 40 40 40 40 40 40 80
表7
实施例14 实施例15 实施例16 比较例8 比较例9 比较例10
  层压片 实施例6 实施例7 实施例8 比较例3 比较例4 比较例5
  粘附到电路板侧边的温度(℃) 40 80 80 40 80 150
此后，根据热压安装法(在安装芯片过程中：温度＝120℃，压力＝9.8×10-2N/芯片，时间＝3秒；在实际加压过程中：温度=240℃，压力=4.9×10-1N/芯片，时间=10秒)，通过使用倒装芯片键合器(从Kyusyu Matsushita可买到的FB30T-M)将具有层A的芯片安装到布线电路板来制造半导体器件。使用干燥炉(从ESPEC公司可买到的PHH-100.)使获得的半导体器件进行层A的后固化，以产生希望的半导体器件。
测试例
对实施例9至13和比较例6和7中制造的半导体器件进行上述评价。表8中示出了结果。
表8
    实施例9   实施例10   实施例11   实施例12   实施例13   比较例6   比较例7
  凸块的包装性能BG之后的断裂晶片的弯曲量(mm)安装芯片之后电导率不可接受的产品数目晶片展开的量(mm)回流焊中不可接受的产品数目热循环次数     ○○○0/20○0/20500   ○○○0/20○0/20500   ○○○0/20○0/20500   ○○○0/20○0/20500   ○○○0/20○0/20500   ××-----   ××-----
从列表8的结果可以看出实施例9至13中制造的半导体器件在任意评价项都显示出优良的评价结果。另一方面，可以看出比较例6和7中制造的半导体器件每个具有在40℃和80℃时超过300MPa的层B的拉伸模量，以致凸块的包装性能被损害和在BG之后产生断裂，由此不能获得优良的半导体器件。
对实施例14至16和比较例8至10中制造的半导体器件进行上述评价。表9中示出了结果。
表9
  实施例14     实施例15     实施例16 比较例8 比较例9 比较例10
    凸块的包装性能   ○     ○     ○  ○  ○   ○
    晶片的弯曲量(mm)   ○     ○     ○  ×  ○   ×
    安装芯片之后电导率不可接受的产品数目晶片展开的量(mm)回流焊中不可接受的产品数目热循环次数 0/20○0/201000 0/20○0/20500 0/20○0/20500 ---- 3/20×-- ----
从表9的结果可以看出在实施例14至16制造的半导体器件中，当层C具有1000至3000MPa范围内的拉伸模量时，显示出优良的评价结果，与构成层A每一原材料的含量无关和与构成层C的原材料无关。
另一方面，可以看出尽管与比较例6和7中制造的那些半导体器件相比该半导体器件的凸块包装性能和BG之后的断裂具有良好的结果，但是比较例8中制造的半导体器件不满足晶片弯曲量的评价标准。
此外，可以看出尽管半导体器件在凸块的包装性能、BG之后的断裂以及晶片弯曲量方面具有良好的结果，但是比较例9中制造的半导体器件导致安装芯片之后电导率失败，而且树脂展开量不满足评价标准。
而且，可以看出在比较例10中制造的半导体器件中，层B在150℃时具有1至300MPa的拉伸模量(参见表2)。因此，尽管表现出凸块包装性能和BG之后断裂方面的良好结果，但是半导体器件不满足晶片弯曲量的评价标准。
本发明的层压片具有优良的凸块包装性能以及产生优良的晶片可加工性，且可以用于半导体元件和布线电路板之间的树脂包封。此外该层压片可以保证半导体器件的优良的电连接可靠性。上述层压片可以粘附到晶片电路板的电路侧面上而不产生空隙，以致在晶片的背部研磨之后没有晶片的弯曲产生以及没有将树脂推开到树脂的周围。由此，通过使用上述层压片可以有效地制造半导体器件。
如此描述了本发明，显然可以在许多方面进行改变。这种改变不认为是背离本发明的精神和范围，且对于所述领域的技术人员来说显然所有的这种改进都包括在下列权利要求的范围内。

Claims (8)

1、一种层压片，该层压片用于在研磨晶片背部的步骤中粘附到安装了凸出电极的晶片的电路侧面上，其中该层压片至少包括：
与电路侧面接触、由热固性树脂制成的层A；
直接层压在层A上、由在40℃至80℃时具有1至300MPa的拉伸模量的热塑性树脂制成的层B；以及
由至少在25℃的温度下无塑性的热塑性树脂制成的最外层C。
2、根据权利要求1的层压片，其中层C在40℃至80℃时具有1000至3000MPa的拉伸模量。
3、根据权利要求1的层压片，其中h，At和Bt满足以下关系：
At＜h和(At+Bt)＞h，
其中h是凸出电极的高度，At是层A的厚度，以及Bt是层B的厚度。
4、根据权利要求3的层压片，其中At是10至180μm，Bt是25至200μm。
5、根据权利要求4的层压片，其中h是10至200μm。
6、根据权利要求1的层压片，其中构成层A的热固性树脂组合物包括：
(i)在一个分子中具有两个或更多个环氧基的环氧树脂；
(ii)固化剂；
(iii)潜在固化催化剂；以及
(iv)热塑性树脂。
7、一种用于制造半导体器件的方法包括以下步骤，研磨安装凸出电极的晶片的背部，其中权利要求1至6的任意一项的层压片粘附在晶片的电路侧面上，除去层压片的层A之外的其他层，以及将晶片切割为单个芯片。
8、一种通过权利要求7的方法获得的半导体器件。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102637589A (zh) * 2011-02-15 2012-08-15 日东电工株式会社 半导体装置的制造方法

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005322804A (ja) * 2004-05-10 2005-11-17 Nitto Denko Corp 光半導体装置
US20060068213A1 (en) * 2004-09-29 2006-03-30 O'brien Kevin Decorative laminate assembly with improved tie sheet and bridging agent
CN101035649B (zh) * 2004-10-08 2010-09-08 昭和电工株式会社 液体珩磨加工机和液体珩磨加工方法
JP2006261529A (ja) * 2005-03-18 2006-09-28 Lintec Corp フリップチップ実装用アンダーフィルテープおよび半導体装置の製造方法
US20090075429A1 (en) * 2005-04-27 2009-03-19 Lintec Corporation Sheet-Like Underfill Material and Semiconductor Device Manufacturing Method
JP2007035880A (ja) * 2005-07-26 2007-02-08 Matsushita Electric Works Ltd バンプ付きウエハの製造方法、バンプ付きウエハ、半導体装置
JP2007141963A (ja) * 2005-11-15 2007-06-07 Denso Corp 基板の実装方法、及びその実装方法で実装された半導体装置
JP4699189B2 (ja) * 2005-12-01 2011-06-08 日東電工株式会社 半導体装置の製造方法及び電子部品
JP2007250952A (ja) * 2006-03-17 2007-09-27 Sanken Electric Co Ltd 半導体装置およびその製造方法
JP2007266191A (ja) * 2006-03-28 2007-10-11 Nec Electronics Corp ウェハ処理方法
US8766224B2 (en) 2006-10-03 2014-07-01 Hewlett-Packard Development Company, L.P. Electrically actuated switch
JP2008159755A (ja) * 2006-12-22 2008-07-10 Sekisui Chem Co Ltd 半導体装置の製造方法
US7838391B2 (en) * 2007-05-07 2010-11-23 Stats Chippac, Ltd. Ultra thin bumped wafer with under-film
US9111981B2 (en) * 2008-01-24 2015-08-18 Brewer Science Inc. Method for reversibly mounting a device wafer to a carrier substrate
WO2009099191A1 (ja) 2008-02-07 2009-08-13 Sumitomo Bakelite Company Limited 半導体用フィルム、半導体装置の製造方法および半導体装置
JP5318435B2 (ja) * 2008-02-29 2013-10-16 日東電工株式会社 半導体ウエハの裏面研削用粘着シート及びこの裏面研削用粘着シートを用いる半導体ウエハの裏面研削方法
JP2009260224A (ja) * 2008-03-21 2009-11-05 Hitachi Chem Co Ltd 半導体ウエハのダイシング方法及び半導体装置の製造方法
JP2009260232A (ja) * 2008-03-26 2009-11-05 Hitachi Chem Co Ltd 半導体封止用フィルム状接着剤、半導体装置及びその製造方法
JP5837272B2 (ja) * 2008-05-21 2015-12-24 日立化成株式会社 半導体製造装置の製造方法
US20100007007A1 (en) * 2008-07-08 2010-01-14 Samsung Electronics Co., Ltd Semiconductor package
US8431921B2 (en) 2009-01-13 2013-04-30 Hewlett-Packard Development Company, L.P. Memristor having a triangular shaped electrode
JP5477144B2 (ja) * 2009-05-26 2014-04-23 日立化成株式会社 回路部材接続用接着剤シート及び半導体装置の製造方法
CN102918430B (zh) 2010-06-01 2016-08-24 3M创新有限公司 多层密封膜
US8852391B2 (en) 2010-06-21 2014-10-07 Brewer Science Inc. Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate
US9263314B2 (en) 2010-08-06 2016-02-16 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
CN103081081B (zh) * 2010-08-23 2016-03-02 积水化学工业株式会社 粘接片及半导体芯片的安装方法
JP2012074623A (ja) * 2010-09-29 2012-04-12 Sekisui Chem Co Ltd 半導体加工用接着フィルム及び半導体チップ実装体の製造方法
JP5957794B2 (ja) * 2011-01-26 2016-07-27 日立化成株式会社 積層シート及び半導体装置の製造方法
JP5802400B2 (ja) * 2011-02-14 2015-10-28 日東電工株式会社 封止用樹脂シートおよびそれを用いた半導体装置、並びにその半導体装置の製法
JP5666335B2 (ja) 2011-02-15 2015-02-12 日東電工株式会社 保護層形成用フィルム
TWI540644B (zh) 2011-07-01 2016-07-01 漢高智慧財產控股公司 斥性材料於半導體總成中保護製造區域之用途
JP2013021119A (ja) * 2011-07-11 2013-01-31 Shin Etsu Chem Co Ltd ウエハーレベルアンダーフィル剤組成物、これを用いた半導体装置及びその製造方法
JP5800640B2 (ja) * 2011-08-30 2015-10-28 日東電工株式会社 発光ダイオード装置の製造方法
JP5958262B2 (ja) 2011-10-28 2016-07-27 信越化学工業株式会社 ウエハ加工体、ウエハ加工用部材、ウエハ加工用仮接着材、及び薄型ウエハの製造方法
JP6337417B2 (ja) * 2012-03-16 2018-06-06 住友ベークライト株式会社 接着シートおよび電子部品
JP5965185B2 (ja) 2012-03-30 2016-08-03 デクセリアルズ株式会社 回路接続材料、及びこれを用いた半導体装置の製造方法
SG11201406125PA (en) 2012-05-30 2014-11-27 Toray Industries Adhesive sheet for production of semiconductor device with bump electrode, and method for production of semiconductor device
JP5738263B2 (ja) * 2012-12-25 2015-06-17 日立化成株式会社 半導体装置の製造方法
KR102070091B1 (ko) 2013-02-20 2020-01-29 삼성전자주식회사 기판 연마 방법 및 이를 이용한 반도체 발광소자 제조방법
JP5976573B2 (ja) * 2013-03-13 2016-08-23 日東電工株式会社 補強シート及び二次実装半導体装置の製造方法
JP6358535B2 (ja) * 2013-04-26 2018-07-18 パナソニックＩｐマネジメント株式会社 配線板間接続構造、および配線板間接続方法
JP6069143B2 (ja) 2013-09-11 2017-02-01 デクセリアルズ株式会社 アンダーフィル材、及びこれを用いた半導体装置の製造方法
JP6069142B2 (ja) 2013-09-11 2017-02-01 デクセリアルズ株式会社 アンダーフィル材、及びこれを用いた半導体装置の製造方法
JP6129696B2 (ja) 2013-09-11 2017-05-17 デクセリアルズ株式会社 アンダーフィル材、及びこれを用いた半導体装置の製造方法
JP6069153B2 (ja) 2013-09-27 2017-02-01 デクセリアルズ株式会社 アンダーフィル材、及びこれを用いた半導体装置の製造方法
WO2015098949A1 (ja) * 2013-12-26 2015-07-02 日立化成株式会社 仮固定用フィルム、仮固定用フィルムシート及び半導体装置
JP6328987B2 (ja) * 2014-04-22 2018-05-23 デクセリアルズ株式会社 半導体装置の製造方法
JP6347657B2 (ja) * 2014-04-22 2018-06-27 デクセリアルズ株式会社 保護テープ、及びこれを用いた半導体装置の製造方法
JP2015092594A (ja) * 2014-12-10 2015-05-14 日東電工株式会社 保護層形成用フィルム
JP6438790B2 (ja) 2015-02-06 2018-12-19 デクセリアルズ株式会社 半導体装置の製造方法、及びアンダーフィルフィルム
JP6021982B2 (ja) * 2015-03-31 2016-11-09 積水化学工業株式会社 バックグラインド−アンダーフィル一体型テープ、及び、半導体チップの実装方法
JP6599134B2 (ja) 2015-06-04 2019-10-30 デクセリアルズ株式会社 保護テープ、及びこれを用いた半導体装置の製造方法
JP6595296B2 (ja) 2015-10-19 2019-10-23 デクセリアルズ株式会社 保護テープ、及び半導体装置の製造方法
WO2017078042A1 (ja) 2015-11-04 2017-05-11 リンテック株式会社 保護膜形成用シート
JP6273542B2 (ja) 2015-11-04 2018-02-07 リンテック株式会社 硬化性樹脂フィルム及び第１保護膜形成用シート
CN108140622B (zh) 2015-11-04 2021-03-05 琳得科株式会社 热固性树脂膜和第2保护膜形成膜的套件、及其形成方法
US20180320029A1 (en) 2015-11-04 2018-11-08 Lintec Corporation Curable resin film and first protective film forming sheet
TWI623425B (zh) * 2015-11-04 2018-05-11 日商琳得科股份有限公司 固化性樹脂膜及第一保護膜形成用片
TWI641494B (zh) 2015-11-04 2018-11-21 日商琳得科股份有限公司 第一保護膜形成用片、第一保護膜形成方法以及半導體晶片的製造方法
TWI643741B (zh) 2015-11-04 2018-12-11 琳得科股份有限公司 固化性樹脂膜及第一保護膜形成用片
JP6816918B2 (ja) * 2015-11-04 2021-01-20 リンテック株式会社 半導体装置の製造方法
JP6230761B2 (ja) 2015-11-04 2017-11-15 リンテック株式会社 第１保護膜形成用シート
TWI761317B (zh) 2015-11-04 2022-04-21 日商琳得科股份有限公司 熱固化性樹脂膜、第一保護膜形成用片以及第一保護膜的形成方法
US9837375B2 (en) * 2016-02-26 2017-12-05 Semtech Corporation Semiconductor device and method of forming insulating layers around semiconductor die
JP6132056B2 (ja) * 2016-06-17 2017-05-24 日立化成株式会社 半導体装置の製造方法
GB2551732B (en) * 2016-06-28 2020-05-27 Disco Corp Method of processing wafer
WO2018088269A1 (ja) * 2016-11-08 2018-05-17 リンテック株式会社 半導体装置の製造方法
JP6975006B2 (ja) * 2016-12-26 2021-12-01 リンテック株式会社 ワークの製造方法
KR102325868B1 (ko) 2017-05-16 2021-11-12 데쿠세리아루즈 가부시키가이샤 언더필재, 언더필 필름, 및 이를 이용한 반도체 장치의 제조 방법
JP7095978B2 (ja) * 2017-11-16 2022-07-05 日東電工株式会社 半導体プロセスシートおよび半導体パッケージ製造方法
SG11202100988PA (en) * 2018-08-03 2021-03-30 Showa Denko Materials Co Ltd Adhesive composition, film-like adhesive, adhesive sheet, and method for producing semiconductor device
WO2020100696A1 (ja) 2018-11-12 2020-05-22 日立化成株式会社 半導体装置の製造方法及び半導体ウエハ加工用接着フィルム
JP7047750B2 (ja) * 2018-12-21 2022-04-05 味の素株式会社 積層配線板の製造方法
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JP7032477B2 (ja) * 2020-06-19 2022-03-08 日東電工株式会社 バンプ根元補強用シート
KR20230166071A (ko) 2021-03-30 2023-12-06 가부시끼가이샤 레조낙 반도체용 접착제, 반도체용 접착제 시트, 및 반도체장치의 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1240464A (zh) * 1996-12-16 2000-01-05 国际壳牌研究有限公司 用于电子封装的热固性密封剂
JP2000223602A (ja) * 1999-01-29 2000-08-11 Motorola Japan Ltd チップを基板に接合する構造およびその製造方法
JP2001144123A (ja) * 1999-09-02 2001-05-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
JP2001144140A (ja) * 1999-11-12 2001-05-25 Lintec Corp 半導体装置の製造方法
JP2003188334A (ja) * 2001-12-17 2003-07-04 Tomoegawa Paper Co Ltd 半導体装置製造用接着シート

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1660721A (en) * 1926-07-02 1928-02-28 Martin J Schrag Orthopedic apparatus
US4099525A (en) * 1977-03-07 1978-07-11 Mccarthy Robert O Animal leg brace
US5230700A (en) * 1989-04-28 1993-07-27 Charles Humbert Orthopedic apparatus for persons handicapped in one leg
US5578041A (en) * 1994-10-14 1996-11-26 Trustees Of The University Of Pennsylvania External fixation device
US6350664B1 (en) * 1999-09-02 2002-02-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JP2001144120A (ja) 1999-11-10 2001-05-25 Sumitomo Bakelite Co Ltd 半導体装置およびその製造方法
JP4369584B2 (ja) 2000-01-21 2009-11-25 日東電工株式会社 半導体ウエハ保持保護用粘着シート
JP4438973B2 (ja) * 2000-05-23 2010-03-24 アムコア テクノロジー，インコーポレイテッド シート状樹脂組成物及びそれを用いた半導体装置の製造方法
JP2002327165A (ja) 2001-04-20 2002-11-15 Three M Innovative Properties Co 熱硬化性の接着剤フィルム及びそれを用いた接着構造
US6794751B2 (en) * 2001-06-29 2004-09-21 Intel Corporation Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies
US20030111519A1 (en) 2001-09-04 2003-06-19 3M Innovative Properties Company Fluxing compositions
JP3717899B2 (ja) * 2002-04-01 2005-11-16 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1240464A (zh) * 1996-12-16 2000-01-05 国际壳牌研究有限公司 用于电子封装的热固性密封剂
JP2000223602A (ja) * 1999-01-29 2000-08-11 Motorola Japan Ltd チップを基板に接合する構造およびその製造方法
JP2001144123A (ja) * 1999-09-02 2001-05-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
JP2001144140A (ja) * 1999-11-12 2001-05-25 Lintec Corp 半導体装置の製造方法
JP2003188334A (ja) * 2001-12-17 2003-07-04 Tomoegawa Paper Co Ltd 半導体装置製造用接着シート

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102637589A (zh) * 2011-02-15 2012-08-15 日东电工株式会社 半导体装置的制造方法
CN102637589B (zh) * 2011-02-15 2015-03-04 日东电工株式会社 半导体装置的制造方法

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