TWI540644B - 斥性材料於半導體總成中保護製造區域之用途 - Google Patents

斥性材料於半導體總成中保護製造區域之用途 Download PDF

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TWI540644B
TWI540644B TW101123332A TW101123332A TWI540644B TW I540644 B TWI540644 B TW I540644B TW 101123332 A TW101123332 A TW 101123332A TW 101123332 A TW101123332 A TW 101123332A TW I540644 B TWI540644 B TW I540644B
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雷伊 佩迪
傑夫利 葛沙
栗山健治
柳浩承
凱文 貝克
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漢高智慧財產控股公司
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Description

斥性材料於半導體總成中保護製造區域之用途
本發明係關於製造半導體晶粒之方法。
在製造半導體晶粒之習用方法中,半導體晶圓經處理以在晶圓頂部側上形成複數個電路,且在隨後步驟中,沿指定切割道或線將晶圓分成個別晶粒,其各自在其頂部側上具有至少一個電路。個別晶粒用於半導體封裝中或電路板上,且藉由黏著劑附接至其基板。除晶圓上之常見半導體電路之外,所製造之一些晶圓具有穿透矽通孔、微凸塊及其他製造元件。
電及電子設備之微型化及輕量化導致需要較薄之半導體晶粒。一種產生較薄半導體晶粒之方式係在將晶圓分成個別晶粒之前自晶圓背側(無任何電路之側)移除過量材料。此移除通常藉由研磨方法來實施且稱為背側研磨,但可預期可使用除研磨之外的方法。在研磨之後,然後藉由機械或雷射鋸割將薄晶圓單體化成個別晶粒。對於極薄晶圓(<50 μm)而言,此標準方法存在潛在問題。極薄晶圓較脆且往往會翹曲。此外,鋸割該等薄晶圓可造成背側或前側碎裂或側壁破裂。
將用於附接個別晶粒之黏著劑施加至晶圓級基板而非至個別晶粒更有效。因此,在一種製造方法中,將黏著劑施加至晶圓背側且稱其為晶圓背側塗層黏著劑。
為防止薄化晶粒在切割操作期間破裂,可部分地切刻切 割線,或出於促進隨後單體化之目的,將切割線雷射至毗鄰電路間之全厚度晶圓之頂部側中。在部分地切刻切割線之後,保護膠帶(亦稱為背部研磨膠帶)層壓至晶圓頂部側以保護電路,並自晶圓背側移除材料達切刻切割線之程度。在移除保護膠帶之後,此方法產生單體化晶粒而無需切割薄化晶圓,且稱該方法為研磨前切割。
此方法之一個缺點係在將黏著劑施加至已單體化成個別晶粒之晶圓背部後,施加黏著劑(例如膜)之晶圓可需要進一步切割。或者,若施加晶圓背側塗層黏著劑,則塗層將進入並污染切割線或切割道,此干擾分離過程且潛在地污染晶片之前側。若在實施磨碎操作之前實施部分地切割操作以薄化晶圓,則此使得需要防止晶圓背側塗層污染至電路間之切割線中之構件。
本發明係關於自半導體晶圓製備半導體晶粒之方法,該半導體晶圓在晶圓頂部側上具有複數個由切割線隔開之製造區域且在晶圓背側上具有黏著劑塗層,該方法包含:將斥性材料施加至其中不欲印刷黏著劑塗層之製造區域及切割線;將黏著劑塗層施加至晶圓背側;移除斥性材料;及沿切割線將晶圓分成個別晶粒。在本說明書及申請專利範圍內,術語「製造區域」應包括電路、穿透矽通孔、微凸塊及半導體上之其他製造元件。
本發明之實質係使用斥性材料來阻止切割線及製造區域 被製造方法中所用黏著劑及塗層且具體而言晶圓背側塗層污染。在自半導體晶圓製備個別半導體晶粒之典型方法中,製造在晶圓頂部表面上具有電路且在一些實施例中具有穿透矽通孔、微凸塊及其他元件之晶圓;在欲發生單體化成個別晶粒之彼等區中將切割線或切割道劃線至毗鄰製造區域間之表面中。
若欲薄化晶圓,則將保護膠帶(稱為背部研磨膠帶)層壓至晶圓之頂部表面上來保護製造區域,並將晶圓之背側薄化至預定深度。
在下一階段,將晶圓背側黏著劑或塗層施加至晶圓背側並將其B階段化。B階段化係用於將黏著劑或塗層部分地固化或將溶劑蒸發掉以使黏著劑變硬而不固化之術語。
為製備用於切割之晶圓,將支撐切割膠帶施加至經B階段化之黏著劑或塗層上之晶圓背側,移除背部研磨膠帶,並將晶圓分成個別晶粒。可藉由刀片或雷射切割進行分離,或在一些實施例中,藉由拉伸切割膠帶來機械地分離晶粒進行分離。
在本發明中,將用以排斥黏著劑背側塗層之材料以足夠塞住切割線之量施加至切割線中及晶圓之頂部表面上,之後將背部研磨保護膠帶層壓至晶圓之頂部側。使黏著劑斥性材料變硬或固定,且然後將背部研磨保護膠帶層壓至晶圓頂部側上及變硬的黏著劑斥性材料上。
薄化晶圓,並將黏著劑塗層施加至晶圓背側。黏著劑背側塗層受黏著劑斥性材料排斥且將不會進入切割道或彼等 施加斥性材料之區。將黏著劑晶圓背側塗層B階段化並將切割膠帶施加於經B階段化黏著劑之頂部上。自晶圓之頂部側移除背部研磨保護膠帶,且現在自晶圓之頂部側清潔斥性材料。隨後可沿切割線將晶圓分成個別晶粒。
根據工業文獻中充分記載之半導體製造方法使得在晶圓之頂部側上形成複數個電路。晶圓係半導體材料,通常係矽。電路可形成於晶圓頂部表面之下方、其上或上方,且可藉由塗層(例如鈍化層)保護。在個別電路間形成於晶圓之頂部側中之切割線亦稱為切割道或溝槽。該等切割線可在電路形成之前形成或與其同時形成。形成切割線之方式包括(例如)濕式或乾式蝕刻及雷射鑽孔。切割線之目的係促進並引導晶圓切割成個別半導體晶粒。
將黏著劑斥性材料施加至切割線及製造區域中以排斥稍後施加之晶圓背側塗層並防止其進入不期望區域中。黏著劑斥性材料經選擇以使其排斥所選欲作為黏著劑施加至晶圓背側之晶圓背側塗層。黏著劑斥性材料係以有效保護切割道及製造區域之量施加,且可係水溶性或有機溶劑可溶性斥性材料。
適宜水溶性斥性材料包括選自由以下組成之群之親水性聚合物:聚乙烯醇、水溶性纖維素、明膠、澱粉及多糖、聚氧化乙烯、聚乙烯吡咯啶酮、磺化聚苯乙烯及衍生自含有親水性基團之烯系不飽和單體之聚合物。適宜有機溶劑可溶性斥性材料選自由以下組成之群:蠟及氟化蠟;固體氫化油;聚烯烴;丙烯酸酯、甲基丙烯酸酯及苯乙烯聚合 物;及聚矽氧化合物。
在一實施例中,斥性材料係包含以下之組合物A之反應產物:(i)一或多種可交聯聚有機矽氧烷,其固化時形成彈性體;及(ii)聚合粒子,其分佈於該一或多種可交聯聚有機矽氧烷內,其在固化彈性體中保持不連續,且其具有低於固化彈性體之降解溫度之熔融溫度。
如本發明中所用術語聚合粒子之「熔融溫度」較佳地係指聚合粒子經歷自固體至液體之狀態改變之溫度。可藉由DSC測定熔融溫度,其中將熔融溫度定義為DSC曲線之反曲點。
如本發明中所用術語固化彈性體之「降解溫度」係指彈性體經歷超過10 wt.-%、較佳地超過20 wt.-%之重量損失之溫度。可藉由TGA(熱重分析)來測定降解溫度。
有用之聚合粒子係聚合粉末,其中聚合粒子較佳選自聚烯烴及/或共聚烯烴,例如聚乙烯、聚丙烯、聚乙烯-共-丙烯、聚丁二烯、聚己內酯、同排聚(1-丁烯)、對排聚丙烯、聚(1-癸烯)、聚(乙烯-共-1-丁烯)、聚(乙烯-共-乙酸乙烯酯)、聚(丁烯己二酸)、聚(α-甲基苯乙烯-共-甲基苯乙烯)、聚氧化乙烯、反式-1,4-聚丁二烯或反式-1,4-聚異戊二烯。
本發明聚合粒子之粒徑可在寬範圍內變化,例如自50 nm至高達約100 μm。在一實施例中,聚合粒子具有約5 μm至約10 μm之大小範圍。可藉由雷射繞射使用Mastersizer 2000(由Malvern instruments有限公司製造,根 據Mie計算)來測定粒徑。
如本發明中所用術語「粒徑」係指d50體積平均粒子直徑。將d50體積平均粒子直徑定義為50體積%之粒子具有比d50值大之直徑之粒子直徑。
聚合粒子係以保持形狀之量、較佳地以基於可固化組合物A之總量1重量%至80重量%之量、更佳地以20重量%至60重量%之量且尤佳地以30重量%至50重量%之量分佈於組合物A之可交聯聚有機矽氧烷內。
在另一實施例中,本發明方法中所使用之形狀記憶型聚合物係包含以下之組合物B之固化產物:(i)一或多種固化時形成彈性體之可交聯聚有機矽氧烷及(ii)一或多種(甲基)丙烯酸酯。
如本文中所用術語「(甲基)丙烯酸酯」意欲包括甲基丙烯酸酯及丙烯酸酯,且除非另有特別說明,否則在提及甲基丙烯酸酯或丙烯酸酯中之一者時亦意欲涵蓋另一者。
將(甲基)丙烯酸酯(此處係液體填充物)納入可固化組合物B中,隨後固化(甲基)丙烯酸酯,此導致相分離,藉此在組合物B之固化產物中形成聚合(甲基)丙烯酸酯域。
(甲基)丙烯酸酯可選自多種化合物。可用作組合物B中之液體填充物之合意類別之(甲基)丙烯酸酯包括多-及/或單-官能(甲基)丙烯酸酯。可用於本發明之一類(甲基)丙烯酸酯具有一般結構: 其中Ra係H、鹵素或C1至C20烴基;且Rb係H或C1至C20烴基。合意地,Rb係至少C4或更高。
如本文中所用術語「烴基」(烴基團)意欲分別指主要由碳及氫原子組成之具支鏈及無支鏈之基團或雙自由基(diradical)。因此,該等術語涵蓋脂肪族基團,例如烷基、烯基及炔基;芳香族基團,例如苯基;及脂環族基團,例如環烷基及環烯基。本發明烴基可以雜原子不減損基團之烴性質之程度包括雜原子。因此,烴基可包括諸如醚、烷氧化物(alkoxide)、羰基、酯、胺基、氰基、硫化物、硫酸鹽、亞碸、碸及碸基等官能基。
本發明之烴基團及雙自由基可視情況取代至取代基不減損烴基之烴性質之程度。如本文中所用術語「視情況經取代」欲指基團上之一或多個氫可經相應數目之較佳地選自以下之取代基替代:鹵素、硝基、疊氮基、胺基、羰基、酯、氰基、硫化物、硫酸鹽、亞碸、碸及/或碸基。
組合物B之其他合意(甲基)丙烯酸酯係具有一般結構之胺基甲酸酯(甲基)丙烯酸酯: 其中Rc係H、C1至C4烷基或鹵素;Rd係(i)C1至C8羥基伸烷 基或胺基伸烷基,或(ii)C1至C6烷基胺基-C1至C8伸烷基、羥基伸苯基、胺基伸苯基、羥基萘或胺基-萘,其視情況由C1至C3烷基、C1至C3烷基胺基或二-C1至C3烷基胺基取代;且Re係C2至C20伸烷基、C2至C20伸烯基或C2至C20伸環烷基、C6至C40伸芳基、伸烷芳基、C2至C40伸芳烷芳基、C2至C40烷基氧基伸烷基或C2至C40芳基氧基伸芳基,其視情況由1個至4個鹵素原子或由1個至3個胺基或單-或二-C1至C3烷基胺基或C1至C3烷氧基取代。
其他合意(甲基)丙烯酸酯包括(但不限於)一般結構內之胺基甲酸酯(甲基)丙烯酸酯: 其中Rc、Rd及Re係如上文中所闡述,且Rf係藉由自具有至少2個胺基或羥基之聚胺或多元醇移除w個胺基或羥基所獲得之w價殘基;X係O或NRg,其中Rg係H或C1至C7烷基;且w係2至20之整數。
適宜單官能(甲基)丙烯酸酯選自(甲基)丙烯酸異莰基酯、(甲基)丙烯酸金剛烷基酯、(甲基)丙烯酸二環戊烯基酯、(甲基)丙烯酸三甲基環己基酯、(甲基)丙烯酸環己基酯、(甲基)丙烯酸正辛基酯、(甲基)丙烯酸異辛基酯、(甲基)丙烯酸正壬基酯、(甲基)丙烯酸異壬基酯、(甲基)丙烯酸正癸基酯、(甲基)丙烯酸異癸基酯、(甲基)丙烯酸正十一烷基酯、(甲基)丙烯酸異十一烷基酯、(甲基)丙烯酸正 十二烷基酯、(甲基)丙烯酸異十二烷基酯、2(2-乙氧基乙氧基)乙基丙烯酸酯及/或其組合。
有利地,(甲基)丙烯酸酯可係丙烯酸異莰基酯、丙烯酸異辛基酯及/或丙烯酸2(2-乙氧基乙氧基)乙基異癸基酯。
在一較佳實施例中,組合物B之(甲基)丙烯酸酯組份包含以下組合:(甲基)丙烯酸異莰基酯與(甲基)丙烯酸正癸基酯、(甲基)丙烯酸異莰基酯與(甲基)丙烯酸異癸基酯、(甲基)丙烯酸異莰基酯與(甲基)丙烯酸正十一烷基酯、(甲基)丙烯酸異莰基酯與(甲基)丙烯酸異十一烷基酯、(甲基)丙烯酸異莰基酯與(甲基)丙烯酸正十二烷基酯或(甲基)丙烯酸異莰基酯與(甲基)丙烯酸異十二烷基酯。
合意的特定多官能(甲基)丙烯酸酯包括聚乙二醇二甲基丙烯酸酯及二丙二醇二甲基丙烯酸酯。
其他合意(甲基)丙烯酸酯選自雙酚A之丙烯酸酯、甲基丙烯酸酯及甲基丙烯酸縮水甘油基酯。在所提及之該等自由基可聚合組份中,合意者係乙氧基化雙酚-A-二甲基丙烯酸酯(「EBIPMA」)。
上文所提及之(甲基)丙烯酸酯中之任一者之混合物可用於組合物B中。
可以佔總組合物B之至少5重量%之量添加一或多種(甲基)丙烯酸酯。合意地,一或多種(甲基)丙烯酸酯係以佔總組合物B之15重量%至80重量%之量存在,且更合意地以佔總組合物B之20%重量至70重量%之量存在。
如上文所提及,組合物A以及組合物B包含一或多種固 化時形成彈性體之可交聯聚有機矽氧烷。
本發明方法中所用之可交聯聚有機矽氧烷較佳選自可固化聚矽氧組合物。可採用各種類型之可固化聚矽氧組合物。舉例而言,可採用熱固化聚矽氧組合物、濕固化聚矽氧組合物及光固化聚矽氧組合物。多模態固化聚矽氧組合物,例如光及濕雙重固化組合物或熱及濕雙重固化聚矽氧組合物亦有用。
適宜可交聯聚有機矽氧烷選自式(I)化合物, 其中R1、R2及R5彼此獨立地選自氫、C1-20烷基、C1-20烷氧基或C1-20醯基;且R3 其中R6係C1-20烴基,且R4係H或C1-4烷基。
在另一實施例中,可交聯聚有機矽氧烷選自式(II)化合物: 其中MA係甲基丙烯醯氧基丙基,n係自1至1200,且c係0或1;且每一R5彼此獨立地係C1-20烴基或C1-20羥羧基 (hydrocarboxyl)。
上述R1、R2、R3及R5基團之實例係烷基(例如甲基、丙基、丁基及戊基)、烯基(例如乙烯基及烯丙基)、環烷基(例如環己基及環庚基)、芳基(例如苯基)、芳基烷基(例如β苯基乙基)、烷基芳基及烴氧基(例如烷氧基、芳基氧基、烷芳基氧基、芳烷氧基、且具體而言係甲氧基、乙氧基或羥基)。任一上述基團之一些或所有氫原子可由鹵素(例如氟或氯)取代。
可交聯聚有機矽氧烷中之重複單元之數量可經改變以達到特定分子量、黏度及其他化學或物理特性。
基於可固化組合物A之總重量或基於可固化組合物B之總重量,可交聯聚有機矽氧烷可以約20重量%至約95重量%之量存在。
除可交聯聚有機矽氧烷之外,組合物A及/或組合物B可包括一或多種矽氫化物交聯劑及/或一或多種有機金屬矽氫化觸媒。
在一實施例中,矽氫化物交聯劑選自式(III)化合物 其中R7、R9及R10中之至少兩者係H;另外R、R7、R9及R10相同或不同,且係C1-20烴基,較佳地甲基;x係10至1000之整數;且y係1至20之整數。
一或多種矽氫化物交聯劑可以足夠達成期望交聯量之量 存在,且在一實施例中,基於組合物A之總重量或基於組合物B之總重量以1重量%至10重量%之量存在。
有用之有機金屬矽氫化觸媒可選自任一對起始熱矽氫化固化反應有效之貴金屬觸媒或含貴金屬之觸媒。尤其有用者係鉑及銠觸媒,其有效催化聚矽氧鍵結之氫原子與聚矽氧鍵結之烯基之間之加成反應。本發明中有用之其他類別之觸媒包括有機銠及鉑醇鹽。亦涵蓋釕、鈀、鋨及銥之錯合物。
可以任一有效量使用一或多種有機金屬矽氫化觸媒以實現熱固化。在一實施例中,基於組合物A之總重量或基於組合物B之總重量,觸媒係以0.025重量%至1.0重量%之量存在。
端視組合物A或B之可交聯聚有機矽氧烷組份之化學性質而定且端視預期固化機制而定,該等組合物A或B之中每一者可包括一或多種起始劑,其中術語「起始劑」及「觸媒」在本發明中可互換使用。
適用於本方法中之起始劑包括濕固化起始劑、光起始劑、自由基起始劑、熱固化觸媒及/或其組合。
一或多種起始劑(各自基於組合物A或組合物B之總重量)可以0.01重量%至10重量%之量、較佳地以0.1重量%至5重量%之量存於組合物A或組合物B中。
可採用多種光起始劑作為組合物A及/或組合物B之部分。本發明方法中可使用任一已知之促進交聯之自由基類型光起始劑。當光可固化組合物作為整體暴露於電磁輻射 時,光起始劑提高固化處理之快速性。
可用於組合物A及/或組合物B中之UV光起始劑之非限制性實例包括丙酮酸鹽、苯乙酮、氧化膦、安息香、二苯甲酮、二烷氧基-二苯甲酮、米其勒酮(Michler's ketone,4,4'-雙(二甲基胺基)二苯甲酮))、二乙氧基苯乙酮及/或其任一組合。
在本發明另一實施例中,本發明方法中所使用之形狀記憶型膜係包含以下之組合物C之固化產物:(i)一或多種選自芳香族環氧樹脂、脂肪族環氧樹脂及/或其組合之環氧樹脂;及(ii)一或多種選自多胺、多羧酸及酐及/或其組合之交聯劑。
適宜芳香族環氧樹脂包括芳香族二環氧化物,例如以商品名EPON 826購自Hexion Speciality Chemicals之雙酚A之二縮水甘油基醚。
適宜脂肪族環氧樹脂包括脂肪族二環氧化物,例如購自TCI America之新戊二醇二縮水甘油基醚(NGDE)。
在尤佳實施例中,組合物C包含一或多種芳香族環氧樹脂與一或多種脂肪族環氧樹脂之組合,其中雙酚A之二縮水甘油基醚與新戊二醇二縮水甘油基醚(NGDE)之混合物用作組合物C之環氧樹脂組份。
如本發明中所用術語「多胺」係指具有至少2個胺基之化合物,而如本發明中所用術語「多羧酸」係指具有至少2個羧酸基之化合物。
適於組合物C之起始劑包括烷氧基化二胺或三胺,例如 以商品名Jeffamine D-230購自Hexion Specialty Chemicals and Huntsman之聚(丙二醇)雙(2-胺基丙基)醚。
可根據任一方法製備本發明方法中所使用之形狀記憶型聚合物膜。製備該形狀記憶型聚合物膜之尤佳方法闡述於美國專利申請案第2004/0266940 A1號、第2008/0064815 A1號及第2008/0262188 A1號中,每一者之揭示內容之全文皆以引用方式明確地併入本文中。
將斥性化合物溶解於適當溶劑(水或有機溶劑)中,並藉由任一有效方法(舉例而言,藉由旋塗、絲網或模版印刷或較佳地藉由噴霧或噴墨印刷)施加。溶液濃度可盡可能高,但只能高達將容許成功施加之程度。然後在繼續進行接下來的步驟之前將水或溶劑蒸發掉,此使得斥性材料變硬。
將保護層層壓至晶圓之頂部側上及斥性材料上方,以在隨後晶圓薄化步驟期間保護電路且在切割晶圓後使電路保持適當位置。保護層通常呈膠帶形式,且在特定實施例中呈UV膠帶形式。最初,黏著劑發黏,且然後當輻照時變硬從而易於釋放。
可使用任一有效使晶圓變薄之方法。在特定實施例中,使晶圓背側經受研磨操作。通常,實施此背部研磨至滿足切割線深度之程度。在一些操作中,將切割線在晶圓前側中切刻得與背側研磨之目標深度相比略深。此稍略過度切刻促進個別晶粒之最後分離。
在背側薄化操作之後,將黏著劑塗層施加至晶圓背側。 此黏著劑晶圓背側塗層用於將個別晶粒附接至其基板。藉由任一有效方法(例如藉由旋塗、絲網或模板印刷或噴霧或噴墨印刷)來實施晶圓背側塗層之施加。晶圓背側塗層之化學組合物係任一將滿足隨後處理需求之黏著劑。該等黏著劑已為業內所知。在一實施例中,晶圓背側塗層係可進行B階段化之液體,此意指其可經加熱以移除溶劑或經UV光起始以部分地固化。在進行B階段化之後,晶圓背側塗層在室溫下相對不黏。在隨後晶粒附接操作中,塗層可經加熱以在晶粒附接期間軟化並流動,且然後可於高溫下加熱進行最終固化。
在此實施例中,晶圓背側塗層之化學性質經選取以使其可經B階段化,且使製造區域中之斥性材料將能夠排斥晶圓背側塗層黏著劑。
在另一實施例中,晶圓背側塗層之組成經選取以使其固化至更脆狀態。此脆性狀態使得背側塗層在個別晶粒之單體化期間破碎(而非機械鋸割或雷射)。
出於隨後處置目的,將支撐膠帶施加於晶圓背側上之B階段化塗層的頂部上。之後,自晶圓頂部側移除保護(背部研磨)膠帶。
然後自製造區域移除斥性材料。若此材料係水溶性材料,用水洗滌晶圓表面直至移除材料之所有痕跡為止。若此材料係溶劑溶性材料,使用用於溶解該材料之適當溶劑清潔表面直至移除材料之所有痕跡為止。在一些使用上文所闡述聚矽氧彈性體組合物之實施例中,斥性材料以機械 方式且容易地自製造區域及切割道釋放。
最終,沿切割線將晶圓分成個別電路。可藉由用刀片鋸割、用雷射燃燒,藉由拉伸晶圓背側塗層(若其以脆性材料形式提供)或藉由部分鋸割或雷射燃燒及拉伸之組合來進行此分離。
斥性材料在此方法中之用途係排斥晶圓背側塗層黏著劑自製造區域離開,從而防止污染。

Claims (6)

  1. 一種自半導體晶圓製備半導體晶粒之方法,該半導體晶圓在該晶圓之頂部側上具有複數個由切割線隔開之製造區域,且在該晶圓之背側上具有黏著劑塗層,該方法包含:部分地切割該晶圓至一深度以在該晶圓之頂部側上形成製造區域及切割線;在該晶圓之頂部側上施加斥性材料至不欲印刷該黏著劑塗層之該等製造區域及經部分地切割而得之切割線以形成塞住之切割線;將背部研磨膠帶附接至該晶圓之頂部側及背部研磨該晶圓之背側至滿足該塞住之切割線之深度;將該黏著劑塗層施加至該晶圓之該背側,其中該斥性材料排斥該黏著劑塗層之施加;部分地固化該黏著劑塗層;將切割膠帶施加至該部分地固化之黏著劑塗層及移除該背部研磨膠帶;自該等製造區域及塞住之切割線移除該斥性材料;及沿該等切割線將該晶圓分離成個別晶粒。
  2. 如請求項1之方法,其中該斥性材料係選自由以下組成之群之水溶性斥性材料:聚乙烯醇、水溶性纖維素、明膠、澱粉及多糖、聚氧化乙烯、聚乙烯吡咯啶酮、磺化聚苯乙烯及衍生自含親水性基團之烯系不飽和單體之聚合物。
  3. 如請求項1之方法,其中該斥性材料係選自由以下組成之群之有機溶劑可溶性斥性材料:蠟及氟化蠟、固體氫化油、聚烯烴、丙烯酸酯、甲基丙烯酸酯、苯乙烯聚合物及聚矽氧化合物。
  4. 如請求項1之方法,其中該斥性材料係包含以下之組合物之反應產物:(i)一或多種可交聯聚有機矽氧烷,其固化時形成彈性體,及ii)聚合粒子,其分佈於該一或多種可交聯聚有機矽氧烷內,其在該固化彈性體中保持不連續,且其具有低於該固化彈性體之降解溫度之熔融溫度。
  5. 如請求項1之方法,其中該斥性材料係包含以下之組合物之反應產物(i)一或多種可交聯聚有機矽氧烷,其固化時形成彈性體,及ii)一或多種(甲基)丙烯酸酯。
  6. 如請求項1之方法,其中該斥性材料係包含以下之組合物之反應產物(i)一或多種環氧樹脂,其選自芳香族環氧樹脂、脂肪族環氧樹脂及/或其組合,及(ii)一或多種交聯劑,其選自多胺、多羧酸及酐及/或其組合。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6147631B2 (ja) * 2013-09-26 2017-06-14 株式会社ディスコ 加工方法
US10276440B2 (en) 2017-01-19 2019-04-30 Honeywell International Inc. Removable temporary protective layers for use in semiconductor manufacturing
US11610817B2 (en) 2021-03-19 2023-03-21 Infineon Technologies Austria Ag Method of processing a semiconductor wafer, semiconductor wafer, and semiconductor die produced from a semiconductor wafer
JP2024010412A (ja) * 2022-07-12 2024-01-24 日東電工株式会社 保護シート

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62152672A (ja) 1985-12-27 1987-07-07 Mitsubishi Heavy Ind Ltd シリコンウエハの加工治具への着脱方法
JPH0665447A (ja) * 1992-08-24 1994-03-08 Nisshin Chem Ind Co Ltd ポリプロピレン系樹脂組成物
JP4681704B2 (ja) 1999-12-16 2011-05-11 株式会社ディスコ 半導体ウェーハの分割方法
DE10121556A1 (de) 2001-05-03 2002-11-14 Infineon Technologies Ag Verfahren zum Rückseitenschleifen von Wafern
US6582983B1 (en) * 2002-07-12 2003-06-24 Keteca Singapore Singapore Method and wafer for maintaining ultra clean bonding pads on a wafer
JP2004153193A (ja) * 2002-11-01 2004-05-27 Disco Abrasive Syst Ltd 半導体ウエーハの処理方法
US7230047B2 (en) * 2003-06-25 2007-06-12 Henkel Corporation Reformable compositions
JP4170839B2 (ja) * 2003-07-11 2008-10-22 日東電工株式会社 積層シート
JP2005191550A (ja) * 2003-12-01 2005-07-14 Tokyo Ohka Kogyo Co Ltd 基板の貼り付け方法
US7074695B2 (en) 2004-03-02 2006-07-11 Chippac, Inc. DBG system and method with adhesive layer severing
US7226812B2 (en) 2004-03-31 2007-06-05 Intel Corporation Wafer support and release in wafer processing
US20060046433A1 (en) 2004-08-25 2006-03-02 Sterrett Terry L Thinning semiconductor wafers
JP2006120834A (ja) * 2004-10-21 2006-05-11 Disco Abrasive Syst Ltd ウェーハの分割方法
JP4571850B2 (ja) * 2004-11-12 2010-10-27 東京応化工業株式会社 レーザーダイシング用保護膜剤及び該保護膜剤を用いたウエーハの加工方法
US7452957B2 (en) * 2005-08-31 2008-11-18 Kimberly-Clark Worldwide, Inc. Hydrophilic silicone elastomers
JP4847199B2 (ja) * 2006-04-25 2011-12-28 株式会社ディスコ ウエーハに装着された接着フィルムの破断方法
WO2008001706A1 (fr) * 2006-06-29 2008-01-03 Asahi Kasei Emd Corporation Procédé pour la fabrication d'une lentille en plastique
US20080027199A1 (en) 2006-07-28 2008-01-31 3M Innovative Properties Company Shape memory polymer articles with a microstructured surface
US20080064815A1 (en) 2006-09-12 2008-03-13 Henkel Corporation Reinforcement and Cure Enhancement of Curable Resins
EP2067800A4 (en) * 2006-09-29 2010-02-24 Asahi Kasei Emd Corp POLYORGANOSILOXANE COMPOSITION
WO2008069805A1 (en) * 2006-12-08 2008-06-12 Henkel Ag & Co. Kgaa Process for coating a bumped semiconductor wafer
JP5238927B2 (ja) * 2007-03-14 2013-07-17 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置の製造方法
KR100871707B1 (ko) * 2007-03-30 2008-12-05 삼성전자주식회사 깨짐을 억제하는 몰딩부를 갖는 웨이퍼 레벨 패키지 및 그제조방법
US8618238B2 (en) * 2007-04-20 2013-12-31 GM Global Technology Operations LLC Shape memory epoxy polymers
CN101560286B (zh) * 2007-10-04 2013-11-06 通用汽车环球科技运作公司 形状记忆的环氧化物聚合物
US7655539B2 (en) * 2008-04-16 2010-02-02 Fairchild Semiconductor Corporation Dice by grind for back surface metallized dies
TW200952059A (en) * 2008-06-10 2009-12-16 Henkel Corp Methods for coating the backside of semiconductor wafers
US8232140B2 (en) * 2009-03-27 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for ultra thin wafer handling and processing
JP5442308B2 (ja) * 2009-04-22 2014-03-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TW201104736A (en) 2009-04-24 2011-02-01 Henkel Corp Dicing before grinding process for preparation of semiconductor
TW201208071A (en) 2010-04-13 2012-02-16 Henkel Ag & Amp Co Kgaa Method for handling a wafer
JP2011233711A (ja) * 2010-04-27 2011-11-17 Toshiba Corp 半導体装置の製造方法
TW201312683A (zh) 2011-07-01 2013-03-16 Henkel Ag & Co Kgaa 處理晶圓之方法

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