CN1300840C - 利用垂直连接的芯片和晶片集成工艺 - Google Patents

利用垂直连接的芯片和晶片集成工艺 Download PDF

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Publication number
CN1300840C
CN1300840C CNB028234030A CN02823403A CN1300840C CN 1300840 C CN1300840 C CN 1300840C CN B028234030 A CNB028234030 A CN B028234030A CN 02823403 A CN02823403 A CN 02823403A CN 1300840 C CN1300840 C CN 1300840C
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chip
layer
welding disk
substrate
wafer
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CN1592965A (zh
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伯恩哈德·H·波格
罗伊·尤
钱德里卡·普拉萨德
钱德拉塞卡尔·纳拉扬
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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Abstract

描述了一种用于芯片级或者晶片级半导体器件集成的工艺，其中穿过衬底(1)形成垂直连接。在衬底的顶表面中形成金属化部件(2)，处理板(35)附着于衬底。然后在衬底的底表面处减薄该衬底，以露出该部件的底部，从而形成导电贯通孔(20)。该衬底可以包括具有器件(30)的芯片(44)，例如PE芯片。该板可以是利用垂直导电棒/通路互连附着于该衬底的晶片(65)。该衬底和板每个都可以具有在其内制造的器件(30，60)，使得该工艺提供了器件的垂直晶片级集成。

Description

利用垂直连接的芯片和晶片集成工艺
技术领域
本发明涉及集成电路器件的制造。更具体地说，本申请涉及用于其中形成了垂直互连的芯片级和晶片级集成的工艺。
背景技术
对半导体器件中较高的功能性和性能的需求已经推动了更大和更复杂芯片的发展。此外，经常希望在一个芯片上包括几个不同的功能，以得到“单片系统”，这种情况通常导致芯片尺寸增加和制造工艺更复杂。这些因素趋于降低制造产品合格率。估计面积大于400mm2的许多这种复杂芯片通常具有非常低的制造合格率(也许10％以下)。
保持可接受合格率的一种方法是制造较小的芯片、然后在芯片上或者支撑衬底上利用水平和垂直连接互连这些芯片。互连的芯片由此在衬底上或者芯片载体上形成安装在另一个芯片上的一个较大的芯片。除了提高制造合格率，这种方案的另一个主要优点在于：单个芯片可以具不同尺寸、执行不同的功能，或者可以通过不同或者不兼容的方法制造。
图1A示意性地示出了根据本方案构成的系统。衬底或者底部芯片11具有安装在其上的几个芯片10，水平间隔为Δx和Δy。例如，底部芯片11可以是DRAM(动态随机存取存储器)芯片，而四个芯片10为处理器(或者“处理器引擎(PE)”)芯片。
为了实现由单片系统(SOC)理念提供的优点，最好是不同的芯片非常接近并且相对于彼此非常精确地对准。例如，芯片10之间的间隔Δx和Δy最好是大约为50μm或者更小。
可以通过使用导体棒/通路(stud/via)互连而非常高精确地(大约1μm内)将芯片10放置在衬底或者底部芯片11上，如图1B所示意。在图1B中，芯片10具有形成在芯片的端子表面上的金属导体棒12，低熔点合金材料层16淀积在导体棒的表面上。在底部芯片11表面上的介质层17(通常设计并且制造为聚酰亚胺的多层结构)中嵌入高密度布线18(通常为几层Cu导体，如果在图1b中示意的)，并且在层17的表面上具有电接合焊盘15。介质层14位于布线层17上；层14可以由通常用在薄膜封装工艺中的聚酰亚胺材料形成。层14具有形成在其内的通路13(例如通过反应离子蚀刻、光刻或者准分子激光)，使得端子金属接合焊盘15位于每个通路底部。该通路可以形成有倾斜的壁角，作为在通路13中高精度、自对准地放置导电棒12的引导器。可以在介质层14的顶部淀积热塑性聚合物粘合剂薄涂层19，以确保与芯片表面的可靠粘接。在美国专利No.6,444,560、名称为“Process formaking fine pitch connections between devices and structure made bythe process”中提供了这种导电棒/通路对准和结合工艺的细节，这里引入其公开的内容作为参考。与目前的C4互连方案相比，使用自对准导电棒/通路互连允许具有极高的布线密度。
在图1A所示的SOC中，布线层横向延伸到芯片10的区域之外。通常在底部芯片11的顶表面的周边11a进行外部连接。因此SOC的整个尺寸限制了可以获得的用于进行外部连接的导线连接的空间。我们希望改为通过芯片的背面进行外部连接，使得连接不受导线连接空间的限制。在芯片的背面10b上形成连接焊盘(例如C4焊盘)需要垂直穿过芯片体到达芯片的器件面(表面10a)进行电连接。此外，建立穿过器件芯片的垂直互连将便于芯片的垂直层叠，有效地将SOC理念延伸到三维。
因此，需要一种在多芯片器件例如SOC中制造垂直互连的工艺，这种多芯片器件能够允许三维芯片互连，并且能够以高制造合格率实施。
发明内容
本发明通过提供一种用于芯片级或者晶片级垂直集成的工艺致力于满足上述需求，其中利用芯片中的贯通孔(through-via)形成垂直连接。
根据本发明的第一方面，提供一种制造半导体结构的方法。在衬底的顶表面上形成部件，将金属淀积在该部件中以制备导电通路(via)。可以首先在该部件中淀积衬垫以隔离金属与半导体材料。然后形成位于该衬底顶表面上的层；该层包括导电体和该层顶表面上的第一导电焊盘，使得该第一导电焊盘与该部件电连接。将板附着于该层上，然后在衬底的底部减薄该衬底以露出该部件的底部。在衬底的底表面上形成第二导电焊盘，以便与该部件的底部进行电连接，使得第一导电焊盘和第二导电焊盘通过该部件电连接。
该衬底可以包括其中制造有器件(例如DRAM)的芯片。因此在该芯片中的贯通孔中的导电通路的形成允许与第二芯片(例如PE芯片)垂直集成。
该板可以是临时处理板，以便于衬底的减薄。如果该板对消蚀照射(ablating radiation)是透明的，那么便于通过消蚀该层与该板之间的界面除去该板。
根据本发明的另一方面，该板是不从衬底上除去的半导体晶片；该晶片利用垂直导电棒/通路互连附着于衬底上。在上述层上形成覆盖该衬底的第二层，在第二层中形成通路，露出第一导电焊盘。在半导体晶片上形成与通路对准的导电棒；然后使该晶片与第二层接触，使得导电棒与第一导电焊盘电连接。因此，该衬底和该板(导电体晶片)形成晶片系统，并且该衬底和该板每个都可以具有制造在其内的器件(例如分别为DRAM和PE器件)。这样该工艺提供了器件的垂直晶片级集成。
根据本发明的另一方面，提供一种半导体结构，包括：衬底；覆盖该衬底顶表面的第一层；第一层顶上和该衬底底表面上的导电焊盘；第一层上的第二层；和接触第一层的板。该衬底具有延伸通过的通路，第一导电体形成在该通路中。第一层包括连接第一导电体与该层顶上的导电焊盘的第二导电体。衬底底表面上的导电焊盘与第一导电体电连接，使得第一导电焊盘和第二导电焊盘电连接。第二层具有形成在其内以露出第一层顶上的导电焊盘的通路。该板具有形成在其上的导电棒，该导电棒与通路对准并且与导电焊盘电接触。
附图说明
图1A是单片系统示意图，其中较小的芯片设置在较大的芯片上，并且被非常接近地集成和连接。
图1B示出了用于图1A所示芯片的高精度、自对准导电棒/通路互连方案。
图2A-2F示出了根据本发明实施例用于形成穿过芯片体的垂直互连的工艺步骤。
图3A-3F示出了根据本发明实施例的利用垂直互连得到DRAM芯片和处理器(PE)芯片的芯片级集成的工艺步骤。
图3G示出了使用图3F的垂直互连的另一种芯片级集成。
图4A-4E示出了根据本发明的另一个实施例的利用垂直互连得到DRAM和PE晶片的晶片级集成的工艺步骤。
具体实施方式
根据本发明，制造包括穿过芯片的垂直电连接的半导体器件。这些垂直连接通过在该芯片中构成金属化的贯通孔形成，不需要昂贵的深通路蚀刻。
在下面讨论的实施例中，垂直连接了两个不同类型的芯片。具体地说，在所示的例子中，将DRAM芯片(或者硅DRAM器件晶片)垂直连接到多个PE芯片(或者硅PE器件晶片)上。应理解所讨论的这些类型的芯片仅用于说明，本发明可以利用各种芯片和晶片类型实施。
I.金属化通路的形成
如下所述，可以通过在沟槽中淀积金属并且减薄晶片以打开该沟槽的底部从而在半导体衬底例如硅晶片中形成金属化的贯通孔。
在硅晶片1中，在其内制造器件之前，在需要垂直连接的地方蚀刻沟槽2。如图2A所示，该沟槽不延伸穿透晶片，但应延伸到器件深度以下的体(bulk)Si中。在晶片上和沟槽中生长或者淀积氧化物层21。在该氧化物上最好是通过化学汽相淀积(CVD)淀积沟槽衬垫22，一般是钨。然后在衬垫22上淀积铜层23。(如本领域技术人员所了解的，当使用铜来金属化该沟槽时，需要衬垫；许多另外的不需要衬垫的金属化方案都是可行的)。层23的淀积方法是离子物理汽相淀积(IPVD)，以确保沟槽内部的薄的、共形涂层。
在沟槽中和晶片顶部上的层23上(例如通过电镀)形成铜层24。在沟槽的侧壁上生长层24，直至达到使该沟槽的上部封闭的厚度，如图2C所示。利用该结构，在沟槽的底部和晶片的顶部表面之间建立了导电通路，而空隙25残存在沟槽的底部附近。应注意，该空隙25在缓解由部件中及其周围的不同材料的热膨胀系数(TCE)差引起的应力方面具有重要的作用。
然后最好是通过化学-机械抛光(CMP)平整晶片，以从晶片的顶表面除去层21-24。得到的结构示于图2D。然后(通过反应溅射或者其它一些便利的工艺)将沟槽顶部的铜蚀刻到大约5μm的深度，以得到图2E所示的结构。在晶片上(最好是通过CVD)淀积钨层，再次利用CMP平整晶片，留下每个沟槽顶部的钨层26和硅晶片的暴露表面1p(图2F)。这样沟槽结构20具有埋在钨中的铜金属化。
然后准备利用该晶片在表面1p附近形成器件，并且进一步加工以得到芯片级或者晶片级集成。
II.芯片级集成
在形成了金属化的沟槽结构20之后，在晶片1中制造图3A所示意性示出的器件30。如图3A所示，器件位于与该晶片的顶表面相邻的晶片1的区域中。在本实施例中，器件30为DRAM器件。然后在晶片的顶部形成介质层31(一般是聚酰亚胺)；层31具有埋置在其内的高密度布线32a-32c，并且在其顶表面具有用于进行外部连接(例如与DRAM芯片顶部上的PE芯片连接)的电接合焊盘33。图3A示意性地示出了可能连接的例子。该电布线可以连接金属化通路与接合焊盘(导体32a)；器件与接合焊盘(导体32b)；或者器件与通路和/或接合焊盘(导体32c)。尽管将包括导体的层31示为单层，但是应理解为了容易制造，经常将其设计并制造为多层结构。通常将焊盘33形成为多层结构，该多层结构包括Ti-W合金、Ni和Au，但也可以包括Cu、Co或者金属的其它组合。
然后通过研磨、CMP或者其它一些便利的工艺减薄晶片1，使得在晶片1的底部表面1b或者背面露出金属化通路结构20的内部(图3B)。减薄的晶片可能难以处理或者与后续的晶片加工中所用的设备不兼容。因此，在进行减薄工序之前，尤其当晶片的最后厚度小于150μm时，希望将临时处理板附着于晶片上。在本实施例中，将晶片厚度减小到大约100μm或者更小。如图3B所示，利用粘接层36将玻璃板35附着于层31的顶表面上。
这里每个通路结构20都是在晶片的底表面1b上露出钨层22的贯通孔。在表面1b上淀积绝缘层37(例如，聚酰亚胺)，并且在其内的通路20的位置形成开口38。然后在层37上淀积金属层(或者多层的组合)并且构图以在开口38中及其周围形成金属焊盘39。焊盘39一般具有类似于焊盘33的结构；即包括Ti-W合金、Ni和Au的多层结构。得到的结构示于3C。
然后利用本领域已知的方法，在晶片背面上的焊盘39上形成焊料突起41。例如，可以将焊料膏通过丝网涂覆到晶片上，并且对淀积的焊料进行回流处理。图3D示出了准备好用于切割和接合到载体上的晶片结构。
在本实施例中，如图3E所示，将晶片切割为芯片44，同时使玻璃处理板35完好。另外，切割工艺可以包括切割板35(这样需要在接合工艺中对单个芯片进行处理)。将芯片接合到载体45；焊料突起41一般与载体顶表面处的金属焊盘(未示出)连接。载体45可以是另一个芯片、陶瓷衬底、电路板等。
接合工艺之后，从芯片上除去临时处理板35。如图3E所示意性地示出的，这可以方便地通过激光消蚀工艺进行。入射到玻璃板35上的激光辐射46穿透该板，并且消蚀该板和粘合剂层36之间的界面。这样导致该板与层36的分层，使得可以除去板35。然后清洗掉剩余的粘合剂，使接合焊盘33暴露。
如图3F所示，通过将PE芯片连接到DRAM芯片的接合焊片33完成DRAM芯片44和PE芯片54的垂直集成。在PE芯片54中，在晶片中制造处理器件50；PE芯片的其它部分根据与上述方法相同的方法制备，具有由图3F中重复的附图标记所表示的相同结构。特别是，值得注意的是可以使用芯片54顶表面上的接合焊盘33进行与垂直集成结构55的外部连接，该垂直集成结构55包括DRAM芯片和多个PE芯片。
另外，如图3G所示，该PE芯片可以是不具有垂直贯通孔连接的常规芯片56(具有在衬底52中的器件51和布线层31)。在这种情况下，该PE芯片56与芯片44(具有垂直贯通孔连接)接合，以形成集成结构57。
III.晶片级集成
在本发明的该实施例中，在晶片中形成金属化贯通孔，利用导电棒/通路互连将其与另一个晶片接合。
在图4A中，晶片1具有制造在其内的金属化沟槽结构20和器件30(例如，DRAM器件)，介质层31位于晶片的顶部上，介质层31包含电布线并且具有其上的焊盘33(比较图3A)。按上面参考图2A-2F所描述的方式形成沟槽结构。该晶片具有一般是聚酰亚胺层的覆盖层31的介质层61。层61具有形成在其内的通路开口62，以露出焊盘33。在前表面65f附近具有器件60(例如PE器件)的另一个晶片65具有形成在其上的介质层63，介质层63带有用于电连接到导电棒66的高密度布线。如图4A所示，器件60与导电棒66连接，并且导电棒对应于通路62。
然后通过导电棒66与焊盘33电连接从而将晶片1和晶片65结合到一起，如图4B所示。(如上面参考图1B所讨论的，利用导电棒上的焊料层和/或聚酰亚胺层上的粘合剂可以方便地进行粘接。)由此得到的晶片结构70包含互连的器件；应注意晶片1和65可以具有不同的器件类型(例如DRAM和PE器件)和/或不同的材料(Si、SiGe、GaAs等)。
与前面的实施例一样(图4C；比较图3B)，然后减薄晶片1，使得沟槽结构20变为贯通孔。应注意在减薄晶片1的同时，晶片65可以起到处理晶片的作用。另外，还可以处理晶片65以便具有延伸到背面65b的贯通孔；在这种情况下，在将晶片65粘接到晶片1之前，晶片65可能需要与后来除去的临时处理板(未示出)粘接。
与前面的实施例一样，在表面1b上淀积绝缘层37(例如聚酰亚胺)，并且其内形成开口38。然后形成焊盘39以便与贯通孔进行连接，并且将焊料突起41附着到焊盘上(图4D)。
然后切割晶片结构70以制造组合芯片74(例如组合的DRAM/PE芯片)，然后将组合芯片74接合到载体45上，如图4E所示。此时除去用于晶片65的临时处理板。应理解，如果晶片65具有到达背面65b的贯通孔，那么可以与芯片74顶表面进行电连接。因此，可以实现进一步的垂直集成。
工业实用性
本发明通常可应用于半导体器件制造，并且提供了一种用于器件集成的工艺，其中通过芯片背面的通路进行电连接，使得这些连接不受导线连接空间要求的限制。本发明所提供的显著优点在于，在衬底中形成贯通孔而不需要昂贵的深通路蚀刻工艺。可以非常高精确地保持通路尺寸，结果允许高密度的贯通孔。此外，与上面描述的高精确地横向放置芯片类似，使用垂直的导电棒/通路互连允许在第三维高精确地放置芯片。
虽然已经根据具体实施例描述了本发明，但鉴于前面的描述，很显然对于本领域技术人员来说许多选择、修改和变化都是显而易见的。因此，本发明包括落在本发明的范围和精神以及下面的权利要求内的所有这些选择、修改和变化。

Claims (12)

1.一种制造半导体结构的方法，该半导体结构包括具有顶表面和底表面的衬底，该方法包括步骤：
在衬底(1)的顶表面中形成部件(2)；
将金属(24)淀积在该部件中以在其内制备导电通路；
形成覆盖该衬底顶表面的层(31)；该层包括导电体(32a，32b，32c)和该层顶表面上的第一导电焊盘(33)，第一导电焊盘与该部件电连接；
将板(35)附着于该层上，
在衬底的底表面(1b)减薄该衬底，从而露出该部件的底部；和
在衬底的底表面上形成第二导电焊盘(39)，以便与该部件的底部进行电连接，使得第一导电焊盘和第二导电焊盘通过该部件电连接。
2.根据权利要求1的方法，进一步包括在与衬底顶表面相邻的衬底区域中制造半导体器件(30)的步骤。
3.根据权利要求1或2的方法，其特征在于，所述淀积步骤进一步包括淀积金属以在部件中形成空隙(25)。
4.根据权利要求1或2的方法，其特征在于，该半导体结构包括第一芯片(44)，第一芯片(44)具有连接第一导电焊盘和第二导电焊盘的穿通的垂直电连接，并且进一步包括步骤：
利用所述垂直电连接连接第二芯片(54)和第一芯片，使得在第一芯片的顶上设置第二芯片，以便垂直集成第一芯片和第二芯片。
5.根据权利要求4的方法，其特征在于，第一芯片包括DRAM器件(30)和第二芯片包括处理器(50)。
6.根据权利要求1的方法，其特征在于，所述减薄步骤包括减小衬底的厚度，直到小于100μm。
7.根据权利要求1的方法，其特征在于，该板(35)是临时处理板，并且进一步包括分离该板的步骤。
8.根据权利要求7的方法，其特征在于，该板对消蚀照射是透明的，和所述分离步骤包括利用透过该板的消蚀照射(36)消蚀该层和该板之间的界面。
9.根据权利要求4的方法，其特征在于，第二芯片(54)包括在所述第二芯片顶表面上的另一个垂直电连接和导电焊盘(33)。
10.根据权利要求1的方法，其中该板是半导体晶片(65)，覆盖衬底顶表面的该层(31)表征为第一层，所述附着该板的步骤包括下列步骤：
在第一层上形成第二层(61)；
在第二层中形成通路(62)，以露出第一导电焊盘(33)；
在半导体晶片上形成导电棒(66)；
将导电棒与通路对准；和
使半导体晶片与第二层接触，使得导电棒(66)与第一导电焊盘(33)电连接。
11.根据权利要求10的方法，进一步包括步骤：
在与衬底顶表面相邻的衬底区域中制造第一半导体器件(30)；和
在所述分离步骤之前，在半导体晶片中制造第二半导体器件(60)。
12.根据权利要求11的方法，其特征在于，第一半导体器件通过第一层与第一导电焊盘连接，和第二半导体器件与导电棒连接，以便提供其间的垂直电连接。
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