EP4154310A1

EP4154310A1 - Semiconductor die assembly and method of stacking semiconductor components

Info

Publication number: EP4154310A1
Application number: EP20735144.6A
Authority: EP
Inventors: Mustafa Badaroglu
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-06-25
Filing date: 2020-06-25
Publication date: 2023-03-29
Also published as: WO2021259477A1

Abstract

A method of stacking semiconductor components, to obtain a semiconductor wafer assembly, and for forming a semiconductor die assembly therefrom, is provided. The method comprises providing a first wafer comprising at least a first and a second die in a first and a second position, respectively; providing at least a third and a fourth die, to be stacked on the first and the second die, respectively; placing the third and fourth die on a carrier wafer in positions matching at least a part of the first and second position, respectively; applying insulating material on the carrier wafer outside of the third and the fourth dies; and placing the carrier wafer on the first wafer to obtain a first die stack of the first and third dies and a second die stack of the second and fourth dies, causing bonding of the first and third dies and the second and fourth dies, respectively.

Description

SEMICONDUCTOR DIE ASSEMBLY AND METHOD OF STACKING SEMICONDUCTOR COMPONENTS

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor technologies; and more specifically, to a semiconductor die assembly, formed from a semiconductor wafer assembly, and particularly to a method of stacking semiconductor components therein.

BACKGROUND

[0002] Since the invention of the integrated circuit (IC), the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components. For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.

[0003] Integrated circuits stacking is one of the main means of improving high-density integration of electronic packages. With the advancement in semiconductor technologies, there is rapid progress in integrated circuits (ICs), especially the three-dimensional (3D) integrated circuit. The three-dimensional integrated circuits are manufactured by vertically stacking semiconductor components such as multiple wafers and/or dies interconnected vertically. Such three-dimensional integrated circuits support different active integrated circuit devices so that they behave as a single integrated circuit device.

[0004] Conventionally, the multiple wafers and/or dies are stacked using a die-to-wafer hybrid bonding technique. Such conventional die-to-wafer hybrid bonding technique requires a delicate placement of the die to have a successful and yielding bond between the die and the wafer. However, there are some known limitations of such technique, such as alignment errors during die placement on the wafer. For example, die placement on the wafer using the conventional die-to-wafer hybrid bonding technique causes alignment errors in xy-plane of up to 1 pm and tilt errors in z-plane. The alignment errors result in unreliable bonding between the die and the wafer. Further, the conventional die-to-wafer hybrid bonding technique requires a long annealing time (especially, to overcome alignment errors in the z-plane), and therefore might be generally time-consuming. [0005] In some cases, the conventional die-to-wafer hybrid bonding technique incorporates a chemical mechanical planarization (CMP) process to ensure a better bonding strength. However, this requires, ideally, a perfectly planarized wafer surface that makes the conventional die-to-wafer hybrid bonding technique costly. Furthermore, the conventional die-to-wafer hybrid bonding technique relies on expensive dicing methods such as plasma dicing that further increases the manufacturing cost of the three-dimensional integrated circuit.

[0006] In other examples, sometimes, a conventional wafer-to-wafer bonding technique is used to stack multiple wafers and/or dies in the three-dimensional integrated circuit. However, the conventional wafer-to-wafer bonding technique does not accommodate different die sizes and has a low yield due to difficulties in matching a good die on one wafer to another.

[0007] Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with conventional methods of stacking semiconductor components for manufacturing semiconductor wafer assemblies.

SUMMARY

[0008] The present disclosure seeks to provide methods of stacking semiconductor components and semiconductor wafer assemblies. The present disclosure seeks to provide a solution to the existing problem of unreliable and costly methods of stacking semiconductor components to obtain three-dimensional integrated circuits. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art, and provides an improved method of stacking semiconductor components, and semiconductor assemblies manufactured therefrom with improved properties.

[0009] The object of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

[0010] In an aspect, a method of stacking semiconductor components is provided. The method comprises providing a first wafer comprising at least a first and a second die in a first and a second position, respectively. The method further comprises providing at least a third and a fourth die, to be stacked on the first and the second die, respectively and placing the third and fourth die on a carrier wafer in positions matching at least a part of the first and second position, respectively. The method further comprises applying insulating material on the carrier wafer outside of the third and the fourth dies and placing the carrier wafer on the first wafer to obtain a first die stack of the first and third dies and a second die stack of the second and fourth dies, causing bonding of the first and third dies and the second and fourth dies, respectively.

[0011]The method of the first aspect enables to provide an efficient stacking of semiconductor components that enables better alignment accuracy of the semiconductor components. The method provides a die-to-wafer hybrid bonding using a reconstructed wafer-to-wafer hybrid bonding, and in turn solves the misalignment issues with die-to-wafer stacking thus, combining the advantages of die-to-wafer stacking and wafer-to-wafer stacking techniques. The method further enables applying insulating material on the carrier wafer during a wafer-level deposition process, which is done in a more controlled clean- room environment and further improves the alignment of the first die stack of the first and third dies and the second die stack of the second and fourth dies.

[0012] In an implementation form, the method further comprises the steps of applying conductive metal pads on the third and the fourth die aligned with conductive metal pads present on the first and second die, respectively, and planarizing the conductive metal pads on the third and fourth dies before placing the carrier wafer on the first wafer.

[0013] The conductive metal pads provide the electrical connection between the first and third dies, and the second and fourth dies, respectively. The conductive metal pads on the third and fourth dies are planarized before placing the carrier wafer on the first wafer to provide smooth surfaces for the conductive metal pads for better die-to-wafer bonding.

[0014] In an implementation form, alignment of the conductive metal pads is achieved relative to the alignment reference present on the first die and the placement alignment of the third and fourth dies on the carrier.

[0015] The alignment reference present on the first die helps to ensure proper alignment of the conductive metal pads and avoid misalignment errors for the first and the second die on the first wafer with the third and fourth die on the carrier wafer. Further, the conductive metal pads on the carrier wafer are processed after die-to-wafer stacking to adjust any misalignment errors post stacking of dies and wafers.

[0016] In an implementation form, the method further comprises the step of removing the carrier wafer after the bonding.

[0017] The carrier wafer is placed on the first wafer using the temporary bonding process since the purpose of the carrier wafer is to mechanically support the stacking of the first and third dies and the second and fourth dies, respectively and thus, the carrier wafer is removed at the end of the stacking process.

[0018] In an implementation form, the method further comprising the step of separating the first die stack and the second die stack from the remainder of the first wafer.

[0019] The first die stack and the second die stack are separated from the remainder of the first wafer so that the first die stack and the second die stack could be used for building electronic devices.

[0020] In an implementation form, the insulating material includes a layer of a molding compound.

[0021]The molding compound could be used as the insulating material to protect die from the external environment, including chemical reaction and mechanical damage. The molding compound also functions as an adhesive and a binder. Therefore, the molding compound provides mechanical strength and minimises thermal stress in the formed semiconductor wafer assembly.

[0022] In an implementation form, the insulating material includes solely dielectric material.

[0023] The dielectric material could be used as the insulating material in order to protect and insulate the carrier wafer and thus, ensures reliable performance of the formed semiconductor wafer assembly.

[0024] In an implementation form, the insulating material includes a base layer of dielectric material on the surface of the carrier wafer outside of the third and fourth dies and a layer of a molding compound covering the base layer of dielectric material.

[0025] The dielectric material on the surface of the carrier wafer protects and insulates the carrier wafer. Further, the molding compound covering the base layer of dielectric material protects the die from the external environment and mechanical damage. Therefore, the combined use of the dielectric material and the molding compound, as the insulating material, provide mechanical strength to the carrier wafer and increases thermal dispersion of the carrier wafer and thus, ensures reliable performance of the formed semiconductor wafer assembly.

[0026] In an implementation form, the insulating material includes a surface layer of a dielectric material on the surface of the third and fourth die arranged to face the first wafer. [0027] The dielectric material on the surface of the third and fourth dies protects and insulates the respective dies when in contact with the first wafer during the manufacturing process.

[0028] In an implementation form, the method further includes placing a fifth die on the carrier wafer in such a way that the fourth and fifth die will match different areas of the second die when the carrier wafer is placed on the first wafer.

[0029] The present manufacturing method by implementing tools to pick and place dies, including dies of varying size/area, on the carrier wafer allows providing a configuration with dies stacked in a staggered manner, if required.

[0030] In an implementation form, the method further includes arranging at least one via to the bottom wafer through the insulating material.

[0031] Herein, the at least one via includes, but is not limited to, through-dielectric-vias (TDVs) and through-mold-vias (TMVs). The through-dielectric-vias provide improved stress management, reduced keep-out-zones, reduced via-to-via and via-to-device coupling because of relatively large dielectric spacing and low-k dielectrics, reduced parasitic capacitance, faster switching speeds, lower heat dissipation requirements, lower production costs, easy miniaturization that is scalable to large assemblies and interposers, and high performance stacked assemblies. The through-mold-vias helps to create interconnected vias through the mold cap, and also provides a more stable bottom package that enables the use of thinner substrates with a larger die to package ratio.

[0032] In another aspect, a semiconductor wafer assembly is provided. The semiconductor wafer assembly comprises a first wafer having thereon a first and a second die in a first and a second position, respectively, a carrier wafer having thereon a third and a fourth die, stacked on the first and the second die, respectively, with conductive metal pads in matching positions, one or more layers of insulating material between the first wafer and the carrier wafer outside of the third and the fourth dies, the first and third dies and the second and fourth dies, respectively being bonded together, for example, by hybrid bonding.

[0033] The semiconductor wafer assembly of the second aspect being manufactured using the method of the first aspect provides the advantages and effects achieved thereby. The semiconductor wafer assembly does not have the misalignment problems of die-to-wafer stacking as well as issues of possible defects as the defects are encapsulated in the molding compound and the dielectric film during a wafer-level deposition process. [0034] In yet another aspect, a semiconductor die assembly is provided. The semiconductor die assembly comprises a first die and a second die stacked on at least a first portion of the first die and bonded thereto, for example, with hybrid bonding, the first and second dies having conductive metal pads in matching positions.

[0035] The semiconductor die assembly of the third aspect being manufactured using the method of the first aspect provides the advantages and effects achieved thereby. The semiconductor die assembly does not have the misalignment problems of die-to-wafer stacking as well as issue of possible defects as the defects are encapsulated in the molding compound and the dielectric film during a wafer-level deposition process

[0036] In a further implementation form, the semiconductor die assembly comprises a third die stacked on a second portion of the first die and bonded thereto, for example, with hybrid bonding, the first and third dies having conductive metal pads in matching positions, the assembly further comprising a continuous dielectric layer covering the surfaces of the second and third dies facing the first die.

[0037] The semiconductor die assembly allows for staggered stacking of dies. The conductive metal pads provide electrical connection between the first and third dies, and the dielectric layer on the surface of the second and third dies protects and insulates the respective dies when in contact with the first wafer during the manufacturing process.

[0038] In a further implementation form, the semiconductor die assembly comprises a via through the insulating material from the bottom wafer.

[0039] The via includes, but is not limited to, through-dielectric-vias (TDVs) and through- mold-vias (TMVs). The through-dielectric-vias are shielded from the dies and from each other by an intervening thickness of the insulating material sufficient to reduce noise, signal coupling, and frequency losses. The through-dielectric-vias provide improved stress management, reduced keep-out-zones, reduced via-to-via and via-to-device coupling because of relatively large dielectric spacing and low-k dielectrics, reduced parasitic capacitance, faster switching speeds, lower heat dissipation requirements, lower production costs, easy miniaturization that is scalable to large assemblies and interposers, and high performance stacked assemblies. The through-mold-vias helps to create interconnected vias through the mold cap, and also provides a more stable bottom package that enables the use of thinner substrates with a larger die to package ratio.

[0040] It will be appreciated that all implementation forms discussed hereinabove can be combined. It has to be noted that all devices, elements, circuitry, units, and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

[0041] Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

[0043] Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1 is a flowchart listing steps in a method of stacking semiconductor components, in accordance with an embodiment of the present disclosure;

FIGs. 2A to 2M are exemplary illustrations of various stages involved in the stacking of the semiconductor components, in accordance with an embodiment of the present disclosure;

FIG. 3 is an illustration of a semiconductor die assembly, in accordance with an embodiment of the present disclosure; and FIG. 4 is an illustration of a semiconductor die assembly, in accordance with another embodiment of the present disclosure.

[0044] In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

DETAILED DESCRIPTION OF EMBODIMENTS

[0045] The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.

[0046] The present disclosure provides a collective die-to-wafer hybrid bonding (or stacking) using re-constructed wafer-to-wafer hybrid bonding. The resultant semiconductor wafer assembly comprises a first wafer having thereon a first and a second die in a first and a second position, respectively, a carrier wafer having thereon a third and a fourth die, stacked on the first and the second die, respectively, with conductive metal pads in matching positions. Further, the semiconductor wafer assembly comprises one or more layers of insulating material between the first wafer and the carrier wafer outside of the third and the fourth dies, the first and third dies and the second and fourth dies, respectively being bonded together, for example, by hybrid bonding.

[0047] The manufacturing method as disclosed in the present disclosure solves the misalignment problems of die-to-wafer stacking as well as issues of possible defects by encapsulating the defects in the molding compound and the dielectric film during a wafer- level deposition process, which is done in a more controlled clean-room environment. The disclosed method provides innovative post-processing of dielectric stacking and metal pads, such as copper pads, after the initial die-to-wafer placement is complete.

[0048] In the present disclosure, the term "semiconductor" is intended to mean such silicon, germanium and silicon-germanium alloy semiconductor elements. Such elements can be circular, rectangular, or triangular or any other convenient geometric shape, although they are usually in the form of a wafer or disc in most commercial situations. Semiconductors have been known in the industry for many years, and the term semiconductor element has been considered generic to silicon, germanium and silicon-germanium alloys. Further, as used herein, the term "chip" ("chips" for several) generally refers to a semiconductor microchip in various Stages of completion, independent of whether it is integrated into a wafer or isolated from a semiconductor wafer, and comprising an integrated circuit, the on the surface is made of the same. The term "wafer" refers to one in general Round single crystal semiconductor substrate, on the integrated circuits be made in the form of chips. Further, the term “connection” or “interconnect” refers to a physical connection providing possible electrical communication between the connected items. The term “layer” refers to a thin stratum within a semiconductor wafer. The term “film” refers to a relatively thin layer within a semiconductor wafer.

[0049] Referring to FIG. 1 , illustrated is a flowchart of a method 100 of stacking semiconductor components, in accordance with an embodiment of the present disclosure. As should be appreciated, the particular steps and methods described herein are not exclusive and, as will be understood by those skilled in the art, the particular ordering of steps as described herein is not intended to limit the method, e.g., steps may be performed in a differing order, additional steps may be performed, and disclosed steps may be excluded without departing from the spirit of the present disclosure.

[0050] FIGs. 2A to 2M are exemplary illustrations of various stages for executing the method 100 of stacking semiconductor components, in accordance with an embodiment of the present disclosure. Herein, the steps of the method 100 of stacking semiconductor components have been explained in reference to FIGs. 2A to 2M.

[0051]At step 102, the method 100 comprises providing a first wafer comprising at least a first and a second die in a first and a second position, respectively. Herein, the first wafer is a thin slice of semiconductor material (such as electronic-grade silicon and GaAs) that is used for the fabrication of integrated circuits by stacking semiconductor components on the first wafer. The term “wafer” refers to a generally round, single-crystal semiconductor substrate upon which integrated circuits are fabricated in the form of dies. The wafer serves as the substrate for microelectronic devices built in and upon the wafer. It undergoes many microfabrication processes, such as doping, ion implantation, etching, thin-film deposition of various materials, and photolithographic patterning. Finally, the individual microcircuits are separated by wafer dicing and packaged as an integrated circuit.

[0052] Further, each of the first and the second dies is a block of semiconductor material on which a given functional circuit (such as Central Processing Unit) is fabricated. Herein, the “die” is a small block of semiconducting material on which a given functional circuit is fabricated. Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon or other semiconductors through processes such as photolithography. The wafer is cut (diced) into many pieces, each containing one copy of the circuit. Each of these pieces is called a die. In the present examples, the first die and the second die may be identical to each other in respect of one or more of dimensions, semiconductor materials used for fabrication, and the like. In another example, the first die and the second die may be different from each other in respect of the same factors without departing from the scope of the present disclosure.

[0053]As discussed, the first and the second dies are placed in their respective positions or areas on the first wafer. It may be appreciated that positioning of the dies on the wafer may be determined based on the size of the wafer, size of each of the dies to be placed thereon, number of dies to be placed thereon, and the like. Generally, there are hundreds or even thousands of dies placed on a single wafer. In an example, the first wafer may include 500 to 5000 number of dies thereon. In some examples, the positioning of the dies may also be dependent on factors like the manufacturing constraints, such that the dies may be strategically positioned to not cause manufacturing defects, for example during dicing/cutting of the dies from the wafer.

[0054] With reference to FIG. 2A, there is shown a first wafer arrangement 200A comprising a first wafer 202. The first wafer 202 includes a plurality of dies, including a first die 203A and a second die 203B. The first wafer 202 also includes conductive metal pads 204A. The conductive metal pads 204A are processed prior to applying the same on the first wafer 202. The conductive metal pads 204A may be fabricated using copper or copper alloy because of low electrical resistivity, high electro-migration resistance, and high diffusivity of copper. Optionally, other metallic materials can also be used for fabricating the conductive metal pads 204A that may include, but not limited to tin, indium, gold, nickel, silver, palladium, palladium-nickel alloy, titanium, or any combination thereof.

[0055] With reference to FIG. 2B, there is shown a first wafer arrangement 200B comprising the first wafer 202 that includes conductive metal pads 204B. As may be seen, the first wafer 202 of FIG. 2A is filled with dielectric material 205 to obtain the first wafer 202 of FIG. 2B. The dielectric material 205 protects and insulates the first wafer. The dielectric material 205 may include, but is not limited to, silica, hafnium silicate, zirconium silicate and barium titanate. Further, the conductive metal pads 204A of FIG. 2A are planarized to obtain perfectly planar conductive metal pads 204B of FIG. 2B in order to avoid any misalignment and create a flat, mirror surface of the conductive metal pads 204B with no distortions. The conductive metal pads 204B may be planarized using chemical mechanical polishing (CMP) technology. [0056] With reference to FIG. 2C, there is shown a first wafer arrangement 200C comprising the first wafer 202 having the conductive metal pads 204B. The first wafer 202 of FIG. 2B is processed using plasma activation treatment to obtain the first wafer 202 of FIG. 2C. The plasma activation treatment provides ultrafine cleaning of the first wafer 202, which leads to an increase in surface energy.

[0057]At step 104, the method 100 comprises providing at least a third and a fourth die to be stacked on the first and the second die, respectively. Similar to the first and second dies, each of the third and fourth dies is a block of semiconductor material on which a given functional circuit is fabricated. Furthermore, the third die and the fourth die may be identical to or different from each other in respect of one or more of dimensions, semiconductor materials used for fabrication, and the like, without departing from the scope of the present disclosure. In the present embodiments, the third die is stacked on the first die and the fourth die is stacked on the second die.

[0058] With reference to FIG. 2D, there is shown a second wafer arrangement 200D comprising a second wafer 206. The second wafer 206 is a thin slice of semiconductor material (such as electronic-grade silicon and GaAs) that is used for the fabrication of integrated circuits. In the present examples, the second wafer 206 may have a single die to thousands of dies formed thereon, without any limitations. Herein, the plurality of dies may be of similar dimensions or different dimensions, as required. The second wafer 206 comprises a plurality of dies, including a third die 207A and a fourth die 207B formed thereon. It may be noted that the second wafer 206 does not have the conductive metal pads formed therein.

[0059] With reference to FIG. 2E, there is shown a second wafer arrangement 200E with the second wafer 206 having undergone die singulation process. The die singulation process is used for separation of the plurality of dies, including the third die 207A and the fourth die 207B in the second wafer 206. The die singulation processes may include, but are not limited to, diamond scribing and breaking, laser scribing and breaking, back etching, slurry sawing and diamond sawing.

[0060]At step 106, the method 100 comprises placing the third and fourth die on a carrier wafer in positions matching at least a part of the first and second position, respectively. Herein, the carrier wafer may be generally similar to the first wafer. As used herein, the term “carrier wafer” is not intended to limit the function of such a wafer. For example, a “carrier wafer” may include a variety of circuits and/or structures, and a “carrier wafer” is not limited to only carrying other structures. Although the term carrier wafer is used, the carrier wafer may be any structure that provides support for the wafer during the manufacturing of the semiconductor wafer assembly. The carrier wafer provides mechanical support and stability to the first wafer and the first, the second, the third and the fourth dies during handling and stacking of the semiconductor components. The carrier wafer is fabricated typically using, but not limited to, a polymeric material and a semiconductor material.

[0061] Herein, the third die is placed on the carrier wafer such that the third die matches at least the part of the first position so that the third die is stacked generally, or at least partially, on the first die. Similarly, the fourth die is placed on the carrier wafer such that the fourth die matches at least the part of the second position so that the fourth is stacked generally, or at least partially, on the second die. In the present examples, the third die and the fourth die may be placed on the carrier wafer using a pick and place tool. Such technique allows to place the third and fourth die of different dimensions on the same carrier wafer, if required. Herein, the dies are placed on the carrier wafer in face-up configuration. It may be contemplated by a person skilled in the art that the present manufacturing method could achieve any of the 1 -to-1 stacking of the dies, 1-to-2 stacking of the dies, 2-to-1 stacking of the dies and the like. As may be understood, for 1 -to-1 stacking, the carrier wafer should have the same number of dies as the first wafer; for 1-to-2 stacking, carrier wafer should have twice the number of dies as the first wafer; for 2-to-1 stacking, carrier wafer should have half the number of dies as the first wafer; and so on. In general, the present manufacturing method could achieve any possible N-to-M configuration without any limitations.

[0062] With reference to FIG. 2F, there is shown a carrier wafer arrangement 200F comprising a carrier wafer 208 and a plurality of dies, including the third die 207A and the fourth die 207B arranged thereon. The third die 207A and the fourth die 207B, as separated from the second wafer 206, are placed on the carrier wafer 208. According to an embodiment, the third die 207A and the fourth die 207B are placed on the carrier wafer 208 in positions matching at least a part of the first and second position of the first die 203A and the second die 203B in the first wafer 202. Herein, the third die 207A and the fourth die 207B are placed on the carrier wafer 208 using pick & place tools/equipment in face-up configuration. The carrier wafer 208 is then cleaned to remove the chemical and particle impurities without altering or damaging the surface or the substrate of the carrier wafer 208. In an example, the carrier wafer 208 may be cleaned using wet-chemistry based technology that uses hydrofluoric acid and ozonized water.

[0063] At step 108, the method 100 comprises applying insulating material on the carrier wafer outside of the third and the fourth dies. That is, the insulating material is filled in the area where the third and the fourth dies are not located in the carrier wafer. In an example, the insulating material is applied by ejection from a syringe into the desired areas of the carrier wafer to completely fill such areas with the insulating material. In other examples, the insulating material is applied using PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, and other similar techniques as known in the art, which have not been described herein for the brevity of the present disclosure.

[0064] In an embodiment, the insulating material includes a layer of a molding compound. In the present examples, the molding compound may be any suitable epoxy material, also known as Epoxy Mold Compound (EMC), or Epoxy Molding Compounds, are thermosetting plastics with good mechanical, electrical insulation and temperature resistance properties. The molding compound may include, but is not limited to, phenolic resins, amino resins, polyester resins, silicone resins, epoxy resins, and polyurethanes. Such molding compounds are used extensively in the semiconductor, electronics and automotive industries to replace more expensive ceramics, metals and other plastics. The molding compound is encapsulated on the carrier wafer for protecting the dies from the external environment and mechanical damage. The molding compound provides mechanical strength to the carrier wafer and increases the thermal dispersion of the carrier wafer. The molding compound also functions as an adhesive and binder for effectively placing the third and fourth die on the carrier wafer.

[0065] In another embodiment, the insulating material includes solely dielectric material. In the present examples, the dielectric material may include, but not limited to, silica, hafnium silicate, zirconium silicate, barium titanate, Si02, Si3N4, SiON, Ta205, AI203, benzocyclobutene (BCB), polyimide (PI), polybenzoxazoles (PBO), or other suitable dielectric material. The dielectric material could be used as the insulating material in order to protect and insulate the carrier wafer and thus, ensures reliable performance of the formed semiconductor wafer assembly. In one or more examples, the area of the carrier wafer is filled with the dielectric material in a time-controlled manner to reduce the overburden in the formed semiconductor component.

[0066] In another embodiment, the insulating material includes a base layer of dielectric material on the surface of the carrier wafer outside of the third and fourth dies and a layer of a molding compound covering the base layer of dielectric material. Herein, the dielectric material is placed on the surface of the carrier wafer outside of the third and fourth dies. The dielectric material on the surface of the carrier wafer protects and insulates the carrier wafer. The molding compound covering the base layer of dielectric material protects the die from the external environment and mechanical damage. Further, the molding compound provides mechanical strength to the carrier wafer and increases the thermal dispersion of the carrier wafer. Therefore, the combined use of the dielectric material and the molding compound, as the insulating material, provide mechanical strength to the carrier wafer and increases thermal dispersion of the carrier wafer and thus, ensures reliable performance of the formed semiconductor wafer assembly.

[0067] In another embodiment, the insulating material includes a surface layer of a dielectric material on the surface of the third and fourth die arranged to face the first wafer. That is, the dielectric material forms the surface layer on the third die and fourth die, such that when the carrier wafer is placed on the first wafer (as discussed later in the description), the third die and fourth die as stacked on the first die and the second die, respectively are electrically insulated therefrom. Further, the dielectric material on the surface of the third die and fourth die protects and insulates the respective dies when in contact with the first wafer during the manufacturing process.

[0068] With reference to FIG. 2G, there is shown a carrier wafer arrangement 200G comprising the carrier wafer 208 with the plurality of dies, including the third die 207A and the fourth die 207B. The carrier wafer arrangement 200G further comprises an insulating material 211 filled therein. The carrier wafer 208 may be filled with the insulating material 211 in the vacant areas where the dies, such as the third die 207A and the fourth die 207B, are not located thereon. Herein, the insulating material 211 includes one or more of the molding compound and the solely dielectric material.

[0069]With reference to FIG. 2H, there is shown a carrier wafer arrangement 200H comprising the carrier wafer 208 including solely dielectric material 213. The dielectric material 213 is filled or layered in the carrier wafer 208. Herein, the dielectric material 213 is filled or layered in a time-controlled overburden. The dielectric material may include, but is not limited to silica, hafnium silicate, zirconium silicate and barium titanate.

[0070] In an embodiment, the method 100 further comprises the steps of applying conductive metal pads on the third and the fourth die aligned with conductive metal pads present on the first and second die, respectively, and planarizing the conductive metal pads on the third and fourth dies before placing the carrier wafer on the first wafer. In one or more examples, the conductive metal pads may be fabricated using copper or copper alloys because of its properties such as low electrical resistivity, high electro-migration resistance and high diffusivity. It should be noted that any of several different conductive materials may be used to create the conductive pads in the various preferred embodiments of the present disclosure. The present disclosure is not intended to be limited to any particualar conductive material. For example, other metallic materials such as, but not limited to tin, indium, gold, nickel, silver, palladium, palladium-nickel alloy, titanium, or any combination thereof, can also be used for fabricating the conductive metal pads without any limitations.

[0071]The conductive metal pads act as interconnection lines between the third die and the fourth die of the carrier wafer, and the first die and the second die of the first wafer, respectively. In one or more examples, the conductive metal pads on the third and fourth dies are planarized to create a flat, mirror surface of the conductive metal pads with no distortions, before placing the carrier wafer on the first wafer. This ensures proper bonding and avoid any misalignment between the carrier wafer and the first wafer. In the present examples, the conductive metal pads on the third and fourth dies may be planarized using chemical mechanical polishing (CMP) technique that uses combined chemical and mechanical methods involving an abrasive and corrosive chemical slurry (commonly a colloid) in conjunction with a polishing pad to achieve ultra-precision polishing of the surface of the conductive metal pads.

[0072] In accordance with embodiments of the present disclosure, the conductive metal pads are also used for correction of alignment errors between the first die and the third die, and the second die and the fourth die, respectively, during stacking. In particular, the conductive metal pads help with the better alignment accuracy of the third die with the first die, and the fourth die with the second die, respectively. In some examples, the conductive metal pads provide alignment accuracy of less than 200 nm (as compared to alignment accuracy of less than 1 pm by the conventional die-to-wafer hybrid bonding) and conductive metal pad pitch of less than 1 pm (as compared to conductive metal pad pitch of less than 7 pm by the conventional die-to-wafer hybrid bonding).

[0073] In an embodiment, alignment of the conductive metal pads is achieved relative to the alignment reference present on the first die and the placement alignment of the third and fourth dies on the carrier. The alignment reference present on the first die helps to ensure proper alignment of the conductive metal pads and avoid misalignment errors for the first and the second die on the first wafer with the third and fourth die on the carrier wafer. The conductive metal pads are such positioned that the conductive metal pads of the first die align with the conductive metal pads of the third die, and the conductive metal pads of the second die align with the conductive metal pads of the fourth die. Further, the conductive metal pads on the carrier wafer are processed after die-to-wafer stacking to adjust any misalignment errors post stacking of dies and wafers.

[0074]With reference to FIG. 2I, there is shown a carrier wafer arrangement 200I comprising the carrier wafer 208 with conductive metal pads 212A. The conductive metal pads 212A are similar to the conductive metal pads 204A. The conductive metal pads 212A are metalized to use the alignment markers (not shown) per each die of the plurality of dies 210A to correct the alignment errors. In the metallization process, a metal coating is applied on the conductive metal pads 212A to make connections to the conductive metal pads 204A of the first wafer 202. In one or more examples, the metal coating may include, but is not limited to, zinc, gold, aluminium and silver.

[0075]With reference to FIG. 2J, there is shown a carrier wafer arrangement 200J comprising the carrier wafer 208 with conductive metal pads 212B. Herein, the conductive metal pads 212A of FIG. 2I are planarized to obtain the perfectly planar conductive metal pads 212B of FIG. 2J in order to avoid any misalignment and create a flat, mirror surface of the conductive metal pads 212B with no distortions. The conductive metal pads 212B may be planarized using chemical mechanical polishing (CMP) technology. In an example, the carrier wafer 208 is processed using the plasma activation treatment for cleaning thereof. The plasma activation treatment provides ultrafine cleaning of the carrier wafer 208. As discussed, the carrier wafer 208 is filled with the dielectric material 213 that protects and insulates the carrier wafer 208.

[0076] In an embodiment, the method 100 further includes arranging at least one via to the bottom wafer through the insulating material. A via is an electrical connection between layers in a physical electronic circuit that goes through the plane of one or more adjacent layers. The term "via" is used herein generally to refer to complete through-holes or incomplete holes, and may collectively refer to both contacts and vias as known in the art of integrated circuits. The depth of the vias may be through the partial material thickness (i.e. blind vias) or the entire material thickness (i.e. through vias). Vias are formed in desired locations through the use of conventional photolithography and etch techniques. Generally, the vias can be patterned to selectively couple some specific device contacts to achieve the desired function.

[0077] In an example, the at least one via includes, but not limited to, through-dielectric-via (TDV) and through-mold-via (TMV). In through-dielectric-via process, a conductive vertical pillar is fabricated for stacking semiconductor components in the insulating material instead of in the die or the first wafer. Herein, a portion of the third die may be removed and replaced with the dielectric material, and the conductive vertical pillar is fabricated through the insulating material. Similarly, in the through-mold-via, a conductive vertical pillar is fabricated for stacking semiconductor components in the insulating material instead of in the die or the first wafer. Herein, a portion of the third die may be removed and replaced with the molding compound, and the conductive vertical pillar is fabricated through the molding compound. It may be appreciated that, in both cases, generally multiple conductive vertical pillars may be fabricated in the insulating material.

[0078] In the present examples, the through-dielectric-vias are shielded from the dies and from each other by an intervening thickness of the insulating material sufficient to reduce noise, signal coupling, and frequency losses. The through-dielectric-vias provide improved stress management, reduced keep-out-zones, reduced via-to-via and via-to-device coupling because of relatively large dielectric spacing and low-k dielectrics, reduced parasitic capacitance, faster switching speeds, lower heat dissipation requirements, lower production costs, easy miniaturization that is scalable to large assemblies and interposers, and high performance stacked assemblies. Further, the through-mold-vias helps to create interconnected vias through the mold cap, and also provides a more stable bottom package that enables the use of thinner substrates with a larger die to package ratio.

[0079] In an embodiment, the method 100 further includes placing a fifth die on the carrier wafer in such a way that the fourth and fifth die will match different areas of the second die when the carrier wafer is placed on the first wafer. Similar to other dies discussed so far, the fifth die is also a block of semiconductor material on which a given functional circuit is fabricated. The fifth die is stacked on a portion of the second die, similar to the fourth die, with the fourth die and the fifth die both occupying different areas of the second die. For example, the fourth die occupies a first portion of the second die and the fifth die occupies a second portion of the second die. In an example, the fourth die and the fifth die may be identical to or different from each other in respect of one or more of dimensions, semiconductor materials used for fabrication, and the like, without any limitations. In an example, the fourth die and the fifth die may be arranged as being adjacent to each other, although in a stacked manner, such that the fourth and fifth die will match different areas of the second die when the carrier wafer is placed on the first wafer for manufacturing the semiconductor wafer assembly. It may be appreciated that the placement of fifth die in such manner is achieved by implementing tools to pick and place dies, including dies of varying size/area, on the carrier wafer and thus allows to provide configuration with dies stacked in a staggered manner, if required.

[0080]At step 110, the method 100 comprises placing the carrier wafer on the first wafer to obtain a first die stack of the first and third dies and a second die stack of the second and fourth dies, causing bonding of the first and third dies and the second and fourth dies, respectively. As discussed, the die stacking is the process of mounting multiple dies/chips on top of each other within a single semiconductor package. Die stacking, which is also known as 'chip stacking', significantly increases the amount of silicon chip area that can be housed within a single package of a given footprint, conserving precious real estate on the printed circuit board and simplifying the board assembly process. Aside from space savings, die stacking also results in better electrical performance of the device, since the shorter routing of interconnections between circuits results in faster signal propagation and reduction in noise and cross-talk.

[0081] As mentioned, the carrier wafer, with the third and fourth dies, is placed on the first wafer, with the first and second dies, such that the first and third dies are bonded to form the first die stack and the second and fourth dies are bonded to form the second die stack. Herein, one of the dies in each of the formed stacks may be a memory chip, a silicon-die, a flip-chip package, a passive device, and on the like, and may also be a fan-out wafer level package that integrates a single die or multiple dies; and the other die in corresponding formed stacks has a same structure as the associated die therewith, or may have a different structure from that of the associated die therewith. Technologies used to place the carrier wafer on the first wafer may include, but are not limited to, contact bonding and thermo compression bonding. For example, a process of mass reflow or thermo-compression bonding may be adopted to solder one die to the other in the formed stack, and sometimes underfill may be used in between to enhance strength and reliability of the structure, if required.

[0082] With reference to FIG. 2K, there is shown a diagrammatic depiction of a semiconductor wafer assembly 200K with the carrier wafer 208 being stacked onto the first wafer 202. In the semiconductor wafer assembly 200K, the carrier wafer 208 is stacked and bonded onto the first wafer 202 using the hybrid-bonding technique. As discussed, the carrier wafer 208 may be bonded on to the first wafer 202 using techniques which may include, but are not limited to, contact bonding and thermo-compression bonding. For example, a process of mass reflow or thermo-compression bonding may be adopted to solder one die to the other in the formed stack, and sometimes underfill may be used in between to enhance strength and reliability of the structure, if required.

[0083] In general, the semiconductor wafer assembly 200K comprises the first wafer 202 having thereon the first die (such as the first die 203A, not shown) and the second die (such as the second die 203B, not shown) in a first and a second position, respectively. The semiconductor wafer assembly further comprises the carrier wafer 208 having thereon a third die (such as the third die 207A, not shown) and a fourth die (such as the fourth die 207B, not shown), stacked on the first and the second die, respectively, with conductive metal pads (such as the conductive metal pads 204B and the conductive metal pads 212B, only one shown) in matching positions, one or more layers of insulating material (such as, the insulating material 205) between the first wafer 202 and the carrier wafer 208 outside of the third and the fourth dies, the first and third dies, and the second and fourth dies, respectively being bonded together, for example, by hybrid bonding. In the present embodiments, the hybrid bonding enables a die-to-wafer hybrid bonding using a reconstructed wafer-to-wafer hybrid bonding.

[0084] In an embodiment, the method 100 further comprises the step of removing the carrier wafer after the bonding. It is to be noted that the carrier wafer is bonded to the first wafer using a temporary bonding process since the purpose of the carrier wafer is to mechanically support the stacking of the first and third dies and the second and fourth dies, respectively. Thereafter, the carrier wafer is separated at the end of the stacking process. In the present embodiments, the carrier wafer is removed from the first wafer after the bonding of the first and third dies, and the second and fourth dies respectively using a process like laser debonding. Debonding is the act of removing the processed silicon device wafer from the substrate or handling wafer so that the processed silicon device wafer may be added to a 3D stack. In another example, the carrier wafer may be removed from the first wafer using techniques such as, but not limited to, slide debonding and mechanical debonding.

[0085] With reference to FIG. 2L, there is shown a diagrammatic depiction of the semiconductor wafer assembly 200K with the carrier wafer 208 being de-bonded from the first wafer 202. De-bonding is a process of separation of the carrier wafer 208 from the first wafer 202. It may be understood that the carrier wafer 208 is placed on the first wafer 202 using a temporary bonding process since the purpose of the carrier wafer 208 is to mechanically support the stacking of the plurality of dies 204B with the plurality of dies 210 and the carrier wafer 208 is separated thereafter (i.e. after completion of the stacking process). The carrier wafer 208 may be removed from the first wafer 202 using Laser Debonding. In one or more examples, the carrier wafer 208 is removed from the first wafer 202 using techniques that may include, but not limited to, slide debonding and mechanical debonding.

[0086] In an embodiment, the method 100 further comprises the step of separating the first die stack and the second die stack from the remainder of the first wafer. Process of separation of the first die stack and the second die stack from the remainder of the first wafer also known as die cutting, dicing, and singulation is well known in the art. Separating the first die stack and the second die stack results in discrete integrated circuits that may be used independently for various processing applications. The processes that may be used for separating the first die stack and the second die may include, but not limited to, diamond scribing and breaking, laser scribing and breaking, back etching, slurry sawing, and diamond sawing.

[0087]With reference to FIG. 2M, there is shown a diagrammatic depiction of a wafer arrangement 200M with the first wafer 202 undergoing die singulation process. Die singulation process is also referred to as die cutting and dicing. Die singulation results in the formation of individual integrated circuits that may be used independently for processing purposes. The processes that may be used for die singulation may include, but are not limited to, diamond scribing and breaking, laser scribing and breaking, back etching, slurry sawing, and diamond sawing. According to embodiments of the present disclosure, the process of FIGS. 2A-2M causing bonding of the first die 203A and the third die 207A and the second die 203B and the fourth die 207B, respectively to obtain a first die stack 214A (of the first die 203A and the third die 207A) and a second die stack 214B (of the second die 203B and the fourth die 207B).

[0088] It may be appreciated that the steps 102 and 110 of the method 100 and the involved various stages as shown in FIGs. 2A-2M are only illustrative and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.

[0089] Referring now to FIG. 3, illustrated is a semiconductor die assembly 300, in accordance with an embodiment of the present disclosure. The semiconductor die assembly 300 is manufactured as a result of the method 100 of FIG. 1 and the various stages of FIGs. 2A-2M as discussed in the preceding paragraphs. As illustrated, the semiconductor die assembly 300 comprises a first die 302 and a second die 304. Each of the first die 302 and the second die 304 is a block of semiconductor material on which a given functional circuit (such as Central Processing Unit) is fabricated. Herein, it may be noted that the first die 302 may correspond to any one of the first die 203A and the second die 203B of FIGs. 2A-2M; and the second die 304 may correspond to any one of the third die 207A and the fourth die 207B of FIGs. 2A-2M.

[0090] In the semiconductor die assembly 300, the second die 304 is stacked on at least a first portion of the first die 302 and bonded thereto, for example, with hybrid bonding. As discussed, in the present embodiments, the hybrid bonding enables a die-to-wafer hybrid bonding using a reconstructed wafer-to-wafer hybrid bonding. In the present examples, the first die 302 and the second die 304 may be identical to or different from each other in respect of dimensions, semiconductor materials used for fabrication, and the like, without any limitations. Generally, the shapes of the first die 302 and the second die 304 may be in the form of, but not limited to, rectangular, circular, square, oval, and alike.

[0091]The semiconductor die assembly 300 further comprises conductive metal pads 306A. The first 302 and second dies 304 have conductive metal pads 306A in matching positions. The conductive metal pads 306A act as interconnection lines between the first die 302 and the second die 304 and provide better alignment accuracy between the first die 302 with the second die 304. The conductive metal pads 306A may be fabricated using copper or copper alloy because of low electrical resistivity, high electro-migration resistance, and high diffusivity of copper. Optionally, other metallic materials can also be used for fabricating the conductive metal pads 306A that may include, but is not limited to tin, indium, gold, nickel, silver, palladium, palladium-nickel alloy, titanium, or any combination thereof.

[0092] Further, as illustrated, the semiconductor die assembly 300 may include a third die 308 stacked on a second portion of the first die 302 and bonded thereto, for example, with hybrid bonding. In the present embodiment of FIG. 3, the semiconductor die assembly 300 is a result of 1-to-2 stacking configuration (as discussed). The third die 308 is each a block of semiconductor material on which a given functional circuit (such as Central Processing Unit) is fabricated. Herein, the third die 308 may correspond to the fifth die as described above. In the present example, the third die 308 may be identical to or different from the second die 304 in respect of dimensions, semiconductor materials used for fabrication, and the like, without any limitations. In an example, the shape of the third die 308 may include, but is not limited to rectangular, circular, square, oval, and alike. Similar to the second die 304, the third die 308 may be stacked and bonded in the semiconductor die assembly 300, with a die-to-wafer hybrid bonding using a reconstructed wafer-to-wafer hybrid bonding technique.

[0093]As illustrated, the first and third dies 302, 308 have conductive metal pads 306B in matching positions. The conductive metal pads 306B act as interconnection lines between the first die 302 and the third die 308, and provide better alignment accuracy between the first die 302 with the third die 308. The conductive metal pads 306B may be fabricated using copper or copper alloy because of low electrical resistivity, high electro-migration resistance, and high diffusivity of copper. Optionally, other metallic materials can also be used for fabricating the conductive metal pads 306B that may include, but not limited to, tin, indium, gold, nickel, silver, palladium, palladium-nickel alloy, titanium, or any combination thereof. [0094] The assembly 300 further comprises a continuous dielectric layer 310 covering the surfaces of the second and third dies 304, 308 facing the first die 302. As illustrated, the area between the second die 304 and the third die 308 facing the first die 302 is also filled with the dielectric material with a time-controlled overburden. The dielectric material protects and insulates the first die 302 from the second die 304 and the third die 308. The dielectric material may include, but is not limited to silica, hafnium silicate, zirconium silicate and barium titanate.

[0095] In one or more embodiments, the semiconductor die assembly 300 further comprises a layer of a molding compound 312. The molding compound 312 (also known as epoxy material) is placed between a sidewall 314A of the first die 302 and a sidewall 314B of the second die 304, in the assembly 300. The molding compound 312 is further placed between a sidewall 314C of the first die 302 and a sidewall 314D of the third die 308. The molding compound 312 is used for protecting die from external environment and mechanical damage. Further, the molding compound 312 provides mechanical strength to the semiconductor die assembly 300 and increases thermal dispersion of the semiconductor die assembly 300. The molding compound may include, but is not limited to phenolic resins, amino resins, polyester resins, silicone resins, epoxy resins, and polyurethanes. The molding compound may also protect the sidewalls from damage during the dicing of the semiconductor wafer assembly to form the semiconductor die assembly 300.

[0096] In one or more embodiments, the semiconductor die assembly 300 further comprises a via 316 through the insulating material from the bottom wafer 318. Herein, the via 316 is passing through the insulating layer, including the dielectric layer 310 and the molding compound 312, with the bottom wafer 318 having the second die 304 and the third die 308. As discussed, the via 316 includes, but is not limited to, through-dielectric-vias (TDVs) and through-mold-vias (TMVs). The through-dielectric-vias are shielded from the dies and from each other by an intervening thickness of the insulating material sufficient to reduce noise, signal coupling, and frequency losses. The through-dielectric-vias provide improved stress management, reduced keep-out-zones, reduced via-to-via and via-to- device coupling because of relatively large dielectric spacing and low-k dielectrics, reduced parasitic capacitance, faster switching speeds, lower heat dissipation requirements, lower production costs, easy miniaturization that is scalable to large assemblies and interposers, and high performance stacked assemblies. The through-mold-vias helps to create interconnected vias through the mold cap, and also provides a more stable bottom package that enables the use of thinner substrates with a larger die to package ratio. In some examples, the semiconductor die assembly 300 further comprises intra-die filling material 320 as known in the art and thus not being described herein for the brevity of the present disclosure.

[0097] Referring to FIG. 4, illustrated is another exemplary semiconductor die assembly 400, in accordance with an embodiment of the present disclosure. In the present embodiment of FIG. 4, the semiconductor die assembly 400 is a result of 1 -to-1 stacking configuration (as discussed). The semiconductor die assembly 400 comprises a first die 402 and a second die 404. According to embodiments of the present disclosure, the first die 402 and the second die 404 are each a block of semiconductor material on which a given functional circuit (such as Central Processing Unit) is fabricated. The first die 402 and the second die 404 are stacked and may be bonded with a die-to-wafer hybrid bonding using a reconstructed wafer-to-wafer hybrid bonding.

[0098] The semiconductor die assembly 400 further comprises conductive metal pads 406. The conductive metal pads 406 of the first die 402 are represented as 406A and the second die 404 are represented as the conductive metal pads 406B. The conductive metal pads 406 act as interconnection lines between the first die 402 and the second die 404 and provide better alignment accuracy between the first die 402 with the second die 402. The conductive metal pads 406 may be fabricated using copper or copper alloy because of low electrical resistivity, high electro-migration resistance, and high diffusivity of copper. Optionally, other metallic materials can also be used for fabricating the conductive metal pads 406 that may include, but not limited to tin, indium, gold, nickel, silver, palladium, palladium-nickel alloy, titanium, or any combination thereof.

[0099] The semiconductor die assembly 400 further comprises insulating material including dielectric material 408A and molding compound 408B. In particular, the insulating material includes a base layer of the dielectric material 408A on a lower position outside of the second die 404 and a layer of the molding compound 408B covering the base layer of dielectric material 408A. The dielectric material 408A protects and insulates the first die 402 and the second die 404. The molding compound 408B covers the base layer of dielectric material 408A for protecting the first die 402 and the second die 404 from the external environment and mechanical damage. Further, the molding compound 408A provides mechanical strength to the semiconductor wafer assembly 400 and increases thermal dispersion of the semiconductor wafer assembly 400. In some examples, the insulating material 408 includes a surface layer of the dielectric material 408A on the surface of the second die 404 arranged to face the first die 402. The dielectric material 408A on the surface of the second die 404 protects and insulates the first die 402 and the second die 404. [0100] The semiconductor die assembly 400 further comprises vias 410A and 41 OB passing through the insulating material. The vias 410A and 410B may include, but are not limited to, through-dielectric-via (TDV) and through-mold-via (TMV). In through-dielectric- via process, a conductive vertical pillar is fabricated for stacking semiconductor components in the insulating material instead of in either of the die and/or the first wafer. For example, a portion of the second die 404 may be removed and replaced with the dielectric material 408A acting as the insulating material, and the conductive pillar is fabricated through the insulating material. In through-mold-via, a conductive vertical pillar is fabricated for stacking semiconductor components in the insulating material instead of the die. For example, a portion of the second die 404 may be removed and replaced with molding compound 408B acting as the insulating material, and the conductive pillar is fabricated through the insulating material. It may be appreciated that more than one conductive vertical pillar, such as two conductive vertical pillars, may be fabricated in the insulating material without any limitations.

[0101] It should be noted that only a limited number of vias, such as vias 410A and 410B, are shown for the ease of illustration and clarity. However, those of ordinary skill in the art will appreciate that, in practice, the semiconductor die assembly 400 associated with integrated circuits and stacked die may include millions or even tens of millions or more active devices and, further, that interconnect structures may include tens or even hundreds of conductors in the layers therein. Similarly, those of ordinary skill in the art will appreciate that each stacked die may, in practice, include dozens or hundreds of back-side connections using conductive vias and leads.

[0102] The present disclosure provides a collective die-to-wafer hybrid bonding (or stacking) using re-constructed wafer-to-wafer hybrid bonding. Herein, in general, the dies are populated on a career wafer using pick & place equipment in face-up configuration. The empty gaps between the dies are partially filled with a epoxy/molding-compound material. The remaining gaps are filled with oxide-like or any di-electric material with a time-controlled overburden. Then, pad vias are patterned and filled with metal to make connections to the pads of the wafer. The top pad surface is then planarized to prepare for the hybrid bonding. This re-constructed wafer is then hybrid-bonded to the other planarized target wafer. The bonded wafers can then be singulated after the debonding of the carrier wafer. This flow enables lower defects and also better alignment accuracy.

[0103] Conventional stacking approaches require two complete wafers that contain copper pads. Further, copper pads are planarized prior to singulation, to the die placement, and to the bonding. The conventionally used die-to-wafer stacking needs a perfectly planarized surface already containing the processed copper pads. Such die placement on the wafer causes alignment errors in the xy-plane (+-1um) and as well as in the z-plane (tilt errors). The manufacturing method as disclosed in the present disclosure solves the misalignment problems of die-to-wafer stacking as well as issues of possible defects by encapsulating the defects in the molding compound and the dielectric film during a wafer-level deposition process.

[0104] The disclosed method provides innovative post-processing of dielectric stacking and metal pads, such as copper pads, after the initial die-to-wafer placement is complete. Herein, copper pads are landed to the bottom copper pads on the wafer, and alignment of post-processed copper pads are not correlated to the alignment reference point but rather to the alignment reference of the opposing die, and thus there is no placement related alignment shifts in the copper pads as these are corrected in the post-processing step. This leads to construction of hybrid library with stronger N (e.g. 1P+2N) and stronger P (e.g. 2P+1 N) cells. This also allows using transition time as the cell swap decision to decide on the type of cells used for a stage in the datapath. This also provides eco-compatibility where cell sizes are identical.

[0105] The semiconductor die assembly of the present disclosure have dual-or-more layer intra-die fill material; for example, molding compound followed by the dielectric material (such as oxides). Such a hybrid intra-die fill process ensures good mechanical strength. In the semiconductor die assembly of the present disclosure, bonding dielectric and bonding interface are visible on the bottom dies. Herein, sidewall damage from the singulation of the bottom wafer does not go through bonding dielectric showing that bonding dielectric deposition and copper pads processed after the die-to-carrier stacking. This results in better alignment accuracy (<200nm vs <1um) and therefore better copper pad pitch (<1um vs 7um), as compared to the assemblies manufactured using the conventional manufacturing processes. The semiconductor die assembly of the present disclosure can be employed for processors, memory, or any other devices that rely on advanced technology nodes.

[0106] Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

1. A method of stacking semiconductor components, comprising providing a first wafer comprising at least a first and a second die in a first and a second position, respectively, providing at least a third and a fourth die, to be stacked on the first and the second die, respectively, placing the third and fourth die on a carrier wafer in positions matching at least a part of the first and second position, respectively applying insulating material on the carrier wafer outside of the third and the fourth dies placing the carrier wafer on the first wafer to obtain a first die stack of the first and third dies and a second die stack of the second and fourth dies, causing bonding of the first and third dies and the second and fourth dies, respectively.

2. A method according to claim 1 , comprising the steps of applying conductive metal pads on the third and the fourth die aligned with conductive metal pads present on the first and second die, respectively, and planarizing the conductive metal pads on the third and fourth dies before placing the carrier wafer on the first wafer.

3. A method according to claim 2, wherein alignment of the conductive metal pads is achieved relative to the alignment reference present on the first die and the placement alignment of the third and fourth dies on the carrier.

4. A method according to any one of the preceding claims, further comprising the step of removing the carrier wafer after the bonding.

5. A method according to any one of the preceding claims, further comprising the step of separating the first die stack and the second die stack from the remainder of the first wafer.

6. A method according to any one of the preceding claims, wherein the insulating material includes a layer of a molding compound.

7. A method according to any one of the claims 1 - 5, wherein the insulating material includes solely dielectric material.

8. A method according to any one of the preceding claims, wherein the insulating material includes a base layer of dielectric material on the surface of the carrier wafer outside of the third and fourth dies and a layer of a molding compound covering the base layer of dielectric material.

9. A method according to any one of the preceding claims, wherein the insulating material includes a surface layer of a dielectric material on the surface of the third and fourth die arranged to face the first wafer.

10. A method according to any one of the preceding claims, further including placing a fifth die on the carrier wafer in such a way that the fourth and fifth die will match different areas of the second die when the carrier wafer is placed on the first wafer.

11. A method according to any one of the preceding claims, further including arranging at least one via to the bottom wafer through the insulating material.

12. A semiconductor wafer assembly comprising a first wafer having thereon a first and a second die in a first and a second position, respectively, a carrier wafer having thereon a third and a fourth die, stacked on the first and the second die, respectively, with conductive metal pads in matching positions, one or more layers of insulating material between the first wafer and the carrier wafer outside of the third and the fourth dies, the first and third dies and the second and fourth dies, respectively being bonded together, for example, by hybrid bonding.

13. A semiconductor die assembly comprising a first die and a second die stacked on at least a first portion of the first die and bonded thereto, for example, with hybrid bonding, the first and second dies having conductive metal pads in matching positions.

14. A semiconductor die assembly according to claim 13, comprising a third die stacked on a second portion of the first die and bonded thereto, for example, with hybrid bonding, the first and third dies having conductive metal pads in matching positions, the assembly further comprising a continuous dielectric layer covering the surfaces of the second and third dies facing the first die.

15. A semiconductor die assembly according to claim 13 or 14, comprising a via through the insulating material from the bottom wafer.