CN1202794A - 具有一级和二级通孔的电路板 - Google Patents

具有一级和二级通孔的电路板 Download PDF

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CN1202794A
CN1202794A CN98107816A CN98107816A CN1202794A CN 1202794 A CN1202794 A CN 1202794A CN 98107816 A CN98107816 A CN 98107816A CN 98107816 A CN98107816 A CN 98107816A CN 1202794 A CN1202794 A CN 1202794A
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circuit board
wiring layer
electric contact
wiring
electrically connected
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CN1084586C (zh
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欧文·梅米斯
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International Business Machines Corp
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Abstract

提供一种在表面上具有排列得与被格栅界定的芯片座上的连接焊托接合的接点的电路板。在格栅之内的电路板部位提供多个一级通孔并电连接到其上方的芯片连接焊托。提供多个位于格栅之外的二级通孔并电连接到里面的芯片连接焊托。

Description

具有一级和二级通孔的电路板
本发明涉及一种能够获得高布线密度的改进型多层印刷电路板。
随着现代的芯片座变得越来越小巧，要把芯片座连接到放在下面的电路板而不会造成相邻电接点之间的短路也变得越来越困难。因此，最好开发一种新的允许比过去的可能密度更大的布线密度的电路板设计。
根据本发明，提供一种新颖的多层电路板。这种电路板包括由排列在芯片座的电连接焊托决定的格栅之内的一级通孔，这些一级通孔排列成一个间隔阵列与芯片座上连接焊托的一个子集相对应。芯片座上那些不与这些一级通孔之一连接的连接焊托则连接到安排在芯片座格栅之外的二级通孔。
仅把一些芯片座的连接焊托连接到由芯片座决定的格栅之内的通孔，开发了在这一区域里面的相邻通孔之间的空间，从而允许更多的迹线和更宽的迹线宽度、间格和焊接尺寸容纳在相邻通孔之间的这些区域内。这又促进了更高的布线密度和灵活性。把其余的芯片座连接焊托连接到位于芯片座格栅之外的通孔允许芯片座上有更稠密的阵列，从而帮助了小型化。结果，通过使用暗通路大大改善了布线密度和灵活性，同时依然保持整个设备的小巧性。
通过参照下面的附图可以更好地理解本发明，在附图中：
图1是根据本发明制造的多层电路板一个局部的简略纵截面图解，电路板上面安装有一个高密度芯片座；
图2是一个类似于图1的视图，但示出了根据本发明的更多介电材料层和电路；
图3是电路板上与芯片座上的接点相配对的电连接焊托的阵列的示意图；
图4是一个示意性内平面视图，说明图1的电路板中位于图1的芯片座确定的格栅以内的一级通孔的阵列；以及
图5是一个类似于图3的示意性内平面视图，示出位于间隔格栅之内和之外两部分的通孔。
参照图1，根据本发明的一种新颖多层电路板以标号10总体表示，它由例如FR4—一种被强化环氧树脂的三层电绝缘材料12、13和14组成。层12具有一个上表面15，层14具有一个下表面16，两个居于中间的内表面17和18分别被定义在层12/13和13/14之间。此外，电路板10在基底的表面15包括有多个接点20。这些接点20排列成要被连接的I/C芯片座上的接点的图案，这个图案在后文中有时称为格栅。一些接点20借助暗通路21直接连到紧靠其下面的镀满金属的通孔22。这些孔22可以终止在表面18，或者如图1所示，可以继续通到表面16。这些孔22有时称为一级孔。其他的接点20则借助通路21连接到表面17或18上的布线24，后者转而又连接到可以整个延伸穿过基底或者是从任一表面15、16、17或18延伸到任何别的表面的电镀通孔26。并且，布线迹线24可设置在任一表面15、16、17和18上与通孔22或26或通路21或焊托20相连接。对于这种布线法，孔22和26之间的允许间隔距离现在将予以说明。正如现在就要更详细说明的，电镀通孔22位于芯片座的格栅图案以内，而电镀通孔26则位格栅图案之外。如图2所示，组成部分13可以包括多层介电材料并且在其里面具有与电镀通孔22和26连通的多个布线层24。设置在下表面16上的接点27使得焊球28能将电路板10连接到元件(未示出)上的焊托29(对图1的实施例作类似的连接)。这使得高密度的芯片座能够连接到基底的表面，并且从电镀通孔延伸出来的电连接扩张到间隔格栅图案之外，允许表面15和16上有更多的空间用于布线并且在组成部分13的内部有更多的空间用于布线。
安装在电路板10上面的是高密度芯片座30。在其下表面32上，芯片座30确定一个电连接焊托34的高密度阵列排列在由全体电连接焊托34规定的一个格栅44的里面(见图3、4和5)。焊球35将焊托34连接到焊托20。连接焊托34紧密集结在一起成一个阵列，并且在所示出的特定实施例中排成诸列36和与之正交的诸行38(图3)。连接焊托34与基底的表面15上的接点20成同一样的阵列形式。
正如图3进一步示出的，电连接焊托34被安排成两组，即A组和B组。特别是，电连接焊托34被安排得使每一列的相邻连接焊托和每一行的相邻连接焊托在不同的组中。这一情形示于图3，从中可以看到，列40中直接毗邻“B”电连接焊托34的两个电连接焊托34都在A组中，同时行42中直接毗邻“B”电连接焊托34的两个电连接焊托34也都在A组中。A和B两组的焊托均可利用暗通路连接到表面17。
根据本发明，通孔或一级孔22可以排列成与芯片座30中电连接焊托34的阵列32相对应的一个间隔图案或阵列。“间隔阵列”的意思是阵列中的各项被排列在各行和各列中使得一个列的各项与相邻列的各项偏离大约为列中各项之间的一半距离。“与阵列32对应”的意思是一级通孔22与芯片座30中选出的电连接焊托34对准或对正，具体地说，是与所示特定实施例中芯片座的“B”电连接焊托34对准或对正。
这一点示于图4，图4示出在中间层13观察时电路板10中一级通孔22的图案。正如从这个图中所能看到的，每个一级通孔22均以和芯片座30中的电连接焊托34同一样的方式排列在一个列和一个行中。此外，一级通孔22还被排列得与芯片座中的对应电连接焊托34对正。但是，由于一级通孔22互相偏离得形成一个对应的间隔阵列，因而一级通孔22的数目近似等于芯片座中电连接焊托34的数目的一半。这样，一级通孔22仅与芯片座30中每隔一个电连接焊托34对正，特别是在所示实施例中，仅与芯片座30的“B”电连接焊托34对正。
借助这一安排，芯片座30的差不多一半电连接焊托34，即全部“B”连接焊托均电连接到直接在“B”连接焊托34下面的电路板的一级通孔22。这些通孔22均被包括在格栅44即芯片座30上连接焊托34的外边界以内。这就丢下芯片座30的差不多一半剩余电接点，即全部“A”电接点留待用别的方法电连接。(不用说，多于或少于一半都可连接到通孔22，只不过一半是一种典型结构而已)。
根据本发明，这些“A”电接点借助连通到导线或迹线24和/或在表面15、16、17和18上未示出的多个另外的或第二布线层的暗通路21，连接到位于格栅44之外的二级通孔26。这种情形示于图5，图5示出位于格栅44中的间隔图案之外的电镀通孔26。这可以借助任何常规的办法按照本发明来完成。例如表面安装工艺(SMT)技术和美国专利No.5,424,492、美国专利No.5,451,721和美国专利No.5,487,218中所叙述的暗通路技术都可用于这一目的。这些专利的发明都被引用到本文作为参考。
为使布线密度最大化，过去采用了许多方法。当通孔例如一级通孔22变得过于密集时，可以容纳在相邻通孔之间的迹线的最大数目和线宽将显著下降，特别是在中间平面和电路板的下表面中尤其如此。这是在电路板被设计得板内大多数(如果不是全部的话)通路形成在或者说“落”在芯片座的格栅以内的情形的一个特殊问题。如上所述，将间隔阵列的一些通孔安排在格栅以里，把其他的安排在格栅以外，则由于在相邻通孔之间提供了多得多的空间而大大减轻这个问题。
因此，把通孔26安排在一级通孔22的间隔阵列以外使得设备的所有相邻通孔之间都有足够的空间扩展，这一做法将受到重视。与此同时，还保持了整个设备的几何尺寸尽可能小巧。结果，就达到了元件布线的更高灵活性和更大密度的所需目的，而不用不适当的增加设备的总尺寸。这在以小型化作为不断追求目标的现代电子元件中是一个特别的优点。
虽然上面仅叙述了本发明的几个实施例，但应当理解，可以作出许多修改而不需要脱离本发明的精神和范围。例如，虽然前面的叙述说明图3的间隔阵列由正交排列的行和列组成，但应当明白，间隔阵列可以由相互交成一个锐角排列的行和列组成或者甚至排列在一个圆周上。此外，应当了解，孔26也可像孔22一样是填满金属的电镀通孔。所有这些修改都被包括在仅受下面的权利要求书限制的本发明范围内。

Claims (18)

1.一种多层电路板，用于安装一个具有高密度排列在一个格栅内的电连接焊托的阵列的芯片座，所述电路板包括：
一个电绝缘的基底，它具有上表面和下表面；
所述上表面上的多个电接点，用于连接到所述芯片座的电连接焊托；
一个在其内具有电接点的第一布线层；
一个在其内具有布线迹线的第二布线层，所述第二布线层与所述基底的上表面共生；
其中所述电路板具有以间隔阵列形式排列在所述格栅以内的一级通孔和位于所述格栅之外的二级通孔，所述一级通孔与所述上表面的相应第一电接点电连通；
所述上表面的相应第二电接点与所述第二通孔电连接。
2.权利要求1的电路板，其特征在于所述安装焊托的电接点都排成列和行的形式，每一列中的电接点都与相邻行中的电接点对准，所述电接点被排成第一电接点组和第二电接点组，使得直接毗邻每个连接焊托的连接焊托都在与该连接焊托不同的组中。
3.权利要求2的电路板，其特征在于所述列和行排列得相互成直角。
4.权利要求2的电路板，其特征在于所述一级通孔都是填塞满的。
5.权利要求2的电路板，其特征还在于将第一布线层连接到第二布线层的暗通路。
6.权利要求2的电路板，其特征在于所述第一布线层是在所述基底的下表面上。
7.权利要求5的电路板，其特征在于所述第二布线层装在所述基底的上表面上。
8.权利要求6的电路板，其特征在于所述第二布线层居于所述基底的上下表面之间，而且所述安装焊托的第二电接点都通过暗通路电连接到所述第二布线层的相应布线迹线。
9.权利要求8的电路板，其特征在于所述电路板包括多个居于所述上下表面之间的第二布线层，至少有一个第二电接点与所述第二布线层的每一层电连接。
10.权利要求2的电路板，其特征在于所述第二布线层装在所述基底的上表面上。
11.权利要求10的电路板，其特征在于所述第二布线层居于所述基底的上下表面之间，并且所述安装焊托的第二电接点通过暗通路电连接到所述第二布线层的相应布线迹线
12.权利要求11的电路板，其特征在于所述电路板包括多个居于所述上下表面之间的第二布线层，至少一个第二电接点与所述第二布线层的每一层电连接。
13.权利要求1的电路板，其特征在于所述电路板确定排列在所述格栅之外的二级通路，所述二级通路也与所述安装焊托的相应第一电接点电连通并且还与所述第一布线层的相应布线迹线电连通。
14.权利要求13的电路板，其特征在于所述二级通路排成与所述一级通路一样的间隔阵列。
15.一种形成用于安装芯片座的多层电路板的方法，芯片座具有排列在一个格栅之内的高密度电连接焊托的阵列，方法包括的步骤是：
提供一个具有上表面和下表面的电绝缘基底；
在所述上表面上形成多个用于连接到所述芯片座的电连接焊托的电接点；
形成一个在其内具有电接点的第一布线层；
形成一个在其内具有与所述基底的所述上表面共生的布线迹线的第二布线层；
在所述格栅之内形成间隔阵列形式的多个一级通孔和形成多个位于所述格栅之外的二级通孔；
将所述一级通孔与所述上表面的第一电接点电连接起来，将所述上表面的第二电接点与所述二级通孔电连接起来。
16.权利要求15所述的方法，其特征在于所述第一和第二布线层通过暗通路互相连接。
17.权利要求16的方法，其特征还在于形成多个连接上下表面的布线层。
18.权利要求17的方法，其特征在于诸布线层通过暗通路互相连接。
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