CN1349258A - 有机芯片载体的高密度设计 - Google Patents
有机芯片载体的高密度设计 Download PDFInfo
- Publication number
- CN1349258A CN1349258A CN01104645A CN01104645A CN1349258A CN 1349258 A CN1349258 A CN 1349258A CN 01104645 A CN01104645 A CN 01104645A CN 01104645 A CN01104645 A CN 01104645A CN 1349258 A CN1349258 A CN 1349258A
- Authority
- CN
- China
- Prior art keywords
- hole
- integrated circuit
- contact pad
- array pattern
- circuit carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 15
- 210000000988 bone and bone Anatomy 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 229910010293 ceramic material Inorganic materials 0.000 claims 3
- 239000011368 organic material Substances 0.000 claims 3
- 238000004100 electronic packaging Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 230000014509 gene expression Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000009422 external insulation Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
- H01R4/02—Soldered or welded connections
- H01R4/023—Soldered or welded connections between cables or wires and terminals
- H01R4/024—Soldered or welded connections between cables or wires and terminals comprising preapplied solder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Connecting Device With Holders (AREA)
Abstract
Description
Claims (28)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/506,951 US6538213B1 (en) | 2000-02-18 | 2000-02-18 | High density design for organic chip carriers |
US09/506,951 | 2000-02-18 | ||
US09/506951 | 2000-02-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1349258A true CN1349258A (zh) | 2002-05-15 |
CN1203546C CN1203546C (zh) | 2005-05-25 |
Family
ID=24016645
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB011046457A Expired - Lifetime CN1203546C (zh) | 2000-02-18 | 2001-02-16 | 有机芯片载体的高密度设计 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6538213B1 (zh) |
JP (1) | JP2001274288A (zh) |
CN (1) | CN1203546C (zh) |
IL (1) | IL140857A (zh) |
MY (1) | MY124540A (zh) |
SG (1) | SG99347A1 (zh) |
TW (1) | TW478118B (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1295784C (zh) * | 2003-06-27 | 2007-01-17 | 尔必达存储器株式会社 | 用于使得存储器阵列区域小型化的布局方法 |
CN101673886B (zh) * | 2004-11-29 | 2012-07-25 | Fci公司 | 改进的匹配阻抗表面贴装技术基底面 |
CN105789142A (zh) * | 2016-05-05 | 2016-07-20 | 中国工程物理研究院电子工程研究所 | 一种有机基板高密度集成的三维微波电路结构 |
CN110008490A (zh) * | 2015-03-17 | 2019-07-12 | 英飞凌科技奥地利有限公司 | 用于双重区域分割的系统和方法 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7256354B2 (en) * | 2000-06-19 | 2007-08-14 | Wyrzykowska Aneta O | Technique for reducing the number of layers in a multilayer circuit board |
US7281326B1 (en) | 2000-06-19 | 2007-10-16 | Nortel Network Limited | Technique for routing conductive traces between a plurality of electronic components of a multilayer signal routing device |
US7069646B2 (en) * | 2000-06-19 | 2006-07-04 | Nortel Networks Limited | Techniques for reducing the number of layers in a multilayer signal routing device |
US7259336B2 (en) | 2000-06-19 | 2007-08-21 | Nortel Networks Limited | Technique for improving power and ground flooding |
JP3527229B2 (ja) * | 2002-05-20 | 2004-05-17 | 沖電気工業株式会社 | 半導体装置、半導体装置の実装方法、及び半導体装置のリペア方法 |
TW586676U (en) * | 2003-06-16 | 2004-05-01 | Via Tech Inc | Hybrid IC package substrate |
US6919635B2 (en) * | 2003-11-04 | 2005-07-19 | International Business Machines Corporation | High density microvia substrate with high wireability |
US7214886B2 (en) * | 2003-11-25 | 2007-05-08 | International Business Machines Corporation | High performance chip carrier substrate |
US7284221B2 (en) * | 2004-11-29 | 2007-10-16 | Fci Americas Technology, Inc. | High-frequency, high-signal-density, surface-mount technology footprint definitions |
US7709747B2 (en) * | 2004-11-29 | 2010-05-04 | Fci | Matched-impedance surface-mount technology footprints |
JP4824397B2 (ja) * | 2005-12-27 | 2011-11-30 | イビデン株式会社 | 多層プリント配線板 |
KR100852176B1 (ko) * | 2007-06-04 | 2008-08-13 | 삼성전자주식회사 | 인쇄회로보드 및 이를 갖는 반도체 모듈 |
JP2010153831A (ja) * | 2008-11-25 | 2010-07-08 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置、及び半導体素子 |
US9459285B2 (en) | 2013-07-10 | 2016-10-04 | Globalfoundries Inc. | Test probe coated with conductive elastomer for testing of backdrilled plated through holes in printed circuit board assembly |
KR102542594B1 (ko) * | 2016-12-16 | 2023-06-14 | 삼성전자 주식회사 | 다층 인쇄 회로 기판 및 이를 포함하는 전자 장치 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5072075A (en) | 1989-06-28 | 1991-12-10 | Digital Equipment Corporation | Double-sided hybrid high density circuit board and method of making same |
US5483421A (en) | 1992-03-09 | 1996-01-09 | International Business Machines Corporation | IC chip attachment |
US5491303A (en) * | 1994-03-21 | 1996-02-13 | Motorola, Inc. | Surface mount interposer |
US6031723A (en) | 1994-08-18 | 2000-02-29 | Allen-Bradley Company, Llc | Insulated surface mount circuit board construction |
US5574630A (en) | 1995-05-11 | 1996-11-12 | International Business Machines Corporation | Laminated electronic package including a power/ground assembly |
US5689091A (en) * | 1996-09-19 | 1997-11-18 | Vlsi Technology, Inc. | Multi-layer substrate structure |
US5815374A (en) * | 1996-09-30 | 1998-09-29 | International Business Machines Corporation | Method and apparatus for redirecting certain input/output connections of integrated circuit chip configurations |
US5894173A (en) | 1996-11-27 | 1999-04-13 | Texas Instruments Incorporated | Stress relief matrix for integrated circuit packaging |
US5900675A (en) | 1997-04-21 | 1999-05-04 | International Business Machines Corporation | Organic controlled collapse chip connector (C4) ball grid array (BGA) chip carrier with dual thermal expansion rates |
US5808873A (en) * | 1997-05-30 | 1998-09-15 | Motorola, Inc. | Electronic component assembly having an encapsulation material and method of forming the same |
US6288347B1 (en) * | 1997-05-30 | 2001-09-11 | Kyocera Corporation | Wiring board for flip-chip-mounting |
US6162997A (en) * | 1997-06-03 | 2000-12-19 | International Business Machines Corporation | Circuit board with primary and secondary through holes |
JPH11121897A (ja) * | 1997-10-14 | 1999-04-30 | Fujitsu Ltd | 複数の回路素子を基板上に搭載するプリント配線基板の製造方法及びプリント配線基板の構造 |
JP3466443B2 (ja) * | 1997-11-19 | 2003-11-10 | 新光電気工業株式会社 | 多層回路基板 |
US6163462A (en) * | 1997-12-08 | 2000-12-19 | Analog Devices, Inc. | Stress relief substrate for solder ball grid array mounted circuits and method of packaging |
US5962922A (en) * | 1998-03-18 | 1999-10-05 | Wang; Bily | Cavity grid array integrated circuit package |
US6137062A (en) * | 1998-05-11 | 2000-10-24 | Motorola, Inc. | Ball grid array with recessed solder balls |
US6239980B1 (en) * | 1998-08-31 | 2001-05-29 | General Electric Company | Multimodule interconnect structure and process |
US6335495B1 (en) * | 1999-06-29 | 2002-01-01 | International Business Machines Corporation | Patterning a layered chrome-copper structure disposed on a dielectric substrate |
-
2000
- 2000-02-18 US US09/506,951 patent/US6538213B1/en not_active Expired - Lifetime
- 2000-12-27 TW TW089127982A patent/TW478118B/zh not_active IP Right Cessation
-
2001
- 2001-01-10 IL IL14085701A patent/IL140857A/xx not_active IP Right Cessation
- 2001-01-25 JP JP2001017512A patent/JP2001274288A/ja active Pending
- 2001-01-31 MY MYPI20010429A patent/MY124540A/en unknown
- 2001-02-06 SG SG200100662A patent/SG99347A1/en unknown
- 2001-02-16 CN CNB011046457A patent/CN1203546C/zh not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1295784C (zh) * | 2003-06-27 | 2007-01-17 | 尔必达存储器株式会社 | 用于使得存储器阵列区域小型化的布局方法 |
US7418685B2 (en) | 2003-06-27 | 2008-08-26 | Elpida Memory, Inc. | Layout method for miniaturized memory array area |
CN101673886B (zh) * | 2004-11-29 | 2012-07-25 | Fci公司 | 改进的匹配阻抗表面贴装技术基底面 |
CN110008490A (zh) * | 2015-03-17 | 2019-07-12 | 英飞凌科技奥地利有限公司 | 用于双重区域分割的系统和方法 |
CN110008490B (zh) * | 2015-03-17 | 2022-11-25 | 英飞凌科技奥地利有限公司 | 用于双重区域分割的系统和方法 |
CN105789142A (zh) * | 2016-05-05 | 2016-07-20 | 中国工程物理研究院电子工程研究所 | 一种有机基板高密度集成的三维微波电路结构 |
CN105789142B (zh) * | 2016-05-05 | 2019-10-08 | 中国工程物理研究院电子工程研究所 | 一种有机基板高密度集成的三维微波电路结构 |
Also Published As
Publication number | Publication date |
---|---|
CN1203546C (zh) | 2005-05-25 |
SG99347A1 (en) | 2003-10-27 |
MY124540A (en) | 2006-06-30 |
IL140857A (en) | 2005-12-18 |
IL140857A0 (en) | 2002-02-10 |
JP2001274288A (ja) | 2001-10-05 |
US6538213B1 (en) | 2003-03-25 |
TW478118B (en) | 2002-03-01 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION Free format text: FORMER OWNER: INTERNATIONAL BUSINESS MACHINES CORP. Effective date: 20110414 |
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C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: NEW YORK, THE USA TO: CALIFORNIA, THE USA |
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TR01 | Transfer of patent right |
Effective date of registration: 20110414 Address after: American California Patentee after: Taisala Intellectual Property Corp. Address before: American New York Patentee before: International Business Machines Corp. |
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C56 | Change in the name or address of the patentee |
Owner name: EVENSARCE CO., LTD. Free format text: FORMER NAME: TESALA INTELLECTUAL PROPERTY COMPANY |
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CP01 | Change in the name or title of a patent holder |
Address after: American California Patentee after: Tessera Inc. Address before: American California Patentee before: Taisala Intellectual Property Corp. |
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CX01 | Expiry of patent term |
Granted publication date: 20050525 |
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CX01 | Expiry of patent term |