CN110008490B - 用于双重区域分割的系统和方法 - Google Patents

用于双重区域分割的系统和方法 Download PDF

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CN110008490B
CN110008490B CN201811423613.0A CN201811423613A CN110008490B CN 110008490 B CN110008490 B CN 110008490B CN 201811423613 A CN201811423613 A CN 201811423613A CN 110008490 B CN110008490 B CN 110008490B
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semiconductor
contact pads
semiconductor die
conductive contact
electrical paths
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CN110008490A (zh
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A·伍德
E·巴彻
M·A·博戴
G·法斯钦
T·奥斯特曼
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本公开涉及用于双重区域分割的系统和方法。其中，一种用于半导体制造的方法包括形成通过分割区域和接触区域分离的半导体电路的第一阵列和半导体电路的第二阵列。该方法还包括在衬底的分割区域内形成工艺控制监控结构的第一阵列。该方法还包括形成设置在接触区域中的接触焊盘的第一阵列。该方法还包括形成工艺控制监控结构的第一阵列与接触焊盘的第一阵列之间的电连接，其中工艺控制监控结构的第一阵列的所有外部电连接均被制造为穿过接触焊盘的第一阵列。

Description

用于双重区域分割的系统和方法
技术领域
本发明总体上涉及用于半导体的分割的系统和方法，并且在具体实施例中，涉及用于双重区域分割的系统和方法。
背景技术
工艺控制监控(PCM)结构是可以在将半导体晶圆分割成单独裸片之前使用的半导体监控结构。利用PCM结构进行监控可以帮助确定制造工艺是否在适当的工艺窗内或者组成集成电路(IC)的各个器件是否在工艺规则内。
然而，现有的PCM系统由于将PCM结构和它们的导电接触焊盘放置在同一区域中而具有成本和性能的缺点。例如，在块PCM设计中，晶圆可被用于形成半导体芯片的区域被用于形成一个或多个PCM结构和接触焊盘，从而减小了每晶圆的芯片的数量。对于仅具有少量大半导体芯片的晶圆来说，这些块PCM设计牺牲了晶圆的生产部分的大部分。因此，当使用大半导体芯片时，PCM结构和它们的接触焊盘通常被放置在分割裸片的通道内。此外，分割穿过金属焊盘会引入降低生产产量的缺陷并且产生被生产的半导体芯片的可靠性问题。例如，当机械锯切被用于分割裸片时，通过硬度不同的金属和非金属材料的组合引入的振动会引起破裂、腔或者表面和/或侧壁损伤的其他形式。此外，由于金属和非金属材料显示出不同的热行为，所以由于相异的加热，使得利用激光进行分割引入了材料应力。
发明内容
根据本发明的实施例，提供了一种半导体裸片。半导体裸片包括半导体电路、导电接触焊盘和在裸片的分割边缘处终止的浮置电路径，其中电路径电耦合至导电接触焊盘。
根据本发明的另一实施例，提供了一种用于半导体制造的方法。该方法包括形成通过接触区域和分割区域分离的半导体电路装置的第一阵列和半导体电路装置的第二阵列。该方法还包括在衬底的分割区域内形成PCM结构的第一阵列。该方法还包括形成设置在接触区域中的接触焊盘的第一阵列。该方法还包括在PCM结构的第一阵列与接触焊盘的第一阵列之间形成电连接，其中PCM结构的第一阵列的所有外部电连接均通过接触焊盘的第一阵列。
根据本发明的另一实施例，提供了用于半导体制造的另一种方法。该方法包括在半导体晶圆中形成PCM结构，半导体晶圆包括用于分割穿过半导体晶圆的分割区域的完整集合，其中PCM结构被设置在完整集合内。该方法还包括在半导体晶圆中形成导电接触焊盘，其中导电接触焊盘电耦合至PCM结构，并且导电接触焊盘不被设置在完整集合内。该方法还包括仅在分割区域的完整集合内分割半导体晶圆。
根据本发明的另一实施例，提供了一种用于布局生成的方法。该方法包括获得用于分割穿过半导体晶圆的分割区域的布局位置，其中布局位置包括在表示半导体晶圆的布局中。该方法还包括获得用于PCM结构的设计并选择用于布局的布置。布置包括PCM结构的第一阵列，每一个都根据用于PCM结构的设计来进行布置，其中PCM结构的第一阵列被设置在分割区域内。布置还包括设置在接触区域中的接触焊盘的第一阵列、通过分割区域和接触区域分离的半导体电路装置的第一阵列和半导体电路装置的第二阵列、以及位于PCM结构的第一阵列和接触焊盘的第一阵列之间的电连接。PCM结构的第一阵列的所有外部电连接均通过接触焊盘的第一阵列。
附图说明
为了更完整地理解本发明及其优势，现在结合附图进行以下描述，其中：
图1A至图1E是示出根据本发明实施例的将被分割的半导体晶圆的顶视图的框图；
图2A和图2B是示出根据本发明实施例的位于晶圆的水平分离区域中的示例性PCM结构和接触焊盘的框图；
图3是示出图2A的PCM结构和一个接触焊盘的截面的框图；
图4是示出根据本发明实施例的用于生成半导体晶圆的布局设计的方法的流程图；
图5是示出根据本发明实施例的用于制造半导体晶圆的方法的流程图；以及
图6是示出根据本发明实施例的可用于实施本文公开的一些设备和方法的处理系统的框图。
具体实施方式
以下详细讨论了本发明优选实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体条件下实施的可应用的发明概念。所讨论的具体实施例仅仅是制造和使用本发明的具体方式，而不限制本发明的范围。首先结合图1A至图1E大体描述包含将被分割穿过PCM结构的裸片的示例性晶圆。更具体地，然后结合图2A和图2B提供PCM结构和接触焊盘被定位在晶圆的水平分离区域中的实施例。进一步结合图3解释该水平分布的PCM结构的截面。结合图4讨论具有PCM结构和接触焊盘的半导体晶圆的布局设计的生成方法。结合图5讨论用于根据布局制造半导体晶圆的方法。最后，结合图6描述用于实施一些示例性设备和方法的处理系统。
将参照具体条件(放置用于监控制造工艺的特定特征的PCM结构和接触焊盘的系统和方法，包括物理特性(诸如线宽、栅极轮廓、接触开口)和其他特性(诸如掺杂、电阻、电容、晶体管性能等))下的实施例来描述本发明。进一步的实施例可应用于组成完整的半导体芯片的一个或多个单独器件的测量系统和电路级性能的其他PCM系统。
图1A至图1E示出了用于实施将被分割的半导体晶圆中的示例性PCM结构和接触焊盘的双重区域。图1A是在半导体电路区域之间的垂直分离区域中具有PCM结构的示例性半导体晶圆的顶视图。图1B是图1A的半导体晶圆的仅包括四个设计副本的示例性片段的放大图。图1C是在水平分离区域中具有PCM结构的可选实施例的顶视图。图1D是在水平和垂直分离区域中均具有PCM结构的另一可选实施例的顶视图。图1E是在所有垂直分离区域和所有水平分离区域中具有PCM结构的另一可选实施例的顶视图。
现在参照图1A，半导体晶圆具有半导体电路区域107，并且这些半导体电路区域107将通过分割穿位于半导体电路区域107之间的分离区域中的分割通道而相互分离。这些分割通道是从晶圆的上部延伸到底部的三维区域。例如，通过机械锯切、激光切割或另一种分离技术来执行分割。图1A的示例性半导体晶圆在分割通道中具有小于或等于20μm的金属宽度。水平分离通道102位于水平分离区域103中，以及垂直分割通道104位于宽垂直分离区域105A和普通垂直分离区域105B中。
半导体电路区域107可以包括电路，例如垂直功率金属氧化物半导体场效应晶体管(MOSFET)、其他功率晶体管或功率芯片；二极管；传感器；微处理器或其他集成电路，包括极大规模集成(VLSI)、小规模集成(SSI)、中规模集成(MSI)或超大规模集成(ULSI)芯片；双极晶体管或者绝缘栅型双极晶体管(IGBT)。
水平分离区域103的宽度L1和普通垂直分离区域105B的宽度L3的最小值均取决于用于分割的制造容限，并且在一些实施例中，这些宽度可以相同。每个宽垂直分离区域105A的宽度L2的最小值增加到近似为普通垂直分离区域105B的宽度L3的两倍以容纳用于定位PCM结构的PCM区域108和用于定位接触焊盘的焊盘区域109。在一些实施例中，L2小于L3的两倍，因为分割宽度容限可以至少部分地集成到焊盘区域109中。在一些实施例中，所有垂直分离区域都被加宽以容纳PCM区域108和焊盘区域109或者提供恒定的阶梯间距以减小用于分割晶圆的设备的复杂度。
光刻工艺使用石英板中间掩模(reticle)或者光掩模以形成晶圆的结构。尽管在图1A中示出了通过步进式光刻形成的晶圆结构，但其他实施例使用掩模对准光刻，其中全晶圆光掩模在单个曝光中在整个晶圆上形成图像。在步进式光刻实施例中，中间掩模将在晶圆表面的1/100或1/50上形成图像，并且该图案是使用步进机横跨晶圆逐步形成的设计副本。在图1A的示例性晶圆中，只出现了8个这样的设计副本101，并且在每个设计副本101中仅出现了8个半导体电路区域107。在一些实施例中，设计副本102可以横跨整个晶圆逐步形成一百次，并且半导体电路区域107可以在每个设计副本101中出现一百次。在图1A和图1B的实施例中，出现比半导体电路107少的宽垂直分离区域105A，因为PCM区域108在每个设计副本101中比半导体电路区域107出现的频率小。其他示例性晶圆具有相等数量的加宽分离区域和半导体电路区域。给定的晶圆设计可以使用一系列中间掩模以在制造工艺的不同阶段形成半导体电路区域的不同层。例如，可以使用计算机辅助设计(CAD)生成中间掩模的布局。
在一些实施例中，布局将包括多个设计副本，它们具有PCM结构、接触焊盘、电路径和互连的不同布置。例如，第一布置可以设置在半导体晶圆的将被首先分割的区域中，并且第二不同的布置可以设置在半导体晶圆的稍后被分割的区域中。在一个实施例中，第一布置可用于缓解最可能在首先分割的区域中形成的缺陷的形成。例如，第一设计可以在第一布置中形成PCM结构和接触焊盘，其最佳地例如通过在垂直分割通道104中使用较低的金属含量来缓解缺陷形成。第二设计可以提供其他优势，诸如通过使用更多的金属互连将连接焊盘电耦合至PCM结构来降低电阻。
现在参照图1B，顶视图示出了半导体晶圆的示例性晶圆片段100的顶视图，其包括用于实施示例性PCM结构111的区域。本领域技术人员应理解，PCM结构111可以包括用于PCM的各种结构，诸如电容器、电阻器、接触电阻结构、二极管、MOSFET、双极晶体管、IGBT、加热器、隔离检查结构、可靠性测试结构、层堆叠结构等。对于基于硅、碳化硅、硅锗、碳(包括石墨)或类似半导体材料的晶圆技术来说，PCM结构可以由任何前述材料或它们的衍生材料(例如，前述材料的氧化物、氮化物或酰亚胺、多晶硅或其他衍生介电材料)制成。使用基于III-V或II-VI化合物半导体衬底的晶圆技术的其他实施例可使用也基于组成衬底的一种或多种元素的PCM结构。这种III-V和II-VI化合物衬底例如可以包括氮化镓、砷化镓、砷化铟、磷化镓、磷化铟、砷化铝、氮化铝、硫化镉、硫化锌、锑化镉和锑化锌。在又一些其他实施例中，类似于半导体电路区域107被监控，PCM结构也可以包含少量的金属或金属化合物(小于5％)，诸如铝、铜、钛、钨、钴、铂、钯、钼、镍、钒、银、金和金属硅化物、金属氮化物以及前述金属的合金。相比而言，如图1B所示，表面接触焊盘106A和隐埋接触焊盘106B可以整个由这些金属和金属化合物制成。
再次参照图1B，示例性晶圆片段100的四个象限是将在水平分割通道102和垂直分割通道104处被分割(即，分离)以制造四个半导体芯片的四个裸片。晶圆片段100的每个象限都包含半导体电路区域107，其将被组装到封装半导体产品中。每个半导体电路区域107都包含有源区域114和密封环110。密封环110是环绕有源区域114并保护有源区域114免受例如由静电放电(ESD)引起的问题和由分割引起的损伤(例如，由机械锯切引起的破裂)的终端结构的一部分。密封环110可以包括缺陷停止区域112，其包括位于晶圆的顶部绝缘层上的间隙并且被设计为防止在分割表面上形成的任何破裂或碎片传播到有源区域114中。密封环110还可以包括湿气阻挡以防止湿气进入有源区域114。
再次参照图1B，晶圆的宽垂直分离区域105A被加宽以容纳PCM结构111(存在于PCM区域108中)以及表面接触焊盘106A和隐埋接触焊盘106B(存在于不同的焊盘区域109)。例如，每个焊盘区域109都可以与PCM区域108相邻。表面接触焊盘106A和隐埋接触焊盘106B用于将外部监控设备连接至PCM结构111。在图1B的示例性晶圆中，与隐埋接触焊盘106B的任何连接均在其隐埋在晶圆表面下之前的步骤中进行，而与表面接触焊盘106A的连接可仍然执行，因为这些焊盘从不被隐埋。表面接触焊盘106A和隐埋接触焊盘106B由导电材料制成。
外部监控设备可通过例如使用导电探针连接至表面接触焊盘106A(隐埋之前连接至隐埋接触焊盘106B)来监控PCM结构111。在一个实施例中，表面接触焊盘106A和隐埋接触焊盘106B由相同的金属层制成，该金属层将在分割之后用于实现从例如包含分割裸片的密封封装件的接合线到每个裸片的顶面的电源金属接合连接。在一些实施例中，接触焊盘具有50μm x 50μm的级别的尺寸，以能够实现具有探针的一致连接。
在图1B的实施例中，PCM区域108位于垂直分割通道104中。由于表面接触焊盘106A和隐埋接触焊盘106B位于与垂直分割通道104分离的区域中，所以存在于垂直分割通道104中的任何金属结构都具有小于或等于20μm的金属宽度，这小于能够实现与测试探针的一致连接所需的最小宽度。在一些实施例中，存在于任何水平或垂直分割通道中并且还电耦合至PCM结构的任何金属结构都具有窄于测试探针的尖端宽度的金属宽度。通过降低垂直分割通道104中的金属含量，避免了分割期间对裸片的损伤。在其他实施例中，PCM结构111存在于水平分割通道102(其缺少宽于20μm的金属结构)中或者水平和垂直分割通道(它们均缺少宽于20μm的金属结构)中。
在图1B的实施例中，PCM区域108在垂直分割通道104内的放置允许PCM结构111在分割期间被损坏，这防止了与最终产品的PCM结构的未经授权的连接以及制造工艺的反向工程。在其他实施例中，PCM区域108位于水平分割通道中以防止反向工程。在用于反向工程较少受到关注的应用的又一些实施例中，PCM区域108不位于水平分割通道102或垂直分割通道104中。
图1B的实施例还包含位于垂直分离区域105中的材料测量块116，其可用于工艺监控的其他方面。在其他实施例中，分离区域还包含允许晶圆的一层上的部件与正在形成的目标结构对齐的对齐结构。图1B的材料测量块116可以包括氧化物测量区域，其包含可使用干涉计进行厚度测量的氧化物的块。材料测量块116还可以包含掺杂测量区域，用于监控表示晶圆的各个区域的掺杂等级，例如使用扫描电容测量和包括扩展电阻测量、二次离子质谱法等的破坏性技术。
现在参照图1C，在可选实施例中，宽水平分离区域103A相对于普通水平分离区域103B加宽以容纳可选设计副本101B的PCM区域108和焊盘区域109。用于每个宽水平分离区域103A的宽度L4的最小值增加以近似为普通水平分离区域103B的宽度L1的两倍，以容纳用于定位PCM结构的PCM区域108和用于定位接触焊盘的焊盘区域109。在一些实施例中，L4小于L1的两倍，因为分割宽度容限可以至少部分地集成到焊盘区域109中。在其他实施例中，所有水平分离区域都被加宽。半导体电路区域的纵横比可以是选择水平分离区域还是垂直分离区域被加宽的因素。例如，在图1C的实施例中，半导体电路区域107A的顶面的垂直尺寸大于水平尺寸。
现在参照图1D，在第二可选实施例中，宽垂直分离区域105A和宽水平分离区域103A分别相对于普通垂直分离区域105B和普通水平分离区域103B加宽以容纳PCM区域108和焊盘区域109。在其他实施例中，所有水平分离区域都被加宽，同时只有一些垂直分离区域被加宽，反之亦然。
现在参照图1E，在第三可选实施例中，所有垂直分离区域105A和所有水平分离区域103A分别相对于普通垂直分离区域105B和普通水平分离区域103B(图1D所示)加宽，以容纳PCM区域108和焊盘区域109。
图2A和图2B示出了位于晶圆的水平分离区域207中的示例性PCM结构和接触焊盘的顶视图。图2A示出了分割之前的晶圆，以及图2B示出了分割之后的晶圆的单个裸片。
现在参照图2A，示例性PCM结构202包括在两个半导体电路区域204A-B之间的水平分割通道203中与晶圆的顶面相邻的多晶硅电阻器。接触焊盘205A-D通过多晶硅路径208、金属迹线211和形成电路径的硅路径212电耦合至PCM结构202。PCM结构202还经由电路径206(隐埋在晶圆表面下方)电耦合至半导体电路区域204B。在其他实施例中，PCM结构可以通过表面路径耦合至半导体电路区域。在又一些其他实施例中，单个PCM结构可以耦合至多个半导体电路区域。
接触焊盘205A通过多晶硅路径208电耦合至PCM结构202。多晶硅提供了电阻高于金属导体的电路径，但是有利地降低了分割通道203的金属含量。这种多晶硅连接可以用于PCM测量值具有较高的接触电阻容限的示例性应用中。
耦合至PCM结构的金属导体还可以用于敏感测量，例如敏感电阻测量。例如，在图2A的具体实施例中，直接金属互连210使用金属迹线211电耦合至接触焊盘205B和205C。在一个实施例中，金属导体被制造得尽可能窄以降低分割区域中的金属含量，同时仍然足够宽使得不对测量引入过量的阻抗。在一个实施例中，金属导体由与接触焊盘相同的材料制成。
通过例如使用深沟槽隔离在半导体路径的任一侧上设置隔离，从接触焊盘到PCM结构的电路径还可以由与晶圆衬底相同的材料制成。例如，在图2A的实施例中，设置在晶圆衬底中的硅路径212将接触焊盘205D电耦合至PCM结构202。
在一些晶圆中，接触焊盘和PCM结构之间的不同电路径被设计为由不同材料组成。例如，在一个示例性晶圆设计中，这些电路径的42％由金属组成，剩余的58％由半导体材料(诸如多晶硅或与晶圆衬底相同的材料)组成。在各个实施例中，接触焊盘和PCM结构之间的电路径的至少50％由半导体材料组成。在又一些其他实施例中，接触焊盘和PCM结构之间的电路径的至少50％由金属组成。
图2B示出了沿着分割通道203进行分割之后的图2A的裸片。图2B的接触焊盘205A-D中的每一个都不与任何半导体电路区域连接，并且具有在裸片的分割边缘214处终止的导电连接。例如，接触焊盘205B-C均没有在分割边缘214处终止的金属迹线211。焊盘205A具有在分割边缘214处终止的多晶硅路径208。接触焊盘205D具有在分割边缘214处终止的硅连接212。
图3示出了图2A的PCM结构202和接触焊盘205A的截面，它们均位于两个半导体电路区域204A和204C之间的水平分离区域207中。每个半导体区域都具有与其边缘邻近的破裂停止部302。接触焊盘205A接触下面的多晶硅区域303(其被部分地隐埋在绝缘层304中并且位于剩余的晶圆层306上方)。绝缘层304的薄部还覆盖水平分割通道203内的PCM结构202。在其他实施例中，PCM结构被暴露给顶面308并且不被任何层覆盖。在又一些实施例中，PCM被向下隐埋到几微米的深度。水平分割通道203是用于分割穿过半导体晶圆的三维区域。水平分割通道203与PCM结构202相交并且还与顶面308和底面310相交，但是不与接触焊盘205A相交。
图4是示出用于例如使用CAD软件应用生成半导体晶圆的布局设计的示例性方法的流程图。在步骤401中，接收用于PCM结构和导电接触焊盘的组合设计。组合设计还可以包括需要仅与金属迹线连接的敏感器件的列表。在步骤402中，从组合设计中提取PCM结构的设计，使得用于PCM结构的提取设计缺少宽于20μm的金属结构。在步骤404中，针对根据提取设计布置的PCM结构的阵列选择布局位置。选择这些布局位置，使得PCM结构的阵列在分割通道内。在步骤406中，选择用于接触焊盘的阵列的布局位置，使得分割穿过分割通道不包括分割穿过接触焊盘。PCM结构的阵列中的每个PCM结构都例如可以与接触焊盘的阵列中的至少一个接触焊盘相邻。布局生成器还接收提供需要考虑的各种规则同时生成布局的技术规范。技术规范中的一个规则可以包括使得允许用于分割通道的总金属含量最大化，从而使得破裂和其他效应最小化。一些实施例可以包括使总金属焊料最小化，使得敏感部件与金属线连接。布局可以将接触焊盘设计为与半导体晶圆的金属层连续。布置电连接以将PCM结构耦合至接触焊盘，使得与PCM结构的所有外部电连接都被制造为通过接触焊盘。这些电连接可以被设计为由多晶硅、金属形成，或者由组成半导体衬底的材料形成，但是电连接如技术规范中所允许的尽可能多使用非金属互连。在步骤408中，选择用于半导体电路的布局位置，使得通过分割区域分离半导体电路的阵列。在步骤410中，完成半导体晶圆的布局的剩余部分。
图5是示出用于半导体制造的示例性方法的流程图。在步骤501中，根据用于半导体晶圆的布局设计生成至少一个中间掩模。在步骤502中，根据至少一个中间掩模形成PCM结构，使得PCM结构不包括宽于20μm的金属结构，并且PCM结构通过分割通道相交。作为示例，PCM结构可以设置在晶圆的半导体电路区域之间。在步骤504中，根据至少一个中间掩模形成导电接触焊盘，使得接触焊盘不通过分割通道相交。作为示例，PCM结构和接触焊盘彼此相邻。接触焊盘可以由半导体晶圆的金属层形成。在步骤506中，电路径(诸如多晶硅路径、金属路径或者由半导体材料制成的路径)被形成为电耦合至PCM结构和导电接触焊盘。在步骤508中，半导体晶圆被分割穿过PCM结构但是不穿过接触焊盘。将晶圆分割成多个裸片会损伤PCM结构而不损伤接触焊盘。
图6示出了可用于实施本文公开的布局生成方法的处理系统的框图。具体设备可以利用所示的所有部件或者仅是部件的子集，并且集成等级可以根据设备而不同，此外，设备可以包含部件的多个示例，诸如多个处理单元、处理器、存储器、发射器、接收器等。在一个实施例中，处理系统包括计算机工作站。处理系统可以包括装配有一个或多个输入/输出设备的处理单元，诸如扬声器、麦克风、鼠标、触摸屏、按键、键盘、打印机、显示器等。处理单元可以包括CPU、存储器、大型存储器设备、视频适配器和连接至总线的输入/输出(I/O)接口。在一个实施例中，单个处理系统或多个处理系统中的多个处理单元可以形成分布式处理池或分布式编辑池。
大容量存储设备可以包括任何类型的存储设备，其被配置为存储数据、程序或者其他信息，并且使得可经由总线访问数据、程序和其他信息。大容量存储设备例如可以包括固态驱动、硬盘驱动、磁盘驱动、光盘驱动等的一个或多个。
本发明的所示实施例具有提供增加的可靠性而不显著增加成本的优势。例如，示例性双重区域结构可用于通过机械切割生成半导体芯片而不引入显著的破裂。在一些实施例中，示例性双重区域结构被用于半导体晶圆，其被激光分割以由于分割通道中降低的金属焊料而允许裸片边缘更均匀的加热。
虽然参照所示实施例描述了本发明，但这种描述并不用于限制。本领域技术人员在参照说明书的基础上，可以实现所示实施例的各种修改和组合以及本发明的其他实施例。因此，所附权利要求包括任何这些修改或实施例。

Claims (19)

1.一种半导体裸片，包括：
半导体电路，设置在衬底内或衬底上；
导电接触焊盘，设置在所述半导体电路外部的衬底上；以及
电路径，在所述裸片的分割边缘处终止，其中所述电路径电耦合至所述导电接触焊盘，而不电耦合至所述半导体电路。
2.根据权利要求1所述的半导体裸片，其中所述电路径包括多晶硅路径。
3.根据权利要求1所述的半导体裸片，其中所述电路径包括所述半导体电路的衬底材料。
4.根据权利要求1所述的半导体裸片，其中所述电路径包括铝、铜、钛、钨、钴、铂、钯、钼、镍、钒、银、金、铝、金属硅化物和金属氮化物中的至少一种。
5.根据权利要求1所述的半导体裸片，其中所述导电接触焊盘包括铝、铜、钛、钨、钴、铂、钯、钼、镍、钒、银、金、铝、金属硅化物和金属氮化物中的至少一种。
6.根据权利要求1所述的半导体裸片，其中所述半导体电路包括金属氧化物半导体场效应晶体管(MOSFET)、双极型晶体管、绝缘栅双极晶型体管(IGBT)、二极管、传感器和集成电路中的至少一种。
7.一种半导体裸片，包括：
有源区域，包括设置在衬底内或衬底上的半导体电路；
围绕所述有源区域的密封环；
焊盘区域，设置在所述有源区域外部的所述密封环的一侧；
设置在所述焊盘区域中的多个导电接触焊盘；以及
多个电路径，在所述裸片的分割边缘处终止，其中所述多个电路径中的每一个从所述多个导电接触焊盘的接触焊盘延伸，而不电耦合至所述半导体电路。
8.根据权利要求7所述的半导体裸片，其中所述多个电路径包括多晶硅线。
9.根据权利要求7所述的半导体裸片，其中所述多个电路径包括所述衬底的衬底材料。
10.根据权利要求7所述的半导体裸片，其中所述多个电路径包括铝、铜、钛、钨、钴、铂、钯、钼、镍、钒、银、金、铝、金属硅化物或金属氮化物。
11.根据权利要求7所述的半导体裸片，其中所述多个导电接触焊盘包括铝、铜、钛、钨、钴、铂、钯、钼、镍、钒、银、金、铝、金属硅化物或金属氮化物。
12.根据权利要求7所述的半导体裸片，其中所述半导体电路包括金属氧化物半导体场效应晶体管(MOSFET)、双极型晶体管、绝缘栅双极晶型体管(IGBT)、二极管、传感器或集成电路。
13.根据权利要求7所述的半导体裸片，其中所述多个导电接触焊盘包括表面接触焊盘和隐埋接触焊盘。
14.根据权利要求7所述的半导体裸片，其中所述密封环包括缺陷停止区域，所述缺陷停止区域包括在所述衬底的最上面的绝缘层上的间隙。
15.一种半导体裸片，包括：
有源区域，包括设置在衬底内或衬底上的半导体电路；
围绕所述有源区域的密封环；
第一焊盘区域，设置在所述有源区域外部的所述密封环的第一侧上；
第二焊盘区域，设置在所述有源区域外部的所述密封环的第二侧上；
多个第一导电接触焊盘，设置在所述第一焊盘区域中；以及
多个第一电路径，在所述半导体裸片的第一边缘处终止，其中所述多个第一电路径中的每一个从所述多个第一导电接触焊盘中的相应的一个接触焊盘延伸，而不电耦合至所述半导体电路；
多个第二导电接触焊盘，设置在所述第二焊盘区域中；以及
多个第二电路径，在所述半导体裸片的第二边缘处终止，其中所述多个第二电路径中的每一个从所述多个第二导电接触焊盘中的相应的一个接触焊盘延伸，而不电耦合至所述半导体电路。
16.根据权利要求15所述的半导体裸片，其中所述第一侧与所述第二侧相交。
17.根据权利要求15所述的半导体裸片，其中所述多个第一电路径在远离所述多个第一导电接触焊盘的第一方向上延伸，其中所述多个第二电路径在远离所述多个第二导电接触焊盘的第二方向上延伸，并且其中所述第一方向垂直于所述第二方向。
18.根据权利要求15所述的半导体裸片，其中所述多个第一电路径和所述多个第二电路径包括多晶硅线。
19.根据权利要求15所述的半导体裸片，其中所述多个第一电路径和所述多个第二电路径包括硅。
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