US20080237048A1 - Method and apparatus for selective electrofilling of through-wafer vias - Google Patents

Method and apparatus for selective electrofilling of through-wafer vias Download PDF

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US20080237048A1
US20080237048A1 US11694655 US69465507A US20080237048A1 US 20080237048 A1 US20080237048 A1 US 20080237048A1 US 11694655 US11694655 US 11694655 US 69465507 A US69465507 A US 69465507A US 20080237048 A1 US20080237048 A1 US 20080237048A1
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hollow
opening
body
solution
wafer
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US11694655
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Ismail Emesh
Ivo Raaijmakers
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ASM NuTool Inc
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ASM NuTool Inc
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00Electroforming
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00Electroforming
    • C25D1/02Tubes; Rings; Hollow bodies
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for plating wafers, e.g. semiconductors, solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/10Electrodes, e.g. composition, counter electrode
    • C25D17/12Shape or form
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00Processes for servicing or operating cells for electrolytic coating
    • C25D21/10Agitating of electrolytes; Moving of racks
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/04Electroplating with moving electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

Abstract

A device for electrodepositing a conductive material from a first solution into at least one feature formed on a wafer includes a hollow body, an electrode, and a moving mechanism. The hollow body includes a first opening and a second opening. The first solution is supplied to the second opening and injected from the first opening. The electrode is disposed within the hollow body. A potential difference is applicable between the first electrode and the surface of the wafer to electrodeposit the conductive material into the at least one feature. The moving mechanism is mechanically coupled to the hollow body. The moving mechanism is configured to position the first opening of the hollow body over the at least one feature.

Description

    FIELD
  • [0001]
    The present invention generally relates to semiconductor IC processing technologies and, more particularly, to a method and apparatus for forming deep vias.
  • BACKGROUND
  • [0002]
    Integrated circuits (ICs) include many devices and circuit members that are formed as dies on a single semiconductor wafer. The current trends in IC technology are towards faster and more powerful circuits. However, as more complex ICs are manufactured, such as microprocessors having high operating frequency ranges, various speed related problems are becoming increasingly challenging. This is especially true when ICs having different functions are used to create electronic systems, for example computing systems including processor and memory ICs, where different ICs are electrically connected by a global interconnect network. However, as the global interconnects become longer and more numerous in the electronic systems, resistive capacity (RC) delay and power consumption, as well as low system performance, are becoming limiting factors.
  • [0003]
    One proposed solution to this problem is three dimensional (3-D) integration or 3-D IC packaging technology, where 3-D integration refers to the vertical stacking of multiple dies including ICs within a package. In 3-D integration technology, multiple dies are electrically connected using vertical interconnects or 3-D conductive vias, which may have depths as well as widths or diameters as large as about 100 micrometers or greater. 3-D vias extend through one or more of the wafers and are aligned when the wafers are stacked to provide electrical communication among the ICs in the stacked wafers. 3-D packaging may result in reductions of size and weight of the IC package, reduction in power consumption, and an increase in performance and reliability.
  • [0004]
    In general, to fabricate the 3-D interconnects, initially deep vias are formed in the wafers, which are subsequently filled with a conductive material, typically a metal such as copper due to its low electrical resistivity and electromigration characteristics. Electroplating is one of the preferred methods to fill deep vias. Although traditional electroplating technology has been successfully applied to fill relatively shallow vias between levels within chips (“interlevel vias”), electroplating such relatively deep vias for 3-D integration with the same technology presents difficulties. For example, to adequately fill such deep vias, it is typical to deposit relatively thick layers of metal over the surface of the wafer. A subsequent planarization process (e.g., chemical mechanical planarization (CMP) processes) may then be used to remove the conductive material from the wafer surface and to level the wafer surface for subsequent manufacturing steps. The deposition and planarization of thick layers of conductive material increase the costs of IC fabrication and decrease throughput. Additionally, forming thick layers of conductive material on the wafer increases stress within the wafer, and may induce stress-related defects. Another problem associated with the 3-D integration, which also reduces deposition throughput, includes the usage of low current densities. Since the features to be filled in 3-D processes are larger compared to interlevel vias, the plating current densities must be limited to a low range that does not cause defects such as voids in the large vias.
  • [0005]
    To this end, there is a need for alternative methods of depositing conductive materials into deep vias without causing defects.
  • SUMMARY
  • [0006]
    In certain embodiments, a device for electrodepositing a conductive material from a first solution into at least one feature formed on a wafer comprises a hollow body, an electrode, and a moving mechanism. The hollow body includes a first opening and a second opening. The first solution is supplied to the second opening and injected from the first opening. The electrode is disposed within the hollow body. A potential difference is applicable between the first electrode and the surface of the wafer to electrodeposit the conductive material into the at least one feature. The moving mechanism is mechanically coupled to the hollow body. The moving mechanism is configured to position the first opening of the hollow body over the at least one feature.
  • [0007]
    In certain embodiments, a method of electrodepositing a conductive material into a 3-D via to form a conductive structure for 3-D integration comprises providing an electrodeposition device comprising a first hollow body including a first opening and a second opening, a first electrode disposed within the first hollow body, and a moving mechanism mechanically coupled to the first hollow body. The method further comprises holding a wafer with a wafer carrier. A surface of the wafer includes at least one via. The method further comprises operating the moving mechanism to position the first opening of the first hollow body proximate to a first via of the wafer surface, supplying a solution to the second opening of the first hollow body, flowing the solution out of the first opening of the first hollow body and into the first via, and applying a potential difference between the first electrode and the surface of the wafer.
  • [0008]
    In certain embodiments, a method of electrofilling a conductor into a deep feature formed on a surface of a wafer using an electrodeposition device having an opening comprises holding the wafer by a wafer carrier, positioning the opening of the device over the deep feature, and electrodepositing the conductor only into the deep feature without electrodepositing the conductor onto the surface of the wafer.
  • [0009]
    All of these embodiments are intended to be within the scope of the invention herein disclosed. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of the preferred embodiments having reference to the attached figures, the invention not being limited to any particular preferred embodiment(s) disclosed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    These and other features, aspects, and advantages of the invention disclosed herein are described below with reference to the drawings of preferred embodiments, which are intended to illustrate and not to limit the invention.
  • [0011]
    FIG. 1 illustrates an embodiment of an electrodeposition device for filling a deep via;
  • [0012]
    FIG. 2 illustrates another embodiment of an electrodeposition device for filling a deep via;
  • [0013]
    FIG. 3 illustrates yet another embodiment of an electrodeposition device for filling multiple deep vias;
  • [0014]
    FIG. 4 illustrates an embodiment of an electrodeposition device for sequential filling of multiple deep vias having different dimensions;
  • [0015]
    FIG. 5 illustrates an embodiment of an electrodeposition device including an example integrated electrode assembly for simultaneous filling of multiple deep vias having different dimensions;
  • [0016]
    FIGS. 6A-6D illustrate an example process of a method of manufacturing the integrated electrode assembly of FIG. 5;
  • [0017]
    FIG. 7A illustrates a deep via after being selectively filled with a conductive material; and
  • [0018]
    FIG. 7B illustrates the deep via of FIG. 7A after a planarization process.
  • DETAILED DESCRIPTION
  • [0019]
    The present invention provides a method and a plating device or a microplating device to form 3-D integration structures for 3-D integration of chip stacks. The plating device of the present invention is able to selectively electrodeposit or electrofill conductive materials in deep features such as, but not limited to, 3-D vias and trenches formed on semiconductor wafers to manufacture 3-D integration structures or through wafer conductive structures. Certain embodiments of electrodeposition devices of the present invention include a hollow body (or “injector”) having an electrode (anode) that is configured to be in electrical communication with a plating or deposition solution (e.g., when the deposition solution is flowed through the hollow body by being disposed in the hollow body). During the deposition process, a first opening of the hollow body is positioned proximate to (e.g., over) a top opening of a 3-D via and the deposition solution is delivered or injected into the via. As the deposition solution is delivered into the via, a potential difference is applied between the wafer surface and the electrode in electrical communication with the deposition solution. In some embodiments, a moving mechanism with an associated control system is configured to move and position the hollow body proximate to (e.g., over) the top opening of a via formed on the wafer to selectively fill the via. As used herein, the phrase “moving mechanism” is to be interpreted as a mechanism configured to move something, and need not be in the state of movement. In some embodiments, a moving mechanism with an associated control system is configured to move the hollow body proximate to (e.g., over) the top openings of multiple vias formed on the wafer to selectively fill the vias. After the via is filled with the conductive material, the backside of the wafer may be polished to expose a bottom portion of the 3-D conductive structure or 3-D conductive plug, thereby allowing a chip or wafer comprising the filled via to be used in 3-D integration.
  • [0020]
    Although it is not necessary, the first opening of the plating device may have substantially the same geometric shape as the top opening of the via hole. The dimensions of the first opening, i.e., diameter or width of the first opening, may be substantially equal to or smaller than the dimensions of the top opening of the via, i.e., diameter or width of the top opening, that will be filled. However, the dimensions of the first opening may also be larger than the dimensions of the top opening to accommodate alignment tolerance. For example, if a via is designed to have a diameter of 100 micron and to be in a certain position, the hollow body may be designed to have a first opening with a diameter of 100 micron and to move to the position of the via. If the via created is actually 105 microns and the positioning of the first opening and/or via is offset by 5 microns, the first opening would not cover at least 10 microns, which may result in defects. However, if the first opening of the hollow body is designed to have an opening of 120 microns, the first opening would cover the entire via, even if the via is 5 microns too large and misaligned by 5 microns. In certain embodiments, the dimension of the first opening is sized based on the tolerances of the via creation processes such that the top opening of the via is covered by the first opening of the hollow body.
  • [0021]
    In some embodiments, the plating device comprises multiple hollow bodies each having a first opening, wherein such first openings have different geometries and/or are differently sized, for example to operate on wafers having a plurality of vias with differently shaped or sized top openings. In certain such embodiments, as described below, the device comprises a mechanism to selectively deposit using one or more of the hollow bodies.
  • [0022]
    The plating device of the present invention and the selective plating method will be described below in the context of specific example embodiments for copper deposition, although the electrodeposition of other metals is also possible. The plating device can eliminate many of the problems associated with conventional electroplating techniques used in filling deep features such as vias. The device is able to selectively deposit a void-free conductor substantially only into the vias, thereby resulting in little or no conductor overburden on the surface of the wafer. A small overburden of conductive material can reduce or eliminate the time of subsequent CMP processes, thereby increasing IC fabrication throughput. Substantially not depositing conductive material overburden can decrease the stress of the wafer, thereby reducing stress-related defects.
  • [0023]
    In some embodiments, as the conductor is deposited from a first process solution using a hollow body of the plating device, the surface of the wafer is wetted by a second process solution. In certain embodiments, the first process solution comprises an electrolyte (e.g., copper sulfate). In certain embodiments, the first process solution consists essentially of an electrolyte (e.g., copper sulfate without an accelerator or a suppressor). In certain embodiments, the second process solution comprises an electrolyte and at least one additive such as an accelerator or a suppressor (e.g. comprising both an accelerator and a suppressor).
  • [0024]
    FIG. 1 illustrates an example embodiment of a plating device 100 that can be used to selectively fill a 3-D via 102 and/or a deep feature formed in a substrate 104 to form 3-D integration structures. The substrate 104 may be a portion of a semiconductor wafer held by a wafer carrier (FIGS. 3 and 4). The via 102 may have a largest lateral dimension (e.g., width or diameter) between about 10 and 100 microns, or greater than about 100 microns and aspect ratios (depth-to-width ratio) greater than about 5:1, even greater than about 10:1. The via 102 may have straight walls (e.g., as shown in the figures) or walls that at least partially taper (e.g., from a wider portion at the top to a narrower portion at the bottom).
  • [0025]
    To electrodeposit a conductive material into the via 102, the interior surfaces of the via 102 and the surface 106 of the substrate 104 are coated with a dielectric layer 108 (e.g., comprising SiO2). A conductive film 110 having a surface 111 is then formed on the dielectric layer 108. The conductive film 110 may comprise a barrier layer, for example a stacked barrier layer including Ta/TaN or a Ruthenium (Ru) barrier layer, which may be deposited using, for example, ALD (atomic layer deposition) or CVD (chemical vapor deposition) techniques. An example thickness for the conductive film 110 is about 1000 Angstroms (A). In certain embodiments, the conductive film is conformal. If the conductive film 110 comprises a Ta/TaN barrier layer, the conductive film 110 may further comprise a copper seed layer lining the barrier layer for copper electrodeposition. If the conductive film 110 comprises a Ru layer, direct electrodeposition of copper onto the Ru layer is possible without a copper seed layer if the appropriate chemistries are used in the plating solution. In the example illustrated in FIGS. 1 and 2, the conductive film 110 represents a barrier layer and copper seed layer for copper electroplating. During the electroplating process illustrated in FIGS. 1 and 2, copper is deposited into the via 102 through a top opening 112 of the via 102.
  • [0026]
    Referring to FIG. 1, the plating device 100 comprises a hollow body 113 having a first opening 114 and a second opening 116. The hollow body 113 may have an inner cavity 117 and may be shaped as an injector, a fluid channel, or a conduit. The hollow body may be made of an insulator such as a polymer, glass, ceramic, or any other material which is inert under the process conditions. In certain embodiments, an electrode (anode) 118 is disposed in the inner cavity 117 of the hollow body 113 and is in electrical communication with a first terminal of a power supply 130, although any suitable configuration in which the electrode 118 is in electrical communication with a solution in the inner cavity 117 is possible. In some embodiments, the uniformity of the deposition is related to the distance between the electrode 118 and the via 102. The electrode 118 may comprise a noble metal such as platinum. A plating solution 119 enters the hollow body 113 at the second opening 116 and leaves the hollow body 113 through the first opening 114. With respect to the direction of flow of the plating solution 119, the electrode 118 is upstream of the first opening 114 of the hollow body 113. The plating solution 119 may be an electrolyte (e.g., an electrolyte comprising CuSO4) and may include additives such as accelerators and suppressors. Alternatively, the plating solution may be an electrolyte (e.g., an electrolyte comprising CuSO4) without additives to reduce or eliminate the consumption of such additives (e.g., accelerator and/or suppressor) by the electrode (anode) 118. The second opening 116 of the hollow body 113 may be in fluid communication with a plating solution supply tank (not shown).
  • [0027]
    The first opening 114 of the hollow body 113 and the top opening 112 of the via 102 may have substantially similar lateral geometries and/or lateral dimensions. For example, first opening 114 of the hollow body 113 may have a largest lateral dimension (e.g., the diameter of a circular first opening 114, the major axis of an elliptical first opening 114, the longest diagonal of a polygonal first opening 114, etc.) that is substantially the same as the largest lateral dimension of the top opening 112 of the via 102 (e.g., the diameter of a circular via 102, the major axis of an elliptical via 102, the longest diagonal of a polygonal via 102, etc.). In embodiments in which the electrode 118 is disposed in the hollow body 113, the electrode 118 may have a width or diameter larger or smaller than the width or diameter of the first opening 114. In certain such embodiments, if the width or diameter of the electrode 118 is larger than the width or diameter of the first opening 114, the shape of the hollow body 113 accommodates a wider electrode 118. The electrode 118 may be shaped as cylindrical, cubic, rectangular prism, or the like, and may include holes or apertures configured to flow the plating solution 119 therethrough. Alternatively, the electrode may be shaped as a hollow cylinder or tube which can be fitted into the hollow body, thereby forming a circumferential electrode or anode which allows electrolyte to flow through it. After the via 102 is filled with plating solution 119, excess or used (or “spent” or “depleted”) plating solution 119 flows over the surface 111 of the conductive film 110.
  • [0028]
    As described more fully below, a moving mechanism may move the hollow body 113 proximate to an top opening 112 of a via 102 (e.g., over the top opening 112 as illustrated in FIG. 1) or proximate to (e.g., over) the top openings of multiple vias on the wafer to selectively fill the vias. During an example deposition process, the first opening 114 of the hollow body 113 of the plating device 100 is positioned proximate to the top opening 112 of the via 102 in the manner exemplified in FIG. 1 to selectively deposit a conductive material (e.g., comprising copper) into the via 102. As the plating solution 119 is delivered from the plating device 100 into the via 102 through the first opening 114 of the hollow body 113, a potential difference is applied between the electrode 118 and the conductive film 110, which is in electrical communication with a second terminal (more negative with respect to the first terminal) of the power supply 130 to deposit a conductive material (e.g., comprising copper) from the plating solution 119 into the via 102. An example current density is between about 50 mA/cm2 and 100 mA/cm2 operating in galvanostatic mode only, although other current densities and operating conditions are also possible. Electrical communication between the conductive film 110 and the power supply 130 may be made, for example, through stationary or moving electrical contacts.
  • [0029]
    Once a potential difference is formed between the electrode 118 and the conductive film 110, an electric field may be directed into the via 102. The electric filed is directed by the media in which it is conducted (i.e., the first solution 119 comprising an electrolyte). The electric field applied through the hollow body 113 and the plating solution 119 flowing through the hollow body 113 limit the deposition process to occur substantially only within the via 102, and advantageously fills the via 102 with a conductive material deposit with little or no conductive material deposition occurring on the surrounding wafer surface 111. The process conditions (e.g., solution flow rate, concentration of electrolyte, applied potential, etc.) may be adjusted to optimize deposition rate.
  • [0030]
    FIG. 2 shows an example embodiment of a plating device 200 that can be used to selectively fill the 3-D via 102 and/or a deep feature such as a 3-D vertical structure hole formed in the substrate 104. As described above for the plating device 100, the substrate 104 may be a portion of a semiconductor wafer held by a wafer carrier (FIGS. 3 and 4). In the embodiment illustrated in FIG. 2, the plating device 200 comprises a hollow body 202 having a solution inlet 204 to deliver a plating solution 119 from a solution tank (not shown) into an inner cavity 205 of the hollow body 202. In certain embodiments, an electrode (anode) 206 is disposed in the inner cavity 205 of the hollow body 202 and is in electrical communication with a first terminal of a power supply 130, although any suitable configuration in which the electrode 206 is in electrical communication with the solution 119 in the inner cavity 205 is possible. The electrode 206 may comprise a noble metal such as platinum. The plating solution 119 may be an electrolyte (e.g., an electrolyte comprising CuSO4) with or without additives such as accelerators and suppressors.
  • [0031]
    A solution outlet 207 of the hollow body 202 may be in fluid communication with a solution recycling unit (not shown) to remove excess or spent solution from the plating environment. The solution inlet 204 may be positioned upstream to a first opening 208 of the hollow body 202. The solution outlet 207 may be positioned downstream to the solution inlet 204 and proximate to the first opening 208 of the hollow body 202. With respect to the direction of flow of the plating solution 119, the electrode 206 is upstream of the first opening 208 of the hollow body 202. In certain embodiments, a recycling unit is in fluid communication with the second solution 120. As described above with respect to the first opening 112, the first opening 208 of the hollow body 202 and the top opening 112 of the via 102 may have substantially similar lateral geometries and/or lateral dimensions. As described above with respect to the electrode 118, the electrode 206 may be shaped as cylindrical, cubic, rectangular prism, or the like, and may include holes or apertures configured to flow the plating solution 119 therethrough.
  • [0032]
    A moving mechanism (FIGS. 3 and 4) of the plating device 200 may move the hollow body 202 proximate to the top opening 112 of the via 102 (e.g., over the top opening 112 as illustrated in FIG. 2) or proximate to (e.g., over) the top openings of multiple vias on the wafer to selectively fill the vias. During an example selective plating process, the first opening 208 of the hollow body 202 of the plating device 200 is positioned proximate to the top opening 112 of the via 102 in the manner exemplified in FIG. 2 to selectively deposit a conductive material (e.g., comprising copper) into the via 102.
  • [0033]
    As the plating solution 119 is delivered from the plating device 200 into the via 102 through the first opening 208 in the hollow body 202, a potential difference is applied between the electrode 206 and the conductive film 110, which is in electrical communication with a second terminal (more negative with respect to the first terminal) of the power supply 130 to deposit a conductive material (e.g., comprising copper) from the plating solution 119 into the via 102. An example current density is between about 50 mA/cm2 and 100 mA/cm2 operating in galvanostatic mode only, although other current densities and operating conditions are also possible. Electrical communication between the conductive film 110 and the power supply 130 may be made, for example, through stationary or moving electrical contacts. As the plating solution 119 is supplied into the via 102, a potential difference is formed between the electrode 206 and the conductive film 110 and an electric field is directed into the via 102 to fill the via 102. The directed electric field and the solution 119 flowing into the via 102, as described above, limit the deposition process to occur substantially only within the via 102, and advantageously fills the via 102 with a conductive material while little or no conductive material deposition occurs on the surrounding wafer surface 111.
  • [0034]
    In certain embodiments, a second solution 120 is flowed from a solution delivery outlet (FIG. 3) over the surface 111 of the conductive layer 110 during the deposition process. In certain such embodiments, the second solution 120 flows on the surface 111 and enters the via 102 through the gap between the top opening 112 of the via 102 and the first opening 208 of the hollow body 202; thus, the second solution 120 can mix with the plating solution 119 that is flowed into the via 102. To promote this action, an area adjacent the first opening 208 of the hollow body 202 may include a plurality of small apertures allowing solution flow. The second solution 120 may be a copper electrolyte with or without additives. Depending on the composition of the plating solution 119, the second solution 120 may be an electrolyte with or without additives such as accelerators or suppressors, or both. For example, if the plating solution 119 consists essentially of a copper electrolyte (e.g., CuSO4 electrolyte), the second solution 120 may be a copper electrolyte including additives. In certain such embodiments, the flow of the second solution 120 may supply additives to the plating solution 119 by mixing the solutions 119, 120 in the via 102. In embodiments in which the plating solution 119 is an electrolyte including copper and additives such as accelerators and suppressors, the second solution 120 may be an electrolyte consisting essentially of copper electrolyte.
  • [0035]
    FIG. 3 shows an example system 300 comprising a plating device 302 and a wafer carrier 303 holding a wafer W to be processed by the plating device 302. The wafer W has a plurality of 3-D vias 304 or deep features to be filled with a conductive material. The wafer W may be a semiconductor wafer or another substrate (e.g., ceramic, dielectric, etc.) having vias or deep features that may be formed similarly to the manner described above with respect to FIGS. 1 and 2 (e.g., coating with a dielectric layer and a conductive film). In the embodiment illustrated in FIG. 3, a hollow body 306 includes an electrode 310 and may be designed, for example, similarly to the embodiments described above with respect to FIGS. 1 and 2.
  • [0036]
    Referring again to FIG. 3, the hollow body 306 of the plating device 302 is mechanically coupled to a moving mechanism 308. In certain embodiments, the moving mechanism 308 comprises a computer controlled stage, such as a three-axis computer controlled stage that can position the hollow body 306 proximate to, and with any spacing from, any position on the wafer W. In certain such embodiments, the moving mechanism 308 is in communication with a computer system, which may include a central processing unit (CPU), memory, control software, data storage, monitoring devices, input devices, and the like. During processing, the moving mechanism 308 positions the plating device 302 over each of the vias 304 based on a map of the locations of the vias 304 on the wafer W as instructed by the control software. As described above, a plating solution 312 is injected into a via 304 when first opening 314 of the hollow body 306 of the plating device 302 is positioned proximate to (e.g., over) the via 304. The solution 312 flows out of the first opening 314 of the hollow body 306, and a potential difference is applied between the electrode 310 and a conductive surface 314 of the wafer W to form electrodeposits in the particular via 304. During processing, a second process solution 316 may be flowed over the surface 314 of the wafer W from a solution delivery outlet 318. As described above for the plating solution 119 and the second solution 120, the plating solution 312 and the second process solution 316 may be electroplating electrolytes with or without additives. The solution delivery outlet 318 may optionally be part of the system 300 or the plating device 302.
  • [0037]
    FIG. 4 shows an example system 400 comprising a plating device 402 and a wafer carrier 403 holding a wafer W to be processed by the plating device 402. The wafer W has a plurality of 3-D vias or deep features of various dimensions, each to be filled with a conductive material. For example the wafer W may include large vias 404 a, medium vias 404 b, and small vias 404 c. In the embodiment illustrated in FIG. 4, the vias 404 a, 404 b, 404 c are substantially circular (e.g., cylindrical, conical, frustoconical) and have varying diameters. The wafer W may be a semiconductor wafer or another substrate (e.g., ceramic, dielectric, etc.) and the vias or the features may be formed as in the manner described above with respect to FIGS. 1 and 2 (e.g., coating with a dielectric layer and a conductive film). In the embodiment illustrated in FIG. 4, the plating device 402 includes a plurality of hollow bodies, each comprising a first opening and a second opening. For example, the plating device 402 comprises a first hollow body 405 having a first opening 412 a and a second opening 414 a, a second hollow body 406 having a first opening 412 b and a second opening 414 b, and a third hollow body 407 having a first opening 412 c and a second opening 414 c.
  • [0038]
    In certain embodiments, the first opening of each hollow body is configured to have a lateral geometry and/or a largest lateral dimension that is substantially similar to a lateral geometry and/or a largest lateral dimension of a via. In some embodiments, an electrode is disposed in each hollow body (e.g., the electrode 420 a disposed in the hollow body 405, the electrode 420 b disposed in the hollow body 406, and the electrode 420 c disposed in the hollow body 407). In some embodiments, an electrode is disposed in the device 402 such that it can be in electrical communication with the solution 411 flowing through the selected hollow body. The plating device 402 may be used, for example, such that the first hollow body 405 is used to fill the large vias 404 a, the second hollow body 406 is used to fill the medium vias 404 b, and the third hollow body 407 is used to fill the small vias 404 c. With respect to the direction of flow of the solution 411, the electrodes 420 a, 420 b, 420 c are upstream of the first opening 412 a, 412 b, 412 c of the hollow bodies 405, 406, 407, respectively. The electrodes 420 a, 420 b, 420 c are connected to a power supply (exemplified in the above embodiments), or alternatively each electrode may be connected to different power supplies (not shown) to apply different electrical potentials to fill individual vias 404 a, 404 b, 404 c.
  • [0039]
    In certain embodiments, the hollow bodies 405, 406, 407 are mechanically coupled to a body 410 that is mechanically coupled to a moving mechanism 416 and hollow body selection mechanism (not shown). In the embodiment illustrated in FIG. 4, the body selection mechanism is configured to rotate the hollow bodies 405, 406, 407 about a pivotal axis (e.g., similar to a turret in a microscope), although other configurations are also possible. As the selected hollow body is positioned to perform an electroplating process, the second opening of the selected hollow body receives an electroplating solution 411 from an opening 412 of the body 410 of the plating device 402 while the second openings of the other hollow bodies are sealed (e.g., by liquid-tight seals) by the walls 413 of the body 410 to prevent the electroplating solution 411 from flowing into them and out of the first openings of those hollow bodies. For example, in FIG. 4, the second hollow body 406 is positioned for to electroplate a conductive material (e.g., comprising copper) into the via 404 b. Accordingly, the second opening 414 b of the second hollow body 406 is open to allow the plating solution 411 to flow through the opening 412, into the second hollow body 406, out of the first opening 412 b of the second hollow body 406, and into the via 404 b. The second openings 414 a and 414 c of the first and the third hollow bodies 405, 407, respectively, are sealed by the walls 413 such that the solution 411 does not flow into the first and third hollow bodies 405, 407 or out of the first openings 412 a, 412 c of the first and third hollow bodies 405, 407, respectively.
  • [0040]
    Similar to the moving mechanism 308 described above, the moving mechanism 416 may comprise a computer controlled stage, such as a three-axis computer controlled stage that can be moved proximate to, and with any spacing from, any position on the wafer W. In certain such embodiments, the moving mechanism 416 and the hollow body selection mechanism are in communication with a computer system, which may include a CPU, memory, control software, data storage, monitoring devices, input devices, and the like. During processing, the control software instructs the hollow body selection mechanism to select a hollow body that has a lateral geometry and/or a largest lateral dimension that is substantially similar to a lateral geometry and/or a largest lateral dimension of a via on the wafer W. The moving mechanism 416 then positions the selected hollow body proximate to (e.g., over) a particular via. The solution 411 flows out of the first opening of the selected hollow body, and a potential difference is applied between the electrode of the selected hollow body and a conductive surface of the wafer W to form electrodeposits in the particular via. During processing, a second process solution 418 may be flowed over the surface of the wafer W. As described above, the plating solution 411 and the second process solution 418 may be a plating solution with or without additives. A solution delivery outlet (FIG. 3) may optionally be part of the system 400 or the plating device 402.
  • [0041]
    FIG. 5 shows an alternative electroplating system 500 including a plating device 502 and a wafer carrier 504 holding a wafer W to be processed. In certain embodiments, the plating device 502 comprises a plating chamber 506 having an electrode assembly 507 (anode) disposed in a cavity 508 of the plating chamber 506. The specific designs of the plating chamber 506 and the assembly 507 allow a plurality of vias 509 on the wafer W to be electroprocessed at the same time, without being restricted by the size and the distribution of the vias 509. Therefore, as will be described more fully below, for every via 509 in the plurality of the vias on the wafer W to be processed, there is a corresponding electrode 510 included in the electrode assembly 507. Electrodes 510 may be attached to, or integral parts of, an electrode plate 512, which may be attached to a support plate 514 or a support layer. The electrodes 510 and the electrode plate 512 may be formed of a suitable electrode material (e.g., a noble metal such as platinum). The electrode plate 512 is connected to a power supply 530. The support plate 514 may comprise a conductive material such as tantalum (Ta), titanium (Ti), copper (Cu), or any other suitable metal. The electrodes 510 are isolated from one another by an insulation layer 516, which may comprise a dielectric material such as SiO2 or a polymer.
  • [0042]
    A bottom portion 518 of the chamber 506 includes a plurality of openings 520 to allow a plating solution 522 to flow into the vias 509. As described above for other embodiments, a largest lateral dimension of the openings 520 may be slightly smaller than, greater than, or substantially equal to a largest lateral dimension of the top openings of the vias 509, and the lateral geometry of the openings 520 may be substantially similar to the lateral geometry of the top openings of the vias 509. The plating solution may be delivered to the cavity 508 of the chamber 506 through solution inlets 524, and the excess or used plating solution may leave the cavity 508 of the chamber 506 through solution outlets 526.
  • [0043]
    In certain embodiments, a moving mechanism (FIGS. 3 and 4) positions the chamber 506 such that the openings 520 of the plating chamber and the vias 509 are substantially aligned before electrofilling them. During the process, a plating solution 522 flows out of the openings 520 and into the vias 509 and a potential difference is applied between the conductive surface of the wafer W and the electrodes 510 (e.g., via the electrode plate 512). Optionally, a second process solution 528 with or without additives may be flowed on the wafer W surface during the plating process, as described above. The same electrode assembly 507 and the bottom portion 518 can be used for a plurality of processes, as long as each processed portion of the wafer W has the substantially similar via-related characteristics (i.e., arrangement, lateral geometry, lateral dimensions, etc.). An arrangement generally refers to the relative positions of the multiple vias with respect to each other and/or the wafer. If a different wafer or a different portion of the wafer W has different via-related characteristics, a different electrode assembly and a different bottom portion for the plating chamber 506 that are substantially similar to the via-related characteristics of the different wafer or portion of the wafer W can be used.
  • [0044]
    FIGS. 6A-6D illustrate an example embodiment of a method of manufacturing an electrode assembly 600 using conventional photolithograph techniques. As shown in FIG. 6A, a dielectric layer 602 (e.g., comprising SiO2), is formed on a metal layer 604 (e.g., comprising aluminum). The dielectric layer 602 is patterned and electrode holes 606 are opened using conventional masking, definition, and etching operations. At this stage, a map of via characteristics of the wafer to be processed may be created or patterned on the dielectric layer 602. As shown in FIG. 6B, an electrode layer 608 (e.g., comprising platinum) is formed, filling the electrode holes 606 to form the electrodes 610 and extending over the dielectric layer 602. In certain embodiments, the electrode layer 608 includes electrodes 610 and electrode plate 612. In certain alternative embodiments, an electrode layer fills the electrode holes 606 to form the electrodes 610 and a second layer forms the electrode plate 612. As shown in FIG. 6C, a conductive layer 614 (e.g., comprising Ti, Ta, Cu) is formed over the electrode layer 608 (e.g., after planarizing the electrode layer 608). As shown in FIG. 6D, the metal layer 604 is removed to expose ends of the electrodes 610. The electrode assembly 600 may then be used in a plating device (e.g., the plating device 502 illustrated in FIG. 5).
  • [0045]
    FIG. 7A is a schematic illustration of a substrate 700 including a via 702 filled with a conductive material 704 (e.g., comprising copper) using a selective electroplating process, for example as described in the embodiments above. The interior surfaces of the via 702 and the surface 706 of the substrate is coated with a dielectric layer 708 and a conductive film 710 as described above. As shown in FIG. 7A, the selective electroplating process results in a conductive structure with few or no defects and little or no overburden conductive material 705 over the via 702 and on the surface 711 of the substrate 700. As mentioned above, reducing the amount of overburden conductive material can reduce planarization time, increase yield, and reduce costs, as well as reduce defect formation and stress that can result from thick overburden layers.
  • [0046]
    As shown in FIG. 7B, the surface portions of the dielectric and conductive layers 708, 710, respectively, as well the overburden conductive material 705, can be removed by a brief planarization step such as chemical mechanical polishing (CMP) or electrochemical mechanical polishing (ECMP) to form a 3-D conductive structure 712.
  • [0047]
    Although various preferred embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications of the exemplary embodiment are possible without materially departing from the novel teachings and advantages of this invention.

Claims (31)

  1. 1. A device for electrodepositing a conductive material from a first solution into at least one feature formed on a wafer, the device comprising:
    a hollow body including a first opening and a second opening, the first solution being supplied to the second opening and injected from the first opening;
    an electrode disposed within the hollow body, wherein a potential difference is applicable between the first electrode and the surface of the wafer to electrodeposit the conductive material into the at least one feature; and
    a moving mechanism mechanically coupled to the hollow body, the moving mechanism configured to position the first opening of the hollow body over the at least one feature.
  2. 2. The device of claim 1, further comprising a power supply in electrical communication with the electrode and the surface of the wafer.
  3. 3. The device of claim 1, wherein the moving mechanism comprises a stage movable in at least two dimensions.
  4. 4. The device of claim 1, further comprising a controller configured to control movement of the moving mechanism.
  5. 5. The device of claim 4, wherein the controller is configured to instruct the moving mechanism to position the first opening of the hollow body proximate to the at least one feature to deliver the first solution selectively into the at least one feature.
  6. 6. The device of claim 1, wherein the moving mechanism is configured to position the first opening of the hollow body proximate to the at least one feature to deliver the first solution selectively into the at least one feature.
  7. 7. The device of claim 6, wherein a lateral geometry of the first opening of the hollow body is substantially similar to a lateral geometry of a top opening of the at least one feature.
  8. 8. The device of claim 7, wherein a largest lateral dimension of the first opening of the hollow body is substantially equal to or smaller than a largest lateral dimension of the top opening of the at least one feature.
  9. 9. The device of claim 7, wherein a largest lateral dimension of the first opening of the hollow body is substantially equal to or greater than a largest lateral dimension of the top opening of the at least one feature.
  10. 10. The device of claim 1, further comprising another hollow body including a first opening and second opening, the another hollow body mechanically coupled to the moving mechanism.
  11. 11. The device of claim 10, wherein the another hollow body comprises another electrode, wherein a potential difference is applicable between the another electrode and the surface of the wafer to electrodeposit the conductive material into the at least one feature.
  12. 12. The device of claim 10, wherein the hollow body and the another hollow body are mechanically coupled to a hollow body selection mechanism.
  13. 13. The device of claim 1, further comprising a solution delivery outlet configured to deliver a second solution onto the wafer.
  14. 14. The device of claim 13, wherein the second solution comprises additives.
  15. 15. The device of claim 14, wherein the additives comprise at least one of suppressors and accelerators.
  16. 16. The device of claim 1, wherein the first solution is an electrolyte comprising copper.
  17. 17. The device of claim 1, further comprising an electrode assembly disposed within the hollow body, the electrode assembly comprising a plurality of electrodes, the plurality of electrodes including the electrode, the potential difference applicable between the plurality of electrodes and the surface of the wafer to electrodeposit the conductive material into a plurality of features, and wherein the hollow body comprises a plurality of openings, the plurality of openings including the first opening.
  18. 18. The device of claim 17, wherein the plurality of electrodes are formed by a process including masking.
  19. 19. The device of claim 17, wherein at least one of an arrangement, a lateral geometry, and a largest lateral dimension of the plurality of electrodes is substantially similar to an arrangement, a lateral geometry, and a largest lateral dimension of the plurality of openings.
  20. 20. The device of claim 17, wherein at least one of an arrangement, a lateral geometry, and a largest lateral dimension of the plurality of electrodes is substantially similar to an arrangement, a lateral geometry, and a largest lateral dimension of the plurality of features.
  21. 21. The device of claim 17, wherein at least one of an arrangement, a lateral geometry, and a largest lateral dimension of the plurality of openings is substantially similar to an arrangement, a lateral geometry, and a largest lateral dimension of the plurality of features.
  22. 22. A method of electrodepositing a conductive material into a 3-D via to form a conductive structure for 3-D integration, the method comprising:
    providing an electrodeposition device comprising:
    a first hollow body including a first opening and a second opening;
    a first electrode disposed within the first hollow body; and
    a moving mechanism mechanically coupled to the first hollow body;
    holding a wafer with a wafer carrier, a surface of the wafer including at least one via;
    operating the moving mechanism to position the first opening of the first hollow body proximate to a first via of the wafer surface;
    supplying a solution to the second opening of the first hollow body;
    flowing the solution out of the first opening of the first hollow body and into the first via; and
    applying a potential difference between the first electrode and the surface of the wafer.
  23. 23. A method of electrofilling a conductor into a deep feature formed on a surface of a wafer using an electrodeposition device having an opening, the method comprising:
    holding the wafer by a wafer carrier;
    positioning the opening of the device over the deep feature; and
    electrodepositing the conductor only into the deep feature without electrodepositing the conductor onto the surface of the wafer.
  24. 24. The method of claim 23, further comprising flowing a solution comprising the conductor from the opening into the deep feature prior to electrodepositing.
  25. 25. The method of claim 24, further comprising delivering another solution to the surface of the wafer while electrodepositing.
  26. 26. The method of claim 25, wherein the another solution comprises additives.
  27. 27. The method of claim 26, wherein the additives comprises accelerators and suppressors.
  28. 28. The device of claim 23, wherein positioning the opening comprises placing the opening over the deep feature so as to selectively electrodeposit the conductor into the feature.
  29. 29. The method of claim 23, wherein electrodepositing comprises applying a potential difference between surface of the wafer and an electrode of the electrodeposition device.
  30. 30. The method of claim 23, wherein positioning the opening comprises moving the device by a moving mechanism.
  31. 31. The method of claim 23, wherein the solution is an electrolyte comprising copper.
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