CN110129764A - 用于沉积膜的衬底处理系统 - Google Patents

用于沉积膜的衬底处理系统 Download PDF

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CN110129764A
CN110129764A CN201910128259.7A CN201910128259A CN110129764A CN 110129764 A CN110129764 A CN 110129764A CN 201910128259 A CN201910128259 A CN 201910128259A CN 110129764 A CN110129764 A CN 110129764A
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inhibitor
plasma
substrate
feature
process chamber
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CN110129764B (zh
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唐伟
巴特·范·斯查文迪克
钱俊
康胡
阿德里安·拉瓦伊
迪纳什·帕迪
大卫·C·史密斯
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Lam Research Corp
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Abstract

本发明涉及用于无缝特征填充的抑制剂等离子体介导的原子层沉积。用于在衬底处理系统中沉积膜的系统和方法包括在处理室中执行第一原子层沉积(ALD)周期以在包括特征的衬底上沉积膜；在第一ALD周期之后，在处理室中将衬底暴露于抑制剂等离子体达到预定时间段以在特征中生成变化的钝化表面；以及在所述预定时间段之后，在处理室中执行第二ALD周期以在衬底上沉积膜。

Description

用于沉积膜的衬底处理系统
本申请是申请号为201510088812.0、申请日为2015年2月26日、发明名称为“用于无缝特征填充的抑制剂等离子体介导的原子层沉积”的申请的分案申请。
相关申请交叉参考
本申请要求于2014年2月26日提交的美国临时申请第61/944,871号的权益。上述所参考申请的全部公开内容通过参考并入此处。
技术领域
本公开涉及衬底处理系统，且更具体地涉及用于无缝特征填充的衬底处理系统和方法。
背景技术
这里提供的背景描述是为了总体上描述本公开的背景的目的。在该背景技术部分中所描述的当前列明的发明人的工作以及说明书中的在提交时不能作为现有技术的方面既不明示也不暗示地承认其作为针对本公开的现有技术。
浅沟槽隔离(STI)提供集成电路(IC)中个体晶体管器件之间的电气隔离。STI包括填充有高品质的硅(Si)氧化物膜的沟槽。在一些应用中，沟槽的深宽比(AR)可高达8:1且沟槽的开口可缩小至约20nm。实现无空隙STI填充是重要的，因为膜在后续集成步骤中可能会经受进一步的处理，这可暴露该空隙。在一些实例中，该空隙可能无意中接着被导电材料填充，这可导致芯片上不同导体之间的短路。
在一些应用中，利用高密度等离子体化学气相沉积(HDPCVD)以膜填充STI。但是，对于AR高于4:1的沟槽，HDPCVD氧化物填充STI却无空隙是非常具有挑战性的，即使利用沉积-蚀刻-沉积循环工艺。
现在参考图1A-1D，利用HDPCVD的间隙填充实例被示出。在图1A中，衬底100包括具有侧壁104和底部106的沟槽102。在图1B中，氧化层112(比如SiO2)被沉积。氧化层112通常不具有均匀的厚度。在沟槽开口中通常有尖头114。氧化层112通常在侧壁104的下部120处薄于其它位置(比如沟槽底部122和场区)。在图1C和1D的附加HDPCVD步骤之后，尖头114在沟槽开口处相遇而空隙130产生。空隙130在后续处理过程中引发问题。
虽然新兴的可流动氧化物方法提供了液状物填充表现，但对流动性的要求限制了可达到的膜密度。尽管付出额外成本可使用后沉积致密化方法，但这些方法还未被证明是成功的。由于周围侧壁的约束(这阻止了使可流动氧化物膜完全致密化所需的收缩)，所述替代方法不能使高深宽比结构中的膜致密化。
ALD氧化物可被用于以高品质的Si氧化物膜间隙填充深沟槽。但是，在沉积在侧壁上的膜合并之后，在沟槽的中央通常留下接缝。现在参考图2A-2D，利用ALD的间隙填充实例被示出。在图2A中，衬底200包括具有侧壁204和底部206的沟槽202。在图2B中，氧化层212(比如SiO2)在第一ALD周期中被沉积。由图可见，氧化层212在侧壁上在220处以及在沟槽底部222处是共形的。但是，在图2C和2D的附加ALD周期之后，接缝230产生。接缝230在后续湿法化学处理过程中往往具有高蚀刻速率。
发明内容
本部分提供本公开的总体概要，并非其完整范围或其全部特征的全面披露。
一种用于在衬底处理系统中沉积膜的方法包括在处理室中执行第一原子层沉积(ALD)周期以在包括特征的衬底上沉积膜；在所述第一ALD周期之后，在所述处理室中将所述衬底暴露于抑制剂等离子体达到预定时间段以在特征中生成变化的钝化表面；以及在所述预定时间段之后，在所述处理室中执行第二ALD周期以在所述衬底上沉积膜。
在其它特征中，在执行所述第一ALD周期之前，该方法包括在所述处理室中将所述衬底暴露于所述抑制剂等离子体。所述第一ALD周期和所述第二ALD周期包括在第一预定时间段中将所述衬底暴露于第一反应物；在所述第一预定时间段之后从所述处理室排出反应物；在第二预定时间段中将所述衬底暴露于不同于所述第一反应物的第二反应物；以及在所述第二预定时间段之后从所述处理室排出反应物。
在其它特征中，所述膜包括二氧化硅。将所述衬底暴露于所述抑制剂等离子体包括供应抑制剂气体；激发所述抑制剂等离子体；将所述抑制剂等离子体保持所述预定时间段；以及在所述预定时间段之后，熄灭所述抑制剂等离子体。
在其它特征中，所述抑制剂等离子体随着所述特征的深度减小以渐增方式抑制所述特征中的后续的膜沉积。所述抑制剂等离子体使用分子氮作为抑制剂气体而生成。
在其它特征中，所述特征中的所述变化的钝化表面改善所述特征的自下而上的填充以防止所述特征中的接缝。该方法进一步包括在所述第二ALD周期之后将所述衬底暴露于所述抑制剂等离子体并执行附加ALD周期以自下而上填充所述特征却没有接缝。所述抑制剂等离子体使用选自由分子氮、氩、氦、分子氢、氨或其组合物组成的群组的气体生成。所述特征具有大于4:1的深宽比和小于或等于30纳米的开口。
在其它特征中，所述抑制剂等离子体利用第一等离子体源来产生且所述第一ALD周期利用所述第一等离子体源来执行。所述抑制剂等离子体利用第一等离子体源来产生且所述第一ALD周期利用不同于所述第一等离子体源的第二等离子体源来执行。所述抑制剂等离子体利用第一等离子体源来产生且所述第一ALD周期和所述第二ALD周期在不使用等离子体的情况下执行。
在其它特征中，该方法包括在所述第一ALD周期之前执行一或多个ALD周期，其间不使用抑制剂等离子体。该方法包括使用不同于所述第一ALD周期和所述第二ALD周期的工艺来在执行所述第一ALD周期和所述第二ALD周期之后以材料填充所述特征的至少一部分。所述第一ALD周期和所述第二ALD周期沉积介电膜。所述材料包括不同于所述介电膜的其它介电膜。所述材料包括金属。所述特征包括沟槽。所述特征包括孔。
一种用于沉积膜的衬底处理系统包括处理室，所述处理室包括被配置为支撑包括特征的衬底的基架。气体供应源被配置为选择性地供应原子层沉积(ALD)工艺气体给所述处理室以及选择性地供应抑制剂气体给所述处理室。等离子体发生器被配置为在所述处理室中选择性地产生抑制剂等离子体。控制器被配置为控制所述气体供应源和所述等离子体发生器。所述控制器被进一步配置为在所述处理室中执行第一ALD周期以在所述衬底上沉积膜；在所述第一ALD周期之后，在所述处理室中将所述衬底暴露于利用所述抑制剂气体产生的所述抑制剂等离子体达到预定时间段以在所述特征中生成变化的钝化表面；以及在所述预定时间段之后，在所述处理室中执行第二ALD周期以在所述衬底上沉积膜。
在其它特征中，所述控制器被配置为在执行所述第一ALD周期之前将所述衬底暴露于所述抑制剂等离子体。在所述第一ALD周期和所述第二ALD周期中，所述控制器被配置为将所述衬底暴露于第一反应物达到第一预定时间段；在所述第一预定时间段之后从所述处理室排出反应物；将所述衬底暴露于不同于所述第一反应物的第二反应物达到第二预定时间段；以及在所述第二预定时间段之后从所述处理室排出反应物。
在其它特征中，所述膜包括二氧化硅。当将所述衬底暴露于所述抑制剂等离子体时，所述控制器被配置为供应抑制剂气体；激发所述抑制剂等离子体；将所述抑制剂等离子体保持所述预定时间段；以及在所述预定时间段之后，熄灭所述抑制剂等离子体。
在其它特征中，所述抑制剂等离子体随着所述特征的深度减小以渐增方式抑制所述特征中的后续的膜沉积。所述抑制剂等离子体使用分子氮作为所述抑制气体而生成。所述特征中的所述变化的钝化表面改善所述特征的自下而上的填充以防止所述特征中的接缝。所述控制器被进一步配置为在所述第二ALD周期之后将所述衬底暴露于所述抑制剂等离子体并执行附加ALD周期以自下而上填充所述特征却没有接缝。
在其它特征中，所述抑制剂气体选自由分子氢、氨或其组合物组成的群组。所述特征具有大于4:1的深宽比和小于或等于30纳米的开口。
具体而言，本发明的一些方面可以阐述如下：
1.一种用于沉积膜的衬底处理系统，包括：
处理室，所述处理室包括基架，所述基架被配置为支撑包括特征的衬底；
气体源，所述气体源被配置为选择性地将原子层沉积工艺气体供应到所述处理室并选择性地将抑制剂气体供应到所述处理室；
等离子体发生器，所述等离子体发生器被配置为在所述处理室中选择性地产生抑制剂等离子体；和
控制器，所述控制器被配置为控制所述气体源和所述等离子体发生器的输出，其中，所述控制器还被配置为：
在所述处理室中执行第一原子层沉积周期，以在所述衬底上沉积膜；
在所述第一原子层沉积周期之后，在所述处理室中将所述衬底暴露于利用所述抑制剂气体产生的所述抑制剂等离子体以在所述特征中生成变化的钝化表面；和
在所述特征中生成所述变化的钝化表面之后，在所述处理室中执行第二原子层沉积周期以在所述衬底上沉积膜。
2.根据条款1所述的衬底处理系统，其中，所述控制器被配置为在执行所述第一原子层沉积周期之前将所述衬底暴露于所述抑制剂等离子体。
3.根据条款1所述的衬底处理系统，其中，在所述第一原子层沉积周期和所述第二原子层沉积周期中，所述控制器被配置为：
将所述衬底暴露于第一反应物；
在将所述衬底暴露于所述第一反应物之后，从所述处理室排出反应物；
将所述衬底暴露于不同于所述第一反应物的第二反应物；以及在将所述衬底暴露于所述第二反应物之后，从所述处理室排出反应物。
4.根据条款1所述的衬底处理系统，其中，所述膜包括二氧化硅。
5.根据条款1所述的衬底处理系统，其中，当将所述衬底暴露于所述抑制剂等离子体时，所述控制器被配置成：
供应抑制剂气体；
在执行所述第一原子层沉积周期之前，激发所述抑制剂等离子体；在执行所述第二原子层沉积周期的同时，将所述抑制剂等离子体保持在所述处理室中；以及
在所述第二原子层沉积周期期间将所述膜沉积在所述衬底上之后，熄灭所述抑制剂等离子体。
6.根据条款1所述的衬底处理系统，其中，所述抑制剂等离子体随着所述特征的深度减小以渐增方式抑制所述特征中的后续的膜沉积。
7.根据条款1所述的衬底处理系统，其中，所述抑制剂等离子体使用分子氮作为抑制剂气体而生成。
8.根据条款1所述的衬底处理系统，其中，所述控制器还被配置成在所述第二原子层沉积周期之后将所述衬底暴露于所述抑制剂等离子体并执行附加原子层沉积周期以自下而上填充所述特征却没有接缝。
9.根据条款1所述的衬底处理系统，其中，所述抑制剂气体选自由分子氢、氦、氩、氨或其组合物组成的组。
10.根据条款1所述的衬底处理系统，其中，所述特征具有大于4:1的深宽比和小于或等于30纳米的开口。
11.根据条款1所述的衬底处理系统，其中，所述抑制剂等离子体利用第一等离子体源来产生且所述第一原子层沉积周期利用所述第一等离子体源来执行。
12.根据条款1所述的衬底处理系统，其中，所述抑制剂等离子体利用第一等离子体源来产生且所述第一原子层沉积周期利用不同于所述第一等离子体源的第二等离子体源来执行。
13.根据条款1所述的衬底处理系统，其中，所述抑制剂等离子体利用第一等离子体源来产生且所述第一原子层沉积周期和所述第二原子层沉积周期在不使用等离子体的情况下执行。
14.根据条款1所述的衬底处理系统，还包括在所述第一原子层沉积周期之前执行一个或多个原子层沉积周期，而不在其间使用抑制剂等离子体。
15.根据条款1所述的衬底处理系统，还包括使用不同于所述第一原子层沉积周期和所述第二原子层沉积周期的工艺来在执行所述第一原子层沉积周期和所述第二原子层沉积周期之后以材料填充所述特征的至少一部分。
16.根据条款15所述的衬底处理系统，其中：
所述第一原子层沉积周期和所述第二原子层沉积周期沉积介电膜；且
所述材料包括不同于所述介电膜的其他介电膜。
17.根据条款15所述的衬底处理系统，其中，所述材料包括金属。
18.根据条款1所述的衬底处理系统，其中，所述特征包括沟槽。
19.根据条款1所述的衬底处理系统，其中，所述特征包括孔。
通过此处所提供的描述，进一步的应用领域会变得显而易见。本概要中的描述和具体实施例仅仅旨在说明的目的而非旨在限制本公开的范围。
附图说明
图1A-1D示出了根据现有技术使用HDPCVD的沟槽间隙填充的一实施例；
图2A-2D示出了根据现有技术使用ALD的沟槽间隙填充的一实施例；
图3是根据本公开的用于沟槽间隙填充的衬底处理系统的一实施例的功能框图。
图4示出了利用抑制剂等离子体对衬底进行的定向轰击；
图5A-5D示出了根据本公开使用ALD和抑制剂等离子体的沟槽间隙填充的一实施例；以及
图6和7示出了使用ALD和抑制剂等离子体进行沟槽间隙填充的方法的实施例。
在附图中，参考标号可重复使用以标识相似和/或相同的元件。
具体实施方式
本公开描述了用于填充衬底上的特征的系统和方法。在一些实施例中，所述特征形成于衬底的场区下面。在一些实施例中，使用原子层沉积(ALD)工艺消除在间隙填充期间形成在孔或沟槽(例如浅沟槽绝缘体(STI))中的接缝。尽管STI应用已被公开，但本发明适用于需要特征填充的其它应用，例如但不限于，预金属电介质、3D NAND、深沟槽等。本文所述的系统和方法在ALD工艺期间，通过在于特征填充过程中执行的至少一些ALD周期之间将衬底暴露于抑制剂等离子体，增强自下而上的特征填充。
在一些实施例中，特征基本上通过ALD周期填充。在其他实施例中，特征不是完全通过ALD周期填充，并且其它材料被用于填充特征。其它材料的实施例包括具有不同成分的金属或电介质。
抑制剂等离子体创建钝化表面，并增加所沉积的ALD膜的成核屏障。当抑制剂等离子体与特征中的材料相互作用时，由于几何遮蔽效应，因此，相比位置更接近特征或场的顶部的材料，在特征底部的材料接受少得多的等离子体处理。其结果是，在特征顶部的沉积被选择性地抑制，而在特征底部的沉积在进行中受到较少的抑制或没有受到抑制。其结果是，自下而上的填充被增强，从而创建了减轻接缝效果的较有利的倾斜轮廓。
在一些实施例中，分子氮(N2)可以用作抑制剂等离子体的源气体，尤其是当沉积膜为SiO2时。如可以理解的，ALD的SiO2在氮化物表面上以较慢的速率成核。在其它实施例中，所述抑制剂等离子体源气体选自由N2、氩(Ar)、氦(He)、分子氢(H2)、氨(NH3)，或它们的组合物组成的群组。
本文所描述的系统和方法使得ALD的Si氧化物处理可以在STI或其它应用中使用。由于共形沉积的性质，因此相比HDPCVD氧化物，利用N2抑制剂等离子体的ALD氧化物处理能够填充难处理得多的结构，例如具有更高的AR或更窄的特征尺寸的那些结构。在一些实施例中，AR大于或等于4:1、6:1或8:1。在一些实施例中，特征开口小于或等于30纳米、25纳米或20纳米。就湿法蚀刻耐性和破损行为而言，相比可流动氧化物处理，利用抑制剂等离子体的ALD氧化物处理提供了改善的膜质量。
现在参考图3，示出用于执行ALD沉积的系统300的一实施例。该系统300包括处理室324，处理室324包围系统300的其他部件，并包含RF等离子体。RF等离子体可通过电容式等离子体发生器产生。例如，喷头314可连接到RF导线，而加热器块320可以接地，反之亦然。替代地，也可以使用其它类型的等离子体发生器，如感应式等离子体发生器，或远程等离子体发生器，如等离子体管。在这个实施例中，高频RF发生器302和低频RF发生器304被连接到匹配网络306并被连接到喷头314。通过匹配网络306供给的功率和频率足以从工艺气体产生RF等离子体。
基架318支撑衬底316。基架318一般包括卡盘、叉、或升降销以在沉积和/或等离子体处理反应期间以及在沉积和/或等离子体处理反应之间保持并传送衬底。卡盘可以是静电卡盘、机械卡盘或其它类型的卡盘。工艺气体经由入口312引入。多个源气体管线310连接到歧管308。气体可以预先混合或可以不预先混合。适当的阀和质量流量控制机构被用来确保在工艺的沉积和等离子体处理阶段期间输送适当的气体。
工艺气体经由出口322排出室324。真空泵326将工艺气体抽出并通过诸如节流阀或摆阀之类的流量限制装置保持系统内的合适的低压。控制器340可以被提供来监控工艺参数并对气体混合物、等离子体、基架加热、卡盘和/或从处理室去除反应物进行控制。
在一些实施例中，ALD周期可包括等离子体增强ALD(PEALD)。如果使用PEALD，用于ALD周期和抑制等离子体的等离子体源可以是相同的等离子体源。在其它实施例中，可使用不同的等离子体源。对于抑制剂等离子体，具有一定的方向性会是理想的，而对于沉积源，具有很少或没有方向性会是理想的。换言之，可以有2种等离子体源，或1种共用的等离子体源，或仅用于抑制剂等离子体的1种等离子体源。
现在参考图4，在启动ALD之前和/或在至少两个连续的ALD周期之间，根据本公开的系统和方法使衬底400暴露于抑制剂等离子体。抑制剂等离子体增强自下而上的间隙填充并改善高湿法蚀刻率耐性。抑制剂等离子体创建钝化表面，并增加所沉积的ALD膜的成核屏障。当抑制剂等离子体与特征402中的材料相互作用时，由于几何遮蔽效应，因此，相比位置更接近特征或场的顶部的材料，在特征402的底部406的材料接受少得多的等离子体处理。其结果是，在特征顶部的沉积被选择性地抑制，而在特征底部的沉积在进行中受到较少的抑制(例如，沿着侧壁404)或没有受到抑制(例如，在底部406)。其结果是，自下而上的填充被增强，从而创建了减轻接缝效果的较有利的倾斜轮廓。
如可从图4看出的，由抑制剂等离子体生成的钝化表面在场和上部特征区域中被增强，并随着进入特征的距离增加而减弱。如可以理解的，在每个后续的ALD周期之后，类似的图案在所沉积的层上通过抑制剂等离子体创建。以这种方式，在特征顶部的沉积被选择性地抑制，而在特征其它部分的沉积在进行中受到较少的抑制或没有受到抑制。其结果是，自下而上的填充被增强，从而创建了减轻接缝效果的较有利的倾斜轮廓。
现在参考图5A-5D，示出了根据本公开的通过使用ALD、利用抑制剂等离子体进行间隙填充的一实施例。在图5A中，衬底500包括具有侧壁504和底部506的特征502。衬底500可在第一ALD周期前用抑制剂等离子体进行处理。图5B示出了氧化物层512，如通过第一ALD周期沉积的SiO2。更多的膜沉积在特征底部522和侧壁504的下部520。氧化物层512在诸如场之类的区域中具有减小的厚度，并且具有随着特征502的深度增加而增大的厚度。在图5C和5D所示出的附加ALD周期之后，衬底500的间隙填充在无接缝的情况下完成。
现在参考图6，示出了使用抑制剂处理的ALD方法600的一实施例。在608，在第一ALD周期之前，将衬底任选地暴露于抑制剂等离子体，或者在不含抑制剂等离子体的情况下，执行一个或多个ALD周期。在610，执行ALD周期。在一些实施例中，每个ALD周期可包括暴露于第一反应物持续第一预定时间段并在第一预定时间段之后通过吹扫或抽排去除反应物、暴露于第二反应物持续第二预定时间段并在第二预定时间段之后通过吹扫或抽排去除反应物。如果前述ALD周期在614完成，那么，接着在618将衬底暴露于抑制剂等离子体。在622，任选地通过吹扫或抽排从处理室去除反应物。在626，如果有剩余的至少两个ALD周期，则在610重复该过程。否则，该过程继续进行到630，并完成最后的ALD周期。在632，可任选执行无抑制剂等离子体的附加ALD周期以完全或部分地填充特征和/或可用不同的材料填充特征的至少一部分。
现在参考图7，示出了用于供应抑制剂等离子体的方法650的一实施例。在654中，抑制剂气体被供应到处理室中。在658，在室内激发等离子体。在660，当定时器已到时，在664，控制熄灭等离子体。正如可以理解的，等离子体可以以不同的方式产生。如果使用PEALD，则类似的方法用于激发等离子体，但在654，是供给等离子体工艺气体，而不是抑制剂气体。
前面的描述在本质上仅仅是说明性的并且绝不旨在限制本公开、其应用或用途。本公开的广泛教导可以以多种形式来实现。因此，虽然本公开包括特定实施例，但本公开的真实范围不应受限于此，因为在研究附图、说明书和随附权利要求书后，其它的修改方案将变得显而易见。如本文所用，短语“A、B和C中的至少一个”应该被理解为是指使用非排他性逻辑“或”(OR)的逻辑(A或B或C)。应当理解的是，方法中的一个或多个步骤可以以不同的顺序(或同时)执行，而不改变本公开的原理。
在本申请中，包括下面的定义，术语控制器可以被替换为术语电路。术语控制器可以指以下器件、以下器件的一部分、或包括以下器件：专用集成电路(ASIC)；数字、模拟或混合模拟/数字分立电路；数字、模拟或混合模拟/数字集成电路；组合逻辑电路；现场可编程门阵列(FPGA)；执行代码的处理器(共享的、专用的或群组的)；存储由处理器执行的代码的存储器(共享的、专用的或群组的)；提供所描述的功能的其它合适的硬件组件；或上述器件的部分或全部的组合，如在片上系统(system-on-chip)。
如上述使用的术语代码可以包括软件、固件和/或微代码，并且可以指程序、例程、函数、类和/或对象。术语共享处理器包括执行来自多个控制器的部分或全部代码的单个处理器。术语群组处理器包括与另外的处理器组合来执行来自一个或多个控制器的一些或全部代码的处理器。术语共享存储器包括存储来自多个控制器的部分或全部代码的单个存储器。术语群组存储器包括与另外的存储器组合来存储来自一个或多个控制器的一些或全部代码的存储器。术语存储器可以是术语计算机可读介质的子集。如本文所使用的术语计算机可读介质不包括通过介质(例如在载波上)传播的暂时性的电信号或电磁信号；因此术语计算机可读介质可以被认为是有形的和非暂时性的。非暂时性的有形计算机可读介质的非限制性实施例包括非易失性存储器(如闪存)、易失性存储器(例如静态随机存取存储器和动态随机存取存储器)、磁存储器(例如磁带或硬盘驱动器)和光学存储器。
本申请中描述的装置和方法可以部分或完全通过由一个或多个处理器执行的一个或多个计算机程序来实现。这些计算机程序包括存储在至少一个非暂时性的有形计算机可读介质上的处理器可执行指令。这些计算机程序也可以包括和/或依赖于所存储的数据。

Claims (10)

1.一种用于沉积膜的衬底处理系统，包括：
处理室，所述处理室包括基架，所述基架被配置为支撑包括特征的衬底；
气体源，所述气体源被配置为选择性地将原子层沉积工艺气体供应到所述处理室并选择性地将抑制剂气体供应到所述处理室；
等离子体发生器，所述等离子体发生器被配置为在所述处理室中选择性地产生抑制剂等离子体；和
控制器，所述控制器被配置为控制所述气体源和所述等离子体发生器的输出，其中，所述控制器还被配置为：
在所述处理室中执行第一原子层沉积周期，以在所述衬底上沉积膜；
在所述第一原子层沉积周期之后，在所述处理室中将所述衬底暴露于利用所述抑制剂气体产生的所述抑制剂等离子体以在所述特征中生成变化的钝化表面；和
在所述特征中生成所述变化的钝化表面之后，在所述处理室中执行第二原子层沉积周期以在所述衬底上沉积膜。
2.根据权利要求1所述的衬底处理系统，其中，所述控制器被配置为在执行所述第一原子层沉积周期之前将所述衬底暴露于所述抑制剂等离子体。
3.根据权利要求1所述的衬底处理系统，其中，在所述第一原子层沉积周期和所述第二原子层沉积周期中，所述控制器被配置为：
将所述衬底暴露于第一反应物；
在将所述衬底暴露于所述第一反应物之后，从所述处理室排出反应物；
将所述衬底暴露于不同于所述第一反应物的第二反应物；以及
在将所述衬底暴露于所述第二反应物之后，从所述处理室排出反应物。
4.根据权利要求1所述的衬底处理系统，其中，所述膜包括二氧化硅。
5.根据权利要求1所述的衬底处理系统，其中，当将所述衬底暴露于所述抑制剂等离子体时，所述控制器被配置成：
供应抑制剂气体；
在执行所述第一原子层沉积周期之前，激发所述抑制剂等离子体；
在执行所述第二原子层沉积周期的同时，将所述抑制剂等离子体保持在所述处理室中；以及
在所述第二原子层沉积周期期间将所述膜沉积在所述衬底上之后，熄灭所述抑制剂等离子体。
6.根据权利要求1所述的衬底处理系统，其中，所述抑制剂等离子体随着所述特征的深度减小以渐增方式抑制所述特征中的后续的膜沉积。
7.根据权利要求1所述的衬底处理系统，其中，所述抑制剂等离子体使用分子氮作为抑制剂气体而生成。
8.根据权利要求1所述的衬底处理系统，其中，所述控制器还被配置成在所述第二原子层沉积周期之后将所述衬底暴露于所述抑制剂等离子体并执行附加原子层沉积周期以自下而上填充所述特征却没有接缝。
9.根据权利要求1所述的衬底处理系统，其中，所述抑制剂气体选自由分子氢、氦、氩、氨或其组合物组成的组。
10.根据权利要求1所述的衬底处理系统，其中，所述特征具有大于4:1的深宽比和小于或等于30纳米的开口。
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