CN108807365A - 静电放电电路 - Google Patents
静电放电电路 Download PDFInfo
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Abstract
一种静电放电电路,连接至一垫。该静电放电电路包括:一分压器、一RC电路以及一路径控制电路。分压器连接于该垫与一第一节点之间,可提供多个分压。RC电路,连接于该垫与该第一节点之间。RC电路接收这些分压,并提供一控制电压。路径控制电路,连接于该垫与该第一节点之间。路径控制电路接收这些分压与该控制电压。当该垫接收一正静电放电冲击时,该RC电路控制该路径控制电路,使得一第一静电放电路径开启,并将一静电放电电流由该垫经由该第一静电放电路径传递至该第一节点。
Description
技术领域
本发明涉及一种电路,且特别涉及一种静电放电(electro static discharge,简称ESD)电路。
背景技术
众所周知,在互补式金属氧化物半导体的集成电路(CMOS IC)工艺中,为增加其速度与整合度,半导体元件尺寸会越做越小、栅极氧化层(Gate oxide layer)会越来越薄。因此,栅极氧化层的崩溃电压(breakdown voltage)降低,且半导体元件的PN接面(PNjunction)的崩溃电压也降低。
为了避免集成电路(IC)在生产过程中被静电放电冲击(ESD zapping)所损伤,在集成电路(IC)内皆会制作静电放电电路。静电放电电路提供了静电放电电流路径(ESDcurrent path),以免静电放电流(ESD current)流入IC内部电路而造成损伤。
发明内容
本发明涉及一种静电放电电路,连接至一垫,该静电放电电路包括:一分压器,连接于该垫与一第一节点之间,该分压器提供多个分压;一RC电路,连接于该垫与该第一节点之间,该RC电路接收这些分压,并提供一控制电压;以及一路径控制电路,连接于该垫与该第一节点之间,该路径控制电路接收这些分压与该控制电压;其中,当该垫接收一正静电放电冲击时,该RC电路控制该路径控制电路,使得一第一静电放电路径开启,并将一静电放电电流由该垫经由该第一静电放电路径传递至该第一节点。
为了对本发明的上述及其他方面有更佳的了解,下文特举实施例,并配合附图详细说明如下:
附图说明
图1所绘示为本发明静电放电电路的第一实施例。
图2A为第一实施例静电放电电路的电压-电流曲线示意图。
图2B为本发明第一实施例静电放电电路进行人体模式测试的示意图。
图3为本发明静电放电电路的第二实施例。
图4A为第二实施例静电放电电路接收到负静电放电冲击的示意图。
图4B为第二实施例静电放电电路接收到正静电放电冲击的示意图。
图5A为第二实施例静电放电电路的电压-电流曲线示意图。
图5B为本发明第二实施例静电放电电路进行人体模式测试的示意图。
图6为本发明静电放电电路的第三实施例。
图7A为本发明静电放电电路的第四实施例。
图7B为本发明第四实施例的静电放电电路进行人体模式测试时节点d的电压曲线示意图。
图8为本发明静电放电电路的第五实施例。
【符号说明】
100、200、300、400、500:静电放电电路
140、240:内部电路
150、250:垫
210、310:分压器
220、320:RC电路
230:路径控制电路
446、510:反相电路
具体实施方式
在非易失性存储器的编程动作或者抹除动作时,编程电压(program voltage)或者抹除电压(erase voltage)会供应至非易失性存储器中用以编程记忆胞或者抹除记忆胞。
通常,编程电压或者抹除电压会非常接近半导体元件的耐压,但并不会损毁半导体元件。举例来说,非易失性存储器内部电路的半导体元件为MOS晶体管,其操作电压为1.8V,而编程电压为6V。虽然MOS晶体管可以承受6V的电压应力(voltage stress),但如果MOS晶体管承受的电压应力再增大一些(例如7V以上)时,则MOS晶体管就会有损毁的危险。
因此,在非易失性存储器中必须设计静电放电电路,且静电放电电路的开启临限电压(turn on threshold voltage)需要稍微大于6V,且越接近6V越好。当非易失性存储器接收到静电放电冲击(ESD zapping)时,即可快速地将静电放电电流排除,以保护非易失性存储器的内部电路。
请参照图1,其所绘示为本发明静电放电电路的第一实施例。静电放电电路100与内部电路140连接于接收第一供应电压Vpp的垫(pad)150与接收第二供应电压GND的节点g之间。第一供应电压Vpp由垫150输入静电放电电路100与内部电路140。第二供应电压GND由节点g输入静电放电电路100与内部电路140。
静电放电电路100中包括一第一静电放电电流路径(first ESD current path)102与一第二静电放电电流路径(second ESD current path)104。其中,第一静电放电电流路径102包括n个二极管Df1~Dfn串接于第一供应电压Vpp与第二供应电压GND之间。第二静电放电电流路径104包括m个二极管Dr1~Drm串接于第一供应电压Vpp与第二供应电压GND之间。第二供应电压GND可为0V。
基本上,第一静电放电电流路径102的开启临限电压(turn-on thresholdvoltage)为n×Von,其中Von为二极管的切入电压(cut in voltage),例如0.7V。因此,当第一供应电压Vpp与第二供应电压GND之间的电压差(Vpp-0V)大于n×Von时,第一静电放电电流路径102开启。
由以上的说明可知,第一静电放电电流路径102的开启临限电压(n×Von)必需设定成大于第一供应电压Vpp(例如6V)。如果将第一静电放电电流路径102的开启临限电压(n×Von)设定成小于第一供应电压Vpp(例如6V),则会造成第一静电放电电流路径102的误触发(mis-trigger)。同样地,第一静电放电电流路径102的开启临限电压(n×Von)必需设定成小于第二静电放电电流路径104的总崩溃电压(m×Vbj),其中Vbj为单一二极管的崩溃电压(breakdown voltage)。如果将第一静电放电电流路径102的开启临限电压(n×Von)设定成大于第二静电放电电流路径104的总崩溃电压(m×Vbj),则会造成第二静电放电电流路径104的误触发(mis-trigger),并发生二极管崩溃(diode breakdon)。举例来说,当垫150接收正的静电电压时,第一静电放电电流路径102会立即开启,以避免造成第二静电放电电流路径104上的二极管崩溃。
同理,第二静电放电电流路径104开启临限电压为m×Von。换句话说,当第二供应电压GND与第一供应电压Vpp之间的电压差(0V-Vpp)大于m×Von时,第二静电放电电流路径104开启。
举例来说,假设二极管的切入电压Von为0.7V,崩溃电压Vbj为4V,且内部电路140的电压操作范围为0V至6V之间。因此,静电放电电路100中,第一静电放电电流路径102至少要串接9颗(9×0.7V=6.3V)二极管,第二静电放电电流路径104至少要串接2颗(2×4V=8V)二极管。如此,才不会误触发第一静电放电电流路径102或者第二静电放电电流路径104。
为了防止工艺变异(process variation)而造成二极管切入电压Von的变化,可以在第一静电放电电流路径102再增加一颗二极管。如此可以确认第一静电放电电流路径102不会在正常运作时误触发。
因此,当垫150接收到正静电放电冲击(positive ESD zapping)时,第一静电放电电流路径102开启,且静电放电电流由垫150经由第一静电放电电流路径102流至节点g。反之,当垫150接收到负静电放电冲击(negative ESD zapping)时,第二静电放电电流路径104开启,且静电放电电流由节点g经由第二静电放电电流路径104流至垫150。
请参照图2A,其所绘示为第一实施例静电放电电路的电压-电流曲线示意图。其中,第一静电放电电流路径102中的二极管共10颗(n=10),第二静电放电电流路径104中的二极管共2颗(m=2)。另外,在0V~6V之间为第一供应电压Vpp的操作区间(Vpp operationregion)。亦即,内部电路140接收的第一供应电压Vpp如果在0V~6V之间,则静电放电电路100不会被误触发。
当第一供应电压Vpp超过6V或者低于0V时,则代表可能遭受静电放电冲击(ESDzapping),静电放电电路100会根据第一供应电压Vpp的变化来动作。根据本发明的第一实施例,当第一供应电压Vpp上升到达7V时,静电放电电流到达1μA,可视为第一静电放电电流路径102已开启。另外,当第一供应电压Vpp下降-1.4V时,静电放电电流到达-1μA,可视为第二静电放电电流路径104已开启。
请参照图2B,其所绘示为本发明第一实施例静电放电电路进行人体模式(HumanBody Mode,简称HBM)测试的示意图。以人体模式(HBM)测试为例,当2KV的静电电压施加在垫150时,第一供应电压Vpp会升高至12V,且静电放电电流会上升至1.33A。此时,静电放电电流可沿着开启的第一静电放电电流路径102传导至节点g。
如图2B所示,垫150在时间点t1接收到2KV的静电电压,使得第一供应电压Vpp瞬间上升至12V,而第一静电放电电流路径102开启。再者,根据图2A可知,在时间点t1时的静电放电电流约为1.33A。
由于第一静电放电电流路径102已开启,将使得第一供应电压Vpp在时间点t2下降至7V以下。换句话说,静电放电电路100可在4μs内将第一供应电压Vpp下降至7V以下。如此,可以保护内部电路中的半导体元件不会受损。
由于静电放电电流可能流经第一静电放电电流路径102或者第二静电放电电流路径104。因此,在静电放电电路100内,必须设计大尺寸的二极管Df1~Dfn、Dr1~Drm。如此,才可以防止静电放电电流烧毁二极管Df1~Dfn、Dr1~Drm。然而,大尺寸的二极管Df1~Dfn、Dr1~Drm会有较小的寄生电阻(parasitic resistance),使得待机漏电流(standbyleakage current)增加。虽然增加第一静电放电电流路径102与第二静电放电电流路径104中串接二极管n与m的数目可以降低待机漏电流。然而,增加n与m的数目同时也会影响到第一静电放电电流路径102与第二静电放电电流路径104的开启临限电压,此时也需要一并考虑开启临限电压(n×Von)与总崩溃电压(m×Vbj)是否在适用的范围。
如图2B所示,在静电放电冲击过后,第一供应电压Vpp已经下降至7V以下。由于第一供应电压Vpp会维持在7V附近一段时间。而在这段时间内,内部电路140内的半导体元件仍受到7V的电压应力(voltage stress)影响,将使得半导体元件的特性变差,寿命减少。
请参照图3,其所绘示为本发明静电放电电路的第二实施例。静电放电电路200与内部电路240连接于接收第一供应电压Vpp的垫(pad)250与接收第二供应电压GND的节点g之间。第一供应电压Vpp由垫(pad)250输入静电放电电路200与内部电路240。第二供应电压GND由节点g输入静电放电电路200与内部电路240。第二供应电压GND可为0V。
静电放电电路200包括一分压器(voltage divider)210、RC电路220、路径控制电路230。
分压器210包括串接于垫250与节点g之间的电阻Ra、Rb、Rc。电阻Ra连接于垫250与节点a之间,电阻Rb连接于节点a与节点b之间,电阻Rc连接于节点b与节点g之间。因此,节点a可产生分压(divided voltage)Va,节点b可产生分压Vb,且分压Va大于分压Vb。
根据本发明的实施例,第一供应电压Vpp为6V且第二供应电压为0V,电阻Ra、Rb、Rc的电阻值相同。因此,分压Va为4V且分压Vb为2V。当然,本发明并未限定三个电阻Ra、Rb、Rc的电阻值,三个电阻Ra、Rb、Rc的电阻值也可以不相同。
RC电路220包括一电阻Rd与串接的电容器Ce、Cf、Cg。其中,电阻Rd连接于垫250与节点c之间,电容Ce连接于节点c与节点a之间,电容Cf连接于节点a与节点b之间,电容Cg连接于节点b与节点g之间。
路径控制电路230包括多个P型晶体管M1、M2、M3。P型晶体管M1的第一漏源端与基极端(body terminal)连接至垫250、栅极端连接至节点c。P型晶体管M2的第一漏源端与基极端连接至晶体管M1的第二漏源端,栅极端连接至节点a。P型晶体管M3的第一漏源端与基极端连接至晶体管M2的第二漏源端,栅极端连接至节点b,第二漏源端连接至节点g。
再者,每一个P型晶体管M1、M2、M3内皆有一寄生二极管(parasitic diode)Dp1、Dp2、Dp3。以P型晶体管为例,寄生二极管Dp1的阴极(cathode terminal)连接于P型晶体管M1的基极端(body terminal),阳极(anode terminal)连接于P型晶体管M1的第二漏源端。因此,串接的三个寄生二极管Dp1、Dp2、Dp3连接于垫250与节点g之间。
根据本发明的第二实施例,P型晶体管M1的第一漏源端、P型晶体管M1的信道区域(channel region)、P型晶体管M1的第二漏源端、P型晶体管M2的第一漏源端、P型晶体管M2的信道区域、P型晶体管M2的第二漏源端、P型晶体管M3的第一漏源端、P型晶体管M3的信道区域、P型晶体管M3的第二漏源端组合成为第一静电放电电流路径。而RC电路220用来控制第一静电放电电流路径的开启与关闭。
另外,P型晶体管M3的第二漏源端、寄生二极管Dp3、P型晶体管M3的第一漏源端、P型晶体管M2的第二漏源端、寄生二极管Dp2、P型晶体管M2的第一漏源端、P型晶体管M1的第二漏源端、寄生二极管Dp1、P型晶体管M1的第一漏源端组合成为第二静电放电电流路径。再者,第二静电放电电流路径的开启临限电压为2.1V(3×0.7)。也就是说,当第二供应电压GND与第一供应电压Vpp之间的电压差(0V-Vpp)大于2.1V时,第二静电放电电流路径开启。以下详细说明静电放电电路200的运作原理。
首先,当第一供应电压Vpp为6V且第二供应电压GND为0V时,分压器210中,节点a输出的分压Va为4V,节点b输出的分压Vb为2V。
在RC电路220中,节点c产生的控制电压Vc为Vpp(6V),电容器Ce之间的电压差(voltage difference)为2V(6V-4V),电容器Cf之间的电压差为2V(4V-2V),电容器Cg之间的电压差为2V(2V-0V)。
在路径控制电路230中,P型晶体管M1的栅极接收节点c的控制电压Vc(6V),P型晶体管M2的栅极接收分压Va(4V),P型晶体管M3的栅极接收分压Vb(2V)。因此,P型晶体管M1、M2、M3关闭,亦即第一静电放电电流路径关闭。
另外,由于第一供应电压Vpp为6V且第二供应电压GND为0V。因此串接的寄生二极管Dp1、Dp2、Dp3关闭,亦即第二静电放电电流路径关闭。
因此,当第一供应电压Vpp为6V且第二供应电压GND为0V时,第一静电放电电流路径与第二静电放电电流路径皆关闭,而内部电路240接收第一供应电压Vpp而正常运作。
请参照图4A,其所绘示为第二实施例静电放电电路接收到负静电放电冲击的示意图。当垫250接收到负静电放电冲击时,第二静电放电电流路径开启,且静电放电电流IESD由节点g经由寄生二极管Dp1、Dp2与Dp3流至垫250。
请参照图4B,其所绘示为第二实施例静电放电电路接收到正静电放电冲击的示意图。当垫250接收到正静电放电冲击时,第一供应电压Vpp快速上升。造成电容器Ce、Cf、Cg暂时短路,使得P型晶体管M1、M2、M3栅极接收第二供应电压GND(0V)而开启,亦即第一静电放电电流路径开启。换句话说,当垫250接收到正静电放电冲击时,第一静电放电电流路径开启,且静电放电电流IESD由垫250经由P型晶体管M1、M2、M3流至节点g。
根据本发明的实施例,RC电路220中的RC时间常数(RC time constant)被设计为约1μs。亦即,第一静电放电电流路径开启约1μs的时间后,电容器Ce、Cf、Cg再次充电至较高的电压,使得P型晶体管M1、M2、M3关闭,造成第一静电放电电流路径关闭。
根据以上的描述可知,静电放电电路200接收到正静电放电冲击时,静电放电电流IESD会在1μs的时间周期内,由垫250经由P型晶体管M1、M2、M3流至节点g。由于0V~6V之间为第一供应电压Vpp的操作区间(Vpp operation region)。亦即,而在1μs的时间后,第一供应电压Vpp回复至操作区间的范围,使得静电放电电路200不会运作,而内部电路240接收的第一供应电压Vpp。
图5A为第二实施例静电放电电路的电压-电流曲线示意图。当第一供应电压Vpp超过6V或者低于0V时,静电放电电路200会根据第一供应电压Vpp的变化来动作。另外,当第一供应电压Vpp下降-2.1V时,静电放电电流到达-1μA,可视为第二静电放电电流路径开启。
请参照图5B,其所绘示为本发明第二实施例静电放电电路进行人体模式(HBM)测试的示意图。以人体模式(HBM)测试为例,当2KV的静电电压施加在垫250时,第一供应电压Vpp会迅速地升高,而静电放电电流沿着开启的第一静电放电电流路径传导至节点g。相较于第一实施例的静电放电电路100的曲线(虚线)上升至12V,第二实施例的静电放电电路200仅会让第一供应电压Vpp上升至10.5V,两者之间的差异约为1.5V。
如图5B所示,垫250在时间点t1接收到2KV的静电电压,第一静电放电电流路径瞬间开启。如此,第一供应电压Vpp的峰值上升至约10.5V。
由于第一静电放电电流路径已开启,静电放电电路200使得第一供应电压Vpp在1μs时间之内下降至6.5V以下。在5μs之后,第一供应电压Vpp会再继续降低至约4.5V。由于第二实施例的静电放电电路在静电放电冲击之后会下降至4.5V以下。因此,4.5V的第一供应电压Vpp完全不会影响到内部电路240中的半导体元件。换句话说,第二实施例的静电放电电路有更好的放电效率(discharge performance)。
请参照图6,其所绘示为本发明静电放电电路的第三实施例。相同地,静电放电电路300包括一分压器310、RC电路320、路径控制电路230。再者,本发明的第三实施例利用晶体管来组成静电放电电路300。亦即,本发明利用晶体管的各种连接关系,使得晶体管具备电阻的特性,或者使得晶体管具备电容器的特性。
分压器310包括P型晶体管Ma、Mb、Mc。P型晶体管Ma的第一漏源端与基极端连接至垫250、第二漏源端与栅极端连接至节点a。P型晶体管Mb的第一漏源端与基极端连接至节点a、第二漏源端与栅极端连接至节点b。P型晶体管Mc的第一漏源端与基极端连接至节点b、第二漏源端与栅极端连接至节点g。由于P型晶体管Ma、Mb、Mc为二极管式连接(diodeconnected),P型晶体管Ma、Mb、Mc可视为电阻。因此,节点a可产生分压Va,节点b可产生分压Vb,且分压Va大于分压Vb。
RC电路320包括晶体管Md、Me、Mf、Mg。P型晶体管Md的第一漏源端与基极端连接至垫250,栅极端连接至节点a,第二漏源端连接至节点c。因此,P型晶体管Md可视为电阻。
P型晶体管Me的第一漏源端、第二漏源端与基极端连接至节点c,栅极端连接至节点a。P型晶体管Mf的第一漏源端、第二漏源端与基极端连接至节点a,栅极端连接至节点b。P型晶体管Mg的第一漏源端、第二漏源端与基极端连接至节点b、栅极端连接至节点g。因此,P型晶体管Me、Mf、Mg可视为电容器。
基本上,第三实施例静电放电电路300的运作原理与第二实施例相同,此处不再赘述。当然,在此领域的技术人员可以利用第二实施例中的分压电路210搭配第三实施例的RC控制电路320与路径控制电路230来组合成静电放电电路。或者,利用第三实施例中的分压电路310搭配第二实施例的RC控制电路220与路径控制电路230来组合成静电放电电路。
当然,为了要能够更确实地防止内部电路240遭受静电放电冲击,可以再改进第三实施例。
请参照图7A,其所绘示为本发明静电放电电路的第四实施例。相较于第三实施例的静电放电电路300,第四实施例的静电放电电路400中增加一个开关晶体管Msw以及一反相电路(inverter)446。以下仅介绍开关晶体管Msw以及反相电路446的运作原理。
反相电路446的输入端连接至节点c以接收控制电压Vc,第一电源端连接至垫250以接收第一供应电压Vpp,第二电源端连接至节点b以接收分压Vb。再者,开关晶体管Msw的第一漏源端与体极端连接至垫250,第二漏源端连接至节点d,栅极端连接至反相电路446的输出端。
当第一供应电压Vpp供应正常的电压(6V)时,分压Va(4V)连接至P型晶体管Md的栅极端,而控制电压Vc可视为高电平并输入反相电路446,并使得反相电路446的输出端产生低电平,且低电平为分压Vb(2V)。再者,开关晶体管Msw的栅极接收2V的低电平,使得开关晶体管Msw开启,开关晶体管Msw达成垫250与节点d之间的连接。而第一供应电压Vpp可传递至内部电路240。
当第一供应电压Vpp未提供电源时,开关晶体管Msw的栅极为浮接状态(floating),开关晶体管Msw关闭,使得开关晶体管Msw隔离垫250与节点d之间的连接。
再者,如果垫250接收到正静电放电冲击时,造成P型晶体管Me、Mf、Mg所构成电容器暂时短路,使得控制电压Vc变为低电平(GND)并输入反相电路446,而反相电路446的输出端产生高电平,且高电平为第一供应电压Vpp。再者,当开关晶体管Msw的栅极接收高电平时,开关晶体管Msw关闭,使得开关晶体管Msw隔离垫250与节点d之间的连接。更可确保静电放电电流不会经由开关晶体管Msw而传递至内部电路240。
图7B为本发明第四实施例的静电放电电路进行人体模式(HBM)测试时节点d的电压曲线示意图。在进行人体模式测试时,2KV的静电电压施加在垫250上,使得第一静电放电电流路径瞬间开启,静电放电电流沿着开启的第一静电放电电流路径快速地传导至节点g。如此,节点d上的电压峰值上升至约7V。因此,由第四实施例的电压变化可知,内部电路240仅会接收到7V的电压。另外,图7B中的虚线为第一实施例静电放电电路100的电压变化,其内部电路140接收的电压峰值会上升至12V。换句话说,当遭受到静电放电冲击的瞬间,二者之间的电压差距ΔV1约为5V。
由图7B可知,在时间电t1,2KV的静电电压施加在垫250上,节点d上的电压峰值上升至约7V。
由于第一静电放电电流路径已开启,开关晶体管Msw关闭,所以节点d的电压在1μs内会降至4V以下。而在1μs之后,节点d的电压会维持在4.5V附近。
相较于第一实施例的静电放电电路100,其遭受静电放电冲击1μs之后会降至6.5V。二者之间的电压差距ΔV2约为2.0V。由于第四实施例静电放电电路400可以将节点d的电压维持在4.5V,因此更可以保护内部电路240中的半导体元件不会受损。也就是说,第四实施例的静电放电电路400有更佳的放电效能。
由以上的说明可知,静电放电电路400可以在静电放电冲击时,开启第一静电放电电流路径或者第二静电放电电流路径开启,以有效地保护内部电路240。再者,由于开关晶体管Msw关闭,所以静电放电电流更无法经由开关晶体管Msw关闭而传递至内部电路240。
请参照图8,其所绘示为本发明静电放电电路的第五实施例。相较于第四实施例的静电放电电路400,第五实施例的静电放电电路500中提供反相电路510的一实施例。以下仅介绍反相电路510的运作原理。
反相电路510包括P型晶体管Mh、Mi以及N型晶体管Mj。P型晶体管Mh的第一漏源端与基极端连接至垫250,第二漏源端连接至节点e,栅极端连接至节点c以接收控制电压Vc。P型晶体管Mi的第一漏源端与基极端连接节点e,第二漏源端连接至节点f,栅极端连接至节点a以接收分压Va。N型晶体管Mj的第一漏源端连接至节点f,第二漏源端与基极端连接至节点b以接收分压Vb,栅极端连接至节点a以接收分压Va。
当第一供应电压Vpp供应正常的电压(6V)时,节点c的控制电压Vc为6V且分压Va(4V)。因此,P型晶体管Mh、Mi关闭,N型晶体管Mj开启,使得反相电路510产生低电平,且低电平为分压Vb(2V)。再者,开关晶体管Msw的栅极接收2V的低电平,使得开关晶体管Msw开启,开关晶体管Msw达成垫250与节点d之间的连接。而第一供应电压Vpp可传递至内部电路240。
当垫250接收接收到正静电放电冲击时,造成P型晶体管Me、Mf、Mg所构成电容器暂时短路,使得节点c的控制电压Vc以及分压Va变为低电平(GND)并输入反相电路510。因此,P型晶体管Mh、Mi开启,N型晶体管Mj关闭,使得反相电路510产生高电平,且高电平为第一供应电压Vpp。再者,开关晶体管Msw的栅极接收高电平,开关晶体管Msw关闭,使得开关晶体管Msw隔离垫250与节点d之间的连接。更可确保静电放电电流不会经由开关晶体管Msw而传递至内部电路240。
虽然本发明的第二实施例至第五实施例中,路径控制电路230仅提供三个堆迭的P型晶体管(stacked MOS transistors),然而本发明并不限定于只有三个堆迭的P型晶体管。在此领域的技术人员可以利用分压电路来提供更多的分压至路径控制电路中堆迭的多个P型晶体管,也可以达成本发明的目的。
再者,分压电路中的电阻可以设计为具有高电阻值,即可有效地降低静电放电电路的漏电流(leakage current),。再者,为了提升静电放电电路的放电效率,路径控制电路中的P型晶体管M1、M2、M3可设计为大尺寸(size)的晶体管。相同地,开关晶体管Msw也可以设计为大尺寸的晶体管。
综上所述,虽然本发明已以实施例公开如上,然其并非用以限定本发明。本发明所属领域技术人员,在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当视所附权利要求书界定范围为准。
Claims (12)
1.一种静电放电电路,连接至一垫,该静电放电电路包括:
分压器,连接于该垫与第一节点之间,该分压器提供多个分压;
RC电路,连接于该垫与该第一节点之间,该RC电路接收这些分压,并提供控制电压;以及
路径控制电路,连接于该垫与该第一节点之间,该路径控制电路接收这些分压与该控制电压;
其中,当该垫接收正静电放电冲击时,该RC电路控制该路径控制电路,使得第一静电放电路径开启,并将静电放电电流由该垫经由该第一静电放电路径传递至该第一节点。
2.如权利要求1所述的静电放电电路,其中该分压器包括:
第一电阻,具有第一端连接至该垫,第二端连接至第二节点;
第二电阻,具有第一端连接至该第二节点,第二端连接至第三节点;以及
第三电阻,具有第一端连接至该第三节点,第二端连接至该第一节点;
其中,该第二节点产生第一分压,该第三节点产生第二分压。
3.如权利要求2所述的静电放电电路,其中第一晶体管的第一漏源端与基极端相互连接作为该第一电阻的该第一端,该第一晶体管的第二漏源端与栅极端相互连接作为该第一电阻的该第二端;第二晶体管的第一漏源端与基极端相互连接作为该第二电阻的该第一端,该第二晶体管的第二漏源端与栅极端相互连接作为该第二电阻的该第二端;以及,第三晶体管的第一漏源端与基极端相互连接作为该第三电阻的该第一端,该第三晶体管的第二漏源端与栅极端相互连接作为该第三电阻的该第二端。
4.如权利要求2所述的静电放电电路,其中该RC电路包括:
第四电阻,具有第一端连接至该垫,第二端连接至第四节点;
第一电容器,具有第一端连接至该第四节点,第二端连接至该第二节点;
第二电容器,具有第一端连接至该第二节点,第二端连接至该第三节点;以及
第三电容器,具有第一端连接至该第三节点,第二端连接至该第一节点;
其中,该第四节点产生该控制电压。
5.如权利要求4所述的静电放电电路,其中第四晶体管的第一漏源端与基极端相互连接作为该第四电阻的该第一端,该第四晶体管的栅极端连接至该第二节点,该第四晶体管的第二漏源端作为该第四电阻的该第二端;第五晶体管的第一漏源端、第二漏源端与基极端相互连接作为该第一电容器的该第一端,该第五晶体管的栅极端作为该第一电容器的该第二端;第六晶体管的第一漏源端、第二漏源端与基极端相互连接作为该第二电容器的该第一端,该第六晶体管的栅极端作为该第二电容器的该第二端;以及第七晶体管的第一漏源端、第二漏源端与基极端相互连接作为该第三电容器的该第一端,该第七晶体管的栅极端作为该第三电容器的该第二端。
6.如权利要求2所述的静电放电电路,其中该路径控制电路包括:
第八晶体管,第一漏源端与基极端连接至该垫,栅极端接收该控制电压;
第九晶体管,第一漏源端与基极端连接至该第八晶体管的第二漏源端,栅极端接收该第一分压;以及
第十晶体管,第一漏源端与基极端连接至该第九晶体管的第二漏源端,栅极端接收该第二分压,第二漏源端连接至该第一节点。
7.如权利要求6所述的静电放电电路,其中该第八晶体管包括第一寄生二极管,具有阳极端连接于该第八晶体管的该第二漏源端,阴极端连接于该第八晶体管的该第一漏源端;该第九晶体管包括第二寄生二极管,具有阳极端连接于该第九晶体管的该第二漏源端,阴极端连接于该第九晶体管的该第一漏源端;以及该第十晶体管包括第三寄生二极管,具有阳极端连接于该第十晶体管的该第二漏源端,阴极端连接于该第十晶体管的该第一漏源端。
8.如权利要求7所述的静电放电电路,其中,该第八晶体管的该第一漏源端、该第八晶体管的信道区域、该第八晶体管的该第二漏源端、该第九晶体管的该第一漏源端、该第九晶体管的信道区域、该第九晶体管的该第二漏源端、该第十晶体管的该第一漏源端、该第十晶体管的信道区域、该第十晶体管的该第二漏源端组合成为该第一静电放电电流路径。
9.如权利要求7所述的静电放电电路,其中,该第十晶体管的该第二漏源端、该第三寄生二极管、该第十晶体管的该第一漏源端、该第九晶体管的该第二漏源端、该第二寄生二极管、该第九晶体管的该第一漏源端、该第八晶体管的该第二漏源端、该第一寄生二极管、该第八晶体管的该第一漏源端组合成为第二静电放电电流路径。
10.如权利要求2所述的静电放电电路,还包括开关晶体管连接于该垫与内部电路之间,其中该开关晶体管的第一漏源端连接至该垫,第二漏源端连接至该内部电路。
11.如权利要求10所述的静电放电电路,还包括反相电路,具有输入端接收该控制电压,第一电源端连接至该垫,第二电源端接收该第二分压,输出端连接至该开关晶体管的栅极端。
12.如权利要求10所述的静电放电电路,还包括反相电路,包括:
第十一晶体管,第一漏源端与基极端连接至该垫,栅极端接收该控制电压,第二漏源端连接至第五节点;
第十二晶体管,第一漏源端与基极端连接至该第五节点,栅极端接收该第一分压,第二漏源端连接至第六节点;以及
第十三晶体管,第一漏源端连接至该第六节点,栅极端接收该第一分压,第二漏源端接收该第二分压;
其中,该第六节点连接至该开关晶体管的栅极端。
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US10475491B2 (en) | 2019-11-12 |
JP2018186256A (ja) | 2018-11-22 |
TWI630707B (zh) | 2018-07-21 |
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CN108806755A (zh) | 2018-11-13 |
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TWI657633B (zh) | 2019-04-21 |
US20180315462A1 (en) | 2018-11-01 |
JP2018190407A (ja) | 2018-11-29 |
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CN108807365B (zh) | 2020-10-16 |
TW201839771A (zh) | 2018-11-01 |
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EP3396673A1 (en) | 2018-10-31 |
US10090309B1 (en) | 2018-10-02 |
US20180315460A1 (en) | 2018-11-01 |
TW201839604A (zh) | 2018-11-01 |
US10410697B2 (en) | 2019-09-10 |
US10181342B2 (en) | 2019-01-15 |
CN108807388A (zh) | 2018-11-13 |
JP6603963B2 (ja) | 2019-11-13 |
JP6487969B2 (ja) | 2019-03-20 |
TW201840087A (zh) | 2018-11-01 |
TWI657448B (zh) | 2019-04-21 |
CN108807388B (zh) | 2021-03-02 |
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