CN110391650B - 静电放电电路 - Google Patents

静电放电电路 Download PDF

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CN110391650B
CN110391650B CN201910214539.XA CN201910214539A CN110391650B CN 110391650 B CN110391650 B CN 110391650B CN 201910214539 A CN201910214539 A CN 201910214539A CN 110391650 B CN110391650 B CN 110391650B
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赖致玮
丁韵仁
吴易翰
林坤信
许信坤
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eMemory Technology Inc
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Abstract

本发明公开一种静电放电电路，连接在电源垫与第一节点之间。此静电放电电路包括：RC电路以及第一静电放电电流路径。RC电路连接在电源垫与第一节点之间，用以提供第一控制电压与第二控制电压。第一静电放电电流路径连接在电源垫与第一节点之间。当电源垫接收正静电放电冲击时，根据RC电路所提供的第一控制电压与第二控制电压，使得第一静电放电电流路径导通，并将静电放电电流由电源垫经由第一静电放电电流路径传递至第一节点。

Description

静电放电电路
技术领域
本发明涉及一种电路，且特别涉及一种静电放电(electro static discharge，简称ESD)电路。
背景技术
众所周知，在互补式金属氧化物半导体的集成电路(CMOS IC)工艺中，为增加其速度与整合度，半导体元件尺寸会越做越小、栅极氧化层(Gate oxidelayer)会越来越薄。因此，栅极氧化层的崩溃电压(breakdown voltage)降低，且半导体元件的PN接面(PNjunction)的崩溃电压也降低。
为了避免集成电路(IC)在生产过程中被静电放电冲击(ESD zapping)所损伤，在集成电路(IC)内皆会制作静电放电电路。静电放电电路提供了静电放电电流路径(ESDcurrent path)，以免静电放电流(ESD current)流入IC内部电路而造成损伤。
发明内容
本发明涉及一种静电放电电路，连接在一电源垫与一第一节点之间，该静电放电电路包括：一RC电路，连接在该电源垫与该第一节点之间，用以提供一第一控制电压与一第二控制电压；以及一第一静电放电电流路径，连接在该电源垫与该第一节点之间，其中当该电源垫接收一正静电放电冲击时，根据该RC电路提供的该第一控制电压与该第二控制电压，使得该第一静电放电电流路径导通，并将一静电放电电流由该电源垫经由该第一静电放电电流路径传递至该第一节点。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合附图详细说明如下：
附图说明
图1所绘示为本发明静电放电电路的第一实施例。
图2A为第一实施例静电放电电路的电压-电流曲线示意图。
图2B为本发明第一实施例静电放电电路进行人体模式(HBM)测试时的供应电压Vpp与时间关系图。
图3为本发明静电放电电路的第二实施例。
图4A至图4C为电容库的各种范例。
图5A为第二实施例静电放电电路接收到负静电放电冲击的示意图。
图5B为第二实施例静电放电电路接收到正静电放电冲击的示意图。
图6为本发明第二实施例静电放电电路进行人体模式(HBM)测试的供应电压Vpp与时间关系图。
图7为本发明静电放电电路的第三实施例。
【符号说明】
100、200、700：静电放电电路
102：第一静电放电电流路径
104：第二静电放电电流路径
140、240：内部电路
150、250：电源垫
210、710：RC电路
215、715：电容库
具体实施方式
在非易失性存储器的编程动作或者抹除动作时，编程电压(program voltage)或者抹除电压(erase voltage)会供应至非易失性存储器中用以编程存储器胞或者抹除存储器胞。
通常，编程电压或者抹除电压会非常接近半导体元件的耐压，但并不会损毁半导体元件。举例来说，非易失性存储器内部电路的半导体元件为MOS晶体管，其操作电压为1.8V，而编程电压为4.5V。虽然MOS晶体管可以承受4.5V的电压应力(voltage stress)，但如果MOS晶体管承受的电压应力再增大一些(例如4.8V以上)时，则MOS晶体管就会有损毁的危险。
为了要解决上述的问题，在非易失性存储器中必须设计静电放电电路，且静电放电电路的导通临限电压(turn on threshold voltage)需要稍微大于4.5V，且越接近4.5V越好。当非易失性存储器接收到静电放电冲击(ESD zapping)时，即可快速地将静电放电电流排除，以保护非易失性存储器的内部电路。
请参照图1，其所绘示为本发明静电放电电路的第一实施例。静电放电电路100与内部电路140连接在接收第一供应电压Vpp的电源垫(power pad)150与接收第二供应电压GND的节点g之间。第一供应电压Vpp由电源垫150输入静电放电电路100与内部电路140。第二供应电压GND由节点g输入静电放电电路100与内部电路140。在本实施例中，第二供应电压GND为0V。
静电放电电路100中包括一第一静电放电电流路径(first ESD current path)102与一第二静电放电电流路径(second ESD current path)104。其中，第一静电放电电流路径102包括n个二极管Df1～Dfn串接在电源垫150与节点g之间。第二静电放电电流路径104包括m个二极管Dr1～Drm串接在电源垫150与节点g之间。
基本上，第一静电放电电流路径102的导通临限电压(turn-on thresholdvoltage)为n×Von，其中Von为二极管的切入电压(cut in voltage)，例如0.7V。因此，当第一供应电压Vpp与第二供应电压GND之间的电压差(Vpp-0V)大于n×Von时，第一静电放电电流路径102导通。
由以上的说明可知，第一静电放电电流路径102的导通临限电压(n×Von)必需设定成大于第一供应电压Vpp(例如4.5V)。如果将第一静电放电电流路径102的导通临限电压(n×Von)设定成小于第一供应电压Vpp(例如4.5V)，则会造成第一静电放电电流路径102的误触发(mis-trigger)。同样地，第一静电放电电流路径102的导通临限电压(n×Von)必需设定成小于第二静电放电电流路径104的总崩溃电压(m×Vbj)，其中Vbj为单一二极管的崩溃电压(breakdown voltage)。如果将第一静电放电电流路径102的导通临限电压(n×Von)设定成大于第二静电放电电流路径104的总崩溃电压(m×Vbj)，则会造成第二静电放电电流路径104的误触发(mis-trigger)，并发生二极管崩溃(diode breakdon)。举例来说，当电源垫150接收正的静电电压时，第一静电放电电流路径102会立即导通，以避免造成第二静电放电电流路径104上的二极管崩溃。
同理，第二静电放电电流路径104导通临限电压为m×Von。换句话说，当第二供应电压GND与第一供应电压Vpp之间的电压差(0V-Vpp)大于m×Von时，第二静电放电电流路径104导通。
举例来说，假设二极管的切入电压Von为0.7V，崩溃电压Vbj为4V，且内部电路140的电压操作范围为0V至4.5V之间。因此，静电放电电路100中，第一静电放电电流路径102至少要串接7颗(7×0.7V＝4.9V)二极管，第二静电放电电流路径104至少要串接2颗(2×4V＝8V)二极管。如此，才不会误触发第一静电放电电流路径102或者第二静电放电电流路径104。
为了防止工艺变异(process variation)而造成二极管切入电压Von的变化，可以在第一静电放电电流路径102再增加一颗二极管。如此可以确认第一静电放电电流路径102不会在正常运作时误触发。
因此，当电源垫150接收到正静电放电冲击(positive ESD zapping)时，第一静电放电电流路径102导通，且静电放电电流由电源垫150经由第一静电放电电流路径102流至节点g。反之，当电源垫150接收到负静电放电冲击(negative ESD zapping)时，第二静电放电电流路径104导通，且静电放电电流由节点g经由第二静电放电电流路径104流至电源垫150。
请参照图2A，其所绘示为第一实施例静电放电电路的电压-电流曲线示意图。其中，第一静电放电电流路径102中的二极管共7颗(n＝7)，第二静电放电电流路径104中的二极管共2颗(m＝2)。另外，在0V～4.5V之间为第一供应电压Vpp的操作区间(Vpp operationregion)。亦即，内部电路140接收的第一供应电压Vpp如果在0V～4.5V之间，则静电放电电路100被禁能(disable)，且二静电放电电流路径102、104皆关闭。
当第一供应电压Vpp超过4.5V或者低于0V时，则代表可能遭受静电放电冲击(ESDzapping)，静电放电电路100会根据第一供应电压Vpp的变化来动作。根据本发明的第一实施例，当第一供应电压Vpp上升到达4.9V时，静电放电电流到达1μA，可视为第一静电放电电流路径102已导通。另外，当第一供应电压Vpp下降-1.4V时，静电放电电流到达-1μA，可视为第二静电放电电流路径104已导通。
请参照图2B，其所绘示为本发明第一实施例静电放电电路进行人体模式(HumanBody Mode，简称HBM)测试时的供应电压Vpp与时间关系图。以人体模式(HBM)测试为例，当2KV的静电电压施加在电源垫150时，第一供应电压Vpp会升高至12V，且静电放电电流会上升至1.33A。此时，静电放电电流可沿着导通的第一静电放电电流路径102传导至节点g。
如图2B所示，电源垫150在时间点t1接收到2KV的静电电压，使得第一供应电压Vpp瞬间上升至12V，而第一静电放电电流路径102导通。再者，根据图2A可知，在时间点t1时的静电放电电流约为1.33A。
由于第一静电放电电流路径102已导通，将使得第一供应电压Vpp在时间点t2下降至4.9V以下。换句话说，静电放电电路100可在4μs内将第一供应电压Vpp下降至4.5V以下。如此，可以保护内部电路中的半导体元件不会受损。
由于静电放电电流可能流经第一静电放电电流路径102或者第二静电放电电流路径104。因此，在静电放电电路100内，必须设计大尺寸的二极管Df1～Dfn、Dr1～Drm。如此，才可以防止静电放电电流烧毁二极管Df1～Dfn、Dr1～Drm。然而，大尺寸的二极管Df1～Dfn、Dr1～Drm会有较小的寄生电阻(parasitic resistance)，使得待机漏电流(standbyleakage current)增加。虽然增加第一静电放电电流路径102与第二静电放电电流路径104中串接二极管n与m的数目可以降低待机漏电流。然而，增加n与m的数目同时也会影响到第一静电放电电流路径102与第二静电放电电流路径104的导通临限电压，此时也需要一并考虑导通临限电压(n×Von)与总崩溃电压(m×Vbj)是否在适用的范围。
如图2B所示，在静电放电冲击过后，第一供应电压Vpp已经下降至4.5以下。由于第一供应电压Vpp会维持在4.5V附近一段时间。而在这段时间内，内部电路140内的半导体元件仍受到4.5V的电压应力(voltage stress)影响，将使得半导体元件的特性变差，寿命减少。
请参照图3，其所绘示为本发明静电放电电路的第二实施例。静电放电电路200与内部电路240连接在接收第一供应电压Vpp的电源垫250与接收第二供应电压GND的节点g之间。第一供应电压Vpp由电源垫250输入静电放电电路200与内部电路240。第二供应电压GND由节点g输入静电放电电路200与内部电路240。
静电放电电路200包括一RC电路210、P型晶体管M1与N型晶体管M2。其中，P型晶体管M1为P型鳍式晶体管(FinFET)，且N型晶体管M2为N型鳍式晶体管。再者，P型晶体管M1连接在电源垫250与节点d之间。N型晶体管M2连接在节点d与节点g之间。RC电路210连接在电源垫250与节点g之间。RC电路210具有二个控制端分别连接至P型晶体管M1的控制端与N型晶体管M2的控制端。当电源垫250接收到静电放电冲击时，RC电路210能够产生控制电压Va与Vb用以导通P型晶体管M1与N型晶体管M2。
RC电路210包括一第一电阻R1、一第二电阻R2与一电容库(capacitor bank)215。第一电阻R1连接在电源垫250与节点a之间，且节点a能够产生第一控制电压Va。第二电阻R2连接在节点b与节点g之间，且节点b能够产生第二控制电压Vb。电容库215连接在节点a与节点b之间。值得注意地，电容库215并未连接至节点d。
P型晶体管M1包括一第一漏/源端(drain/source terminal)连接至电源垫250、一第二漏/源端连接至节点d、一栅极端连接至节点a、一基体端(body terminal)连接至电源垫250。另外，由于P型晶体管M1制作在N型井区(N-well region)中，所以P型晶体管M1内部存在一寄生二极管(parasitic diode)Dp，其阴极端(Cathode terminal)连接至P型晶体管M1的第一漏/源端，其阳极端(Anode terminal)P型晶体管M1的第二漏/源端。
N型晶体管M2包括一第一漏/源端连接至节点d、一第二漏/源端连接至节点g、一栅极端连接至节点b、一基体端连接至节点g。另外，由于N型晶体管M2制作在P型井区(P-wellregion)中，所以N型晶体管M2内部存在一寄生二极管Dn，其阴极端连接至N型晶体管M2的第一漏/源端，其阳极端N型晶体管M2的第二漏/源端。换句话说，二个寄生二极管Dp、Dn串接在电源垫250与节点d之间。
根据本发明的第二实施例，第一供应电压Vpp为4.5V且第二供应电压为0V，第一电阻R1与第二电阻R2的电阻值相同。
再者，P型晶体管M1的第一漏/源端、P型晶体管M1的沟道区域(channel region)、P型晶体管M1的第二漏/源端、N型晶体管M2的第一漏/源端、N型晶体管M2的沟道区域、N型晶体管M2的第二漏/源端组合成为第一静电放电电流路径。而RC电路210用来控制第一静电放电电流路径的导通与关闭。
另外，N型晶体管M2的第二漏/源端、寄生二极管Dn、N型晶体管M2的第一漏/源端、P型晶体管M1的第二漏/源端、寄生二极管Dp、P型晶体管M1的第一漏/源端组合成为第二静电放电电流路径。再者，第二静电放电电流路径的导通临限电压为1.4V(2×0.7)。也就是说，当第二供应电压GND与第一供应电压Vpp之间的电压差(0V-Vpp)大于1.4V时，第二静电放电电流路径导通。以下详细说明静电放电电路200的运作原理。
首先，当第一供应电压Vpp为4.5V且第二供应电压GND为0V时，电容库215之间的跨压为4.5V。亦即，第一控制电压Va为4.5V，第二控制电压Vb为0V。
再者，P型晶体管M1的栅极接收节点a的第一控制电压Va(4.5V)，N型晶体管M2的栅极接收节电b的第二控制电压Vb(0V)。因此，P型晶体管M1与N型晶体管M2皆关闭，亦即第一静电放电电流路径关闭。
另外，由于第一供应电压Vpp为4.5V且第二供应电压GND为0V。因此串接的寄生二极管Dp、Dn关闭，亦即第二静电放电电流路径关闭。
因此，当第一供应电压Vpp为4.5V且第二供应电压GND为0V时，第一静电放电电流路径与第二静电放电电流路径皆关闭，而内部电路240接收第一供应电压Vpp而正常运作。
根据本发明的第二实施例，电容库215中至少包括一电容器。图4A至图4C为电容库的各种范例。如图4A所示，电容库215中仅有单一个电容器C1连接在节点a与节点b之间。如图4B所示，电容库215包括二个电容器C1、C2，串联在节点a与节点b之间。如图4C所示，电容库215包括二个电容器C1、C2，并联在节点a与节点b之间。以下以二个串连的电容器所组成的电容库215为例来介绍静电放电电路200的运作，而其他类型的电容库运作原理类似，不再赘述。
请参照图5A，其所绘示为第二实施例静电放电电路接收到负静电放电冲击的示意图。当电源垫250接收到负静电放电冲击时，第二静电放电电流路径导通，且静电放电电流IESD由节点g经由寄生二极管Dn与Dp流至电源垫250。
请参照图5B，其所绘示为第二实施例静电放电电路接收到正静电放电冲击的示意图。当电源垫250接收到正静电放电冲击时，第一供应电压Vpp快速上升。造成电容库215中的电容器C1、C2暂时短路，使得节点e上的电压为Vpp/2，而节点a的第一控制电压Va则稍微大于Vpp/2(例如，Vpp/2+ΔV)，节点b的第二控制电压Vb则稍微小于Vpp/2(例如，Vpp/2-ΔV)。由于，P型晶体管M1与N型晶体管M2栅极别接收第一控制电压Va与第二控制电压Vb，所以P型晶体管M1与N型晶体管M2会同时导通，使得第一静电放电电流路径导通，且静电放电电流IESD。换句话说，当电源垫250接收到正静电放电冲击时，第一静电放电电流路径导通，且静电放电电流IESD由电源垫250经由P型晶体管M1与N型晶体管M2流至节点g。
根据本发明的第二实施例，RC电路120中的RC时间常数(RC timeconstant)被设计为约1μs。亦即，第一静电放电电流路径导通约1μs的时间后，第一供应电压Vpp会下降到低于导通临限电压(例如4.5V)。此时，第一控制电压Va为第一供应电压Vpp且第二控制电压Vb为0V，所以P型晶体管M1与N型晶体管M2会关闭，使得第一静电放电电流路径关闭。
根据以上的描述可知，静电放电电路200接收到正静电放电冲击时，静电放电电流IESD会在1μs的时间周期内，由电源垫250经由P型晶体管M1与N型晶体管M2流至节点g。
请参照图6，其所绘示为本发明第二实施例静电放电电路进行人体模式(HBM)测试的供应电压Vpp与时间关系图。以人体模式(HBM)测试为例，当2KV的静电电压施加在电源垫250时，第一供应电压Vpp会迅速地升高，而静电放电电流沿着导通的第一静电放电电流路径传导至节点g。相较于第一实施例的静电放电电路100的曲线(虚线)上升至12V，第二实施例的静电放电电路200仅会让第一供应电压Vpp上升至4.8V，两者之间的差异约为7.2V。
如图6所示，电源垫250在时间点t1接收到2KV的静电电压，第一静电放电电流路径瞬间导通。如此，第一供应电压Vpp的峰值上升至约4.8V且静电放电电流约为1.33A。
由于第一静电放电电流路径已导通，静电放电电路200使得第一供应电压Vpp在1μs时间之内下降至1.5V以下。在5μs之后，第一供应电压Vpp会再继续降低至约1V。由于第二实施例的静电放电电路在静电放电冲击之后会下降至1V以下。因此，1V的第一供应电压Vpp完全不会影响到内部电路240中的半导体元件。换句话说，第二实施例的静电放电电路有更好的放电效率(discharge performance)。
另外，在半导体工艺中，第一电阻R1与第二电阻R2可由多晶硅电阻(polysiliconresistor)来时现，而电容器则可由金属-绝缘体-金属(Metal-Insulator-Metal，简称MIM)电容器来实现。当然，本发明并不限定于此，除了利用上述方式来形成RC电路210中的电容器与电阻之外，RC电路210中的电容器与电阻也可以由晶体管来实现。
请参照图7，其所绘示为本发明静电放电电路的第三实施例。相同地，静电放电电路700包括RC电路710、P型晶体管M1与N型晶体管M2。其中，RC电路710皆由晶体管所组成。利用晶体管的各种连接关系，即使得晶体管等效为电阻或者电容器。
RC电路710包括多个P型晶体管Mr1、Mr2、Mc1、Mc2，而这些P型晶体管Mr1、Mr2、Mc1、Mc2可为P型鳍式晶体管。P型晶体管Mr1的第一漏/源端与基体端连接至电源垫250，P型晶体管Mr1的第二漏/源端与栅极端连接至节点a。P型晶体管Mr2的第一漏/源端与基体端连接至节点b，P型晶体管Mr2的第二漏/源端与栅极端连接至节点g。由于P型晶体管Mr1、Mr2为二极管式连接(diode connection)，所以可以视为电阻。
RC电路710中的电容库715包括P型晶体管Mc1、Mc2。P型晶体管Mc1的第一漏/源端、第二漏/源端与基体端连接至节点a，P型晶体管Mc1的栅极端连接至节点e。P型晶体管Mc2的第一漏/源端、第二漏/源端与基体端连接至节点e，P型晶体管Mc2的栅极端连接至节点b。因此，P型晶体管Mc1、Mc2可以视为电容器。
再者，第三实施例的静电放电电路700的运作原理类似于第二实施例，因此不再赘述。值得注意地，本发明也可以根据第二实施例与第三实施例来适当地修改。例如，RC电路可由二个多晶硅电阻以及晶体管所组成的二个电容器来实现。或者，RC电路可由晶体管所组成的二个电阻以及二个金属-绝缘体-金属(MIM)电容器来实现。
由以上的说明可知，本发明提出一种运用于非易失性存储器的静电放电电路。当非易失性存储器发生静电放电冲击时，静电放电电流可由静电放电电路快速消除，用以保护非易失性存储器的内部电路。
综上所述，虽然本发明已以实施例公开如上，然其并非用以限定本发明。本发明所属领域技术人员在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视所附权利要求书界定范围为准。

Claims (9)

1.一种静电放电电路，连接于电源垫与第一节点之间，该静电放电电路包括：
RC电路，连接在该电源垫与该第一节点之间，用以提供第一控制电压与第二控制电压，其中该RC电路包括：第一电阻，具有第一端连接至该电源垫，以及具有第二端连接至第三节点；第二电阻，具有第一端连接至第四节点，以及具有第二端连接至该第一节点；以及，电容库，具有第一端连接至该第三节点，以及具有第二端连接至该第四节点；
第一P型晶体管，具有第一漏/源端与基体端连接至该电源垫，具有栅极端接收该第一控制电压，以及具有第二漏/源端连接至第二节点；以及
第一N型晶体管，具有第一漏/源端至该第二节点，具有栅极端接收该第二控制电压，以及具有第二漏/源端与基体端连接至该第一节点；
其中，该第一P型晶体管的该第一漏/源端、该第一P型晶体管的沟道区域、该第一P型晶体管的该第二漏/源端、该第一N型晶体管的该第一漏/源端、该第一N型晶体管的沟道区域、该第一N型晶体管的该第二漏/源端组合成为第一静电放电电流路径，且该第一静电放电电流路径连接在该电源垫与该第一节点之间；
其中，当该电源垫接收正静电放电冲击时，根据该RC电路提供的该第一控制电压与该第二控制电压，使得该第一P型晶体管与该第一N型晶体管同时导通，并使得该第一静电放电电流路径导通，并将静电放电电流由该电源垫经由该第一静电放电电流路径传递至该第一节点；
其中，该电容库未连接至该第二节点，该第三节点输出该第一控制电压，且该第四节点输出该第二控制电压。
2.如权利要求1所述的静电放电电路，其中该第一P型晶体管包括第一寄生二极管，具有阳极端连接在该第一P型晶体管的该第二漏/源端，阴极端连接在该第一P型晶体管的该第一漏/源端；且该第一N型晶体管包括第二寄生二极管，具有阳极端连接在该第一N型晶体管的该第二漏/源端，阴极端连接在该第一N型晶体管的该第一漏/源端。
3.如权利要求2所述的静电放电电路，其中，该第一N型晶体管的该第二漏/源端、该第二寄生二极管、该第一N型晶体管的该第一漏/源端、该第一P型晶体管的该第二漏/源端、该第一寄生二极管、该第一P型晶体管的该第一漏/源端界定第二静电放电电流路径。
4.如权利要求1所述的静电放电电路，其中，当该电源垫接收负静电放电冲击时，第二静电放电电流路径导通，并将该静电放电电流自第一节点经由该第二静电放电电流路径传递至该电源垫。
5.如权利要求1所述的静电放电电路，其中该电容库包括至少一电容器。
6.如权利要求5所述的静电放电电路，其中该第一电阻或者该第二电阻为多晶硅电阻，或者该至少一电容器为金属-绝缘体-金属电容器。
7.如权利要求1所述的静电放电电路，其中第二P型晶体管的第一漏/源端与基体端互相连接用来做为该第一电阻的该第一端；该第二P型晶体管的第二漏/源端与栅极端互相连接用来做为该第一电阻的该第二端；第三P型晶体管的第一漏/源端与基体端互相连接用来做为该第二电阻的该第一端；且该第三P型晶体管的第二漏/源端与栅极端互相连接用来做为该第二电阻的该第二端。
8.如权利要求1所述的静电放电电路，其中该电容库包括：
第一电容器，具有第一端连接至该第三节点，以及第二端连接至第五节点；以及
第二电容器，具有第一端连接至该第五节点，以及第二端连接至该第四节点。
9.如权利要求8所述的静电放电电路，其中第四P型晶体管的第一漏/源端、第二漏/源端与基体端互相连接用来做为该第一电容器的该第一端；该第四P型晶体管的栅极端做为该第一电容器的该第二端；第五P型晶体管的第一漏/源端、第二漏/源端与基体端互相连接用来做为该第二电容器的该第一端；以及该第五P型晶体管的栅极端做为该第二电容器的该第二端。
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