201117216 六、發明說明： 【發明所屬之技術領域】 本心明係相關於種用於快閃記憶體之靜電放電保護電路，尤 指-種具有職N井控梅護_之靜電放電保護之快閃記憶體電 路0 【先前技術】 快閃記憶縣，_發性記憶體，常用於記憶卡、快閃驅食 器以及可攜式電子裝置中，以提供:#_存與傳輸。快閃記憶心 藉由寫入、抹除以及重新編程等電性操作進行資料的刪除以及新， =的寫入。制記憶體之優點包含快速的讀出存取時間以及抗震 專。快閃記憶體對於壓力以及溫度的變化亦有良好的抗性。 請參考第1圖，第1圖為快閃記情辦雪女 咯料* 體電路1G之示意圖。快閃言 憶體電路1G包含減錄__⑽，可藉由施加編程電壓 ^ =輸人端WP—PAD進行編程。__路UG可驅_ ，3二之閘極以使編程電壓vpp被傳送到快閃記憶區塊刚。當爲 耘電壓VPP施加於輸入端ypPj>AD時，第一 ~ 不电日日體MN導通而杂 低了施加於傳遞閘⑽之開極之電壓。因此，傳遞閘13()導通，山 時編程電壓VPP可傳送到快閃記憶區塊1〇〇。 201117216 請參考第2圖。輸入端VPP_PAD是快閃記憶體電路10可能產 生靜電放電(ESD)的來源之一。為了減輕靜電放電的影響，目標是將 多餘的電荷引導到低壓的節點，例如節點VSS。因此，快閃記憶體 電路10另包含靜電放電電晶體M—ESD用來引導靜電放電電流遠離 快閃記憶區塊100。當施加到輸入端VPP_PAD之電壓上升時，靜電 放電電晶體M—ESD之閘極將藉由第二電晶體MP使得節點G1之電 壓暫時被拉高，因為當金屬氧化半導體(MOS)電容NC受到靜電放 電而充電時，MOS電容NC以及電阻R將使得第一電晶體_以 及第二電晶體MP之閘極保持在低壓。靜電放電的破壞通常發生的 時間在奈秒(ns)等級，因此，藉由電阻R以及MOS電容NC所設計 的RC時間常數大約為！微秒㈣以使靜電放電電晶體卿保持 導通夠長的時’大部分或全部的靜電放電電流引導開^而，若 靜電放電電晶體m_esd之卩雜之電壓無法即時制編程電壓201117216 VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an electrostatic discharge protection circuit for a flash memory, in particular, an electrostatic discharge protection with a N-well control Flash memory circuit 0 [Prior Art] Flash memory county, _ hair memory, commonly used in memory cards, flash memory devices and portable electronic devices to provide: #_存和传输. Flash memory The deletion of data and the writing of new, = by electrical operations such as writing, erasing, and reprogramming. The advantages of memory include fast read access time and seismic resistance. Flash memory is also resistant to changes in pressure and temperature. Please refer to Figure 1, the first picture is a schematic diagram of the body circuit 1G. Flash memory The memory circuit 1G includes a subtraction __(10) which can be programmed by applying a programming voltage ^ = input terminal WP-PAD. __路UG can drive _, 3 2 gate so that the programming voltage vpp is transferred to the flash memory block just. When the 耘 voltage VPP is applied to the input terminal ypPj > AD, the first ~ non-electric day MN is turned on and the voltage applied to the open end of the transfer gate (10) is low. Therefore, the transfer gate 13 () is turned on, and the mountain programming voltage VPP can be transferred to the flash memory block 1 . 201117216 Please refer to Figure 2. The input terminal VPP_PAD is one of the sources of possible electrostatic discharge (ESD) of the flash memory circuit 10. To mitigate the effects of electrostatic discharge, the goal is to direct excess charge to low voltage nodes, such as node VSS. Therefore, the flash memory circuit 10 further includes an electrostatic discharge transistor M-ESD for directing the electrostatic discharge current away from the flash memory block 100. When the voltage applied to the input terminal VPP_PAD rises, the gate of the electrostatic discharge transistor M_ESD will temporarily pull the voltage of the node G1 by the second transistor MP because the metal oxide semiconductor (MOS) capacitor NC is subjected to When charged by electrostatic discharge, the MOS capacitor NC and the resistor R will keep the gates of the first transistor _ and the second transistor MP at a low voltage. The destruction of electrostatic discharge usually occurs at the nanosecond (ns) level. Therefore, the RC time constant designed by the resistor R and the MOS capacitor NC is approximately! Microseconds (4) When the ESD transistor is kept on for a long time, most or all of the ESD current is turned on, and if the voltage of the electrostatic discharge transistor m_esd is noisy, the programming voltage cannot be programmed immediately.
，靜電放電電荷將進入快閃記憶區塊⑽。這是因為傳遞間⑽ K會因為N井電壓比節點⑴還高(傳遞閘⑽之基體直接接收 知加於輸人端VPPJ>AD的麵)畴通所造成的。 【發明内容】 種具有靜電放電保護之怏閃 因此，本發明之一目的在於提供— 記憶體電路。 201117216 本發明係提供-種快閃記憶體電路，包含複數個快閃記憶區 塊、輸入端、-閘極驅動電路、一靜電放電電晶體以及一傳遞電 日日體。5亥輸入端用來接收—輪入電壓。該閘極驅動電路包含一反相 裔電路一電阻以及-電容。該反相器電路具有—輸人端用來接收 一控制電壓，以及—輸出端用來輸出-輸出電壓，該反相器電路將 該控制電壓反相以產生雜出電壓。該電_來接收該輸入電壓， h電阻〇 $第電性連接於該輸人端；以及—第二端電性連接 於供應電源β亥電谷用來延遲該控制電壓之改變，該電容包含一 第-端電性連接於該反相器電路之輸人端；以及—第二端電性連接 於-供應電源。該靜電放電電晶體包含―第—端電性連接於該輸入 端二第二端電性連接於該供應電源；以及—控制端電性連接於該 反相益電路之輸出端，用來接輯輪出電壓，並根據該輸 制從該靜電放電電晶體H流顺靜電放電電晶體之第二叙 電流之導通。該傳遞電晶體包含端電性連接於其中—快化己 ，區塊；-第二端電性連接於該輪入端；一控制端電 相器電路之輸出端，_收—並根據該輸―t 從_遞電晶體之第1流到該傳遞電晶體之第二端之電流 ^以及-井端電性連接來於藉 靜電放電時使該傳遞電晶體保持關閉。 翰入鳊 ^另提供一 __電路’包含複數個快閃記憶區 塊、-輸人端一_‘㈣、—靜電放電電晶體以及 晶體。該輸入端用來接收-輸入電聲。該閘極驅動電路包含—反相 201117216 器電路…厂電阻一第二電阻以及—電容。該反相器電路 一輸入端用來接收-控制賴，以及一輸出端用來輸出一輪出電 壓，該反細電路將該控制電壓反相以產生該輸出電壓。 阻用來接收該輸入電壓，該第一電阻包含—第一端電性連接於^ :端;：及:第二端。該第二電阻包含-第-端電性連接於；: 電阻之第=，以及-第二端電性連接於該反相器電路之輸入端。 魏制纽翻柳輕之轉，輯容&含 於該反相器電路之輸入端;以及-第二端電性連接於一供應= 該靜電放電電簡含 =接=供應電源’ ·以及—控制端電性連接於該反相器電路之輸 知，用來接收該輸出電壓’並根據該輸出電壓控制從該靜電放電 =之第-端流到該靜電放電電晶體之第二端之電流= 體包含一第一端電性連接於其中一快閃記憶區塊;一第二 :=ΓΓ輸入端;一控制端電性連接於該反相器電路之輸出 之第一 1 ώ收雄出電壓’並根據該輸㈣壓控制從該傳遞電晶體 =一W到該傳遞電晶體之第二端之電流《導通；以及一井端電 遞電赠樹時使該傳 地、tr月另提供一種快閃記憶體電路，包含複數個快閃記憶區 1。二端㈤極驅動電路、—靜電放電電晶體以及-傳遞電 第二電阻以及一第二電容 器雷跋〜认端用來接收—輸人錢。制極驅動電路包含一反相 峪、—第一電阻、一第一電容、— 201117216 該反相器電路具有一輸入端用來接收一控制電壓，以及一輸出端用 來輸出一輸出電壓，該反相器電路將該控制電壓反相以產生該輪出 電壓。該第一電阻用來接收該輸入電壓，該第一電阻包含一第一端 電性連接於該輸入端；以及一第二端電性連接於該反相器電路之輸 入端。該第一電容用來延遲該控制電壓之改變 第一端電性連接於該反相器電路之輸入端；以及一第二端電性連接 於-供應電源。該第二電阻用來接收該輸入電壓，該第二電阻包含 一第-端紐連接於該輸人端；以及—第二端用來輸出—井控制電 壓。該第二電容用來延遲該井控制電壓之改變，該第二電容包含一 第一端電性連接於該第二電阻之第二端；以及—第二端電性連二於 祕應電源。該靜電放電電晶體包含―第—端電性連接於該輸入 端^第二端電性連接於該供應電源；以及一控制端電性連^於該 出端，用來接收該輸罐，並根據該輪出電壓控 淑雜電放電電晶體之第一端流到該靜電放電電晶體 =導通第該傳遞電晶體包含一第一端電性連接於其中讀 相器電路之輸出端，用來接收 :連接於3亥反 從該傳遞電晶，雜翁輸出獅制 # ^观到轉遞電晶體之第 通；以及-井端電性連接於該第二電阻之 入端靜電放電時使該傳遞電晶體保持關閉。來於糟由該輸 【實施方式】 201117216 清參考第3圖’第3圖為具有靜電放電保護之快閃記憶體電路 30之第-實施例之示意圖。快閃記憶體電路3()包含複數個快閃記 憶區塊300、輸入端VPPJ>AD絲接收輸入電壓γρρ、閘極驅動 電路310、靜電放電電晶體M—ESD以及傳遞電晶體33〇。閑極驅動 電路310包含反相器電路311、電阻R以及電容NC，如金屬氧化半 導體(MOS)電容。反相器電路311包含節點μ之輸入端用來接收控 制電壓’以及節點G1之輸出端用來輸出輸出電壓。反相器電路m 籲將控制電壓反相以產生輸出電壓。例如，若節點⑺之電麼為高壓， 節點G1之電壓為低壓，反之亦然。反相器電路311包含第一電晶 體MP以及第二電晶體讀。第一電晶體Mp包含第一端，如沒極， 第二端’如源極，電性連接於輸入端wpj>AD，以及控制端，如開 極第-電晶體MP之控制端用來根據控制電壓控制從第一電晶體 之第到第電曰曰體之第二端之電流之導通。第二電晶體祕^ 包含第-端’如:¾極，電性連接於第—電晶體之第—端，用來輸出 輸出電壓’第二端’如源極，電性連接於供應電源娜，以及控制 &如閘極電性連接於第一電晶體之控制端。第二電晶體_之 控制端用來根據控制電壓控制從第二電晶體之第一端流到第二電晶 體之第二端之電流之導通。電阻R用來接收輸入電壓vpp，電阻r 之第-端電性連接於輸人端VPP_PAD以接收輸人㈣營，電阻 R之第二端電性連接於節點G2之反相器電路3ιι之輸入端。電容 NC用來延遲控制電壓之改變，電容NC之第一端電性連接於節點 G2之反相器電路311之輸入端，電容NC之第二端電性連接於供應 電源VSS ’供應電源vss可為低電壓源或地端。靜電放電電晶體 201117216 Μ—ESD包含第一端電性連接於輸入端Vpp—PAD ,第二端電性連接 於供應電源VSS，以及控制端電性連接於節點G1之反相器電路311 之輸出端以接收輸出電壓。靜電放電電晶體M—ESD之控制端根據 輸出電壓控制從靜電放電電晶體Μ一ESD之第一端流到靜電放電電 曰曰體Μ一ESD之第二端之電流之導通。靜電放電電晶體M—ESD之 第一端為汲極，靜電放電電晶體Μ一ESD之第二端為源極。傳遞電 晶體330包含第一端電性連接於其中一快閃記憶區塊3〇〇，第二端 電性連接於輸入端VPP_PAD，以及控制端電性連接於節點G1之反 相器電路311之輸出端以接收輸出電壓。傳遞電晶體33〇之控制端 根據輸出電壓控制從傳遞電晶體33〇之第一端流到傳遞電晶體33〇 之第二端之電流之導通。傳遞電晶體330之第一端為汲極，傳遞電 曰曰體330之第二端為源極’傳遞電晶體330之井端電性連接於節點 G2之電阻R之第二端以於藉由輸入端靜電放電時使傳遞電晶體33〇 保持關閉。傳遞電晶體330為PMOS電晶體，靜電放電電晶體 MJESD為NMOS電晶體。 在第3圖之快閃記憶體電路30中，當靜電放電的破壞發生時， 靜電放電電荷藉由輸入端VPP_PAD進入快閃記憶體電路3〇，靜電 放電電荷可藉由靜電放電電晶體MjgSD放電。當靜電放電電荷進 入快閃記憶體電路30時，由於電容NC的電壓耦合，造成節點g2 之電壓為低壓’節點G1之電壓因反相ϋ電路311為高壓，而節點 G1之咼電壓位準將造成靜電放電電晶導通，使得靜電放 電電荷藉由靜電放電電晶體M—ESD流到供應電源vss。在第一實 201117216 施例中’因為傳遞電晶體330之井端電性連接於節點G2之電容nc 之第-端’且節點G2之電壓初始時為低壓，所以當靜電放電電晶 體M-ESD將靜電放電電荷引導到供應電源VSS時，傳遞電晶體330 將完全被關閉。因此，可避免靜電放電電荷進入快閃記憶區塊3〇〇。 «^考第4 ® ’第4圖為具有靜電放電保護之快閃記憶體電路 4〇之第一實施例之不意圖。快閃記憶體電路4〇包含複數個快閃記 _ L區塊400、輸入端Vpp—PAD用來接收輸入電壓㈣、閘極驅動 電路4io、靜電放電電晶體M—ESD以及傳遞電晶體㈣。閘極驅動 =路410包含反相器電路如、第一電阻幻、第二電阻幻以及電 >^NC如金屬氧化半導體(M〇s)電容。反相器電路“I包含節點 G2之輸入端用來接收控制電壓’以及節點以之輸出端用來輸出輸 出電壓。反相器電路411將控制電壓反相以產生輸出電壓。例如， 2節點G2之電壓為高壓’節點⑴之電壓為低壓，反之亦然。反相 裔電路411包含第—電晶體Mp以及第二電晶體贿。第一電晶體 MP匕3第一端，如汲極，第二端’如源極，電性連接於輸入端 VPP—PAD ’以及控制端’如閘極。第一電晶體之控綱用來根 據控制電®控制從第一電晶體之第一端流到第-電晶體之第二端之 二，導通。第二電晶體MN包含第一端’如祕，電性連接於第 一電晶體之第一端，用來輸出輪出電壓，第二端，如源極，電性連 接於供f電源VSS，以及控制端，如閘極’電性連接於第一電晶體 之^制端。第二電晶體丽之控制端用來根據控制健控制從第二 電曰曰體之苐—端流到第二電晶體之第二端之電流之導通。第二電阻 201117216 R2用來接收輸入電壓VPP，第二電阻R2之第一端電性連接於輪入 端VPP一PAD以接收輸入電壓VPP，第二電阻幻之第二端電性^接 於第-電阻R1之第-端。第-電阻R1之第二端電性連接於節點 G2之反相器電路411之輸入端。在本實施例中，第一電阻尺丨與第 一電阻R2為串聯。電容NC用來延遲控制電壓之改變，電容之 第一端電性連接於節‘點G2之反相器電路411之輸人端，電容NC 之第二端電性連接於供應電源vss，供應魏vss可為低電壓源或 地端。靜電放電電_M_ESD包含第—端電性連接於輸入端 VPP—PAD ’第二職性連接於供應電源vss，以及控制端電性連接 於節點G1之反相器電路411之輸出端以接收輸出電壓1電放電 電晶體M_ESD之控制端根據輸出電壓控繼靜電放電電晶體 M_ESD之第-端流到靜電放電電晶體M—ESD之第二端之電流之導 通。靜電放钱MM_ESD之第—端域極，靜電放電電晶體 M_ESD之第二端為祕。傳遞電晶體包含第—端電性連接於其 中决閃5己憶區塊4〇〇，第二端電性連接於輸入端vpp—PAD，以及 控制端電性連接於節點⑴之反相器電路411之輸出端以接收輸出 電[傳遞電曰曰體43〇之控制端根據輸出電壓控制從傳遞電晶體柳 之第-端流到傳遞電晶體43〇之第二端之電流之導通。傳遞電晶體 430之第端為及極，傳遞電晶體43〇之第二端為源極，傳遞電晶 體:3〇之井端電性連接於第二電阻幻節點〇2之電阻r之第二端以 於藉由輸人端靜f放電餐傳遞電晶體·保持關。傳遞電晶體 430為PMOS電晶體’靜電放電電晶體μ ESD為NM〇s電晶體。 201117216 _ _記憶體電路30、4〇之操作，如第3圖與第4圖所示，靜電 •放電=何仃經傳遞電晶體330、430之第二端到傳遞電晶體33〇、43〇 $井端，再回朗節點G2。回制節點①之靜電放電電荷將對電 夺NC充電，造成反相器電路、扣之輸出電壓在所有靜電放電 電荷消散之前將傳遞電晶體33〇、43ύ導通。為了減輕這種情形的影 響，傳遞電晶體430之井端μ接電性連接於節點G2，而是藉由第 “電阻R1 f;性連接於節點G2，如此可延遲靜電放電電荷藉由傳遞 •電晶體43〇回流之效應，使靜電放電電晶體Μ一ESD有更多的時間 將靜電放電電荷消散到供應電源vss。 請參考第5圖’第5圖為具有靜電放電保護之快閃記憶體電路 50之第三實施例之示意圖。快閃記憶體電路5〇包含複數個快閃記 憶區塊500、輸入端VPP—PAD用來接收輸入電壓vpp、閘極驅動 電路510、靜電放電電晶體M—ESD以及傳遞電晶體53〇。閑極驅動 電路510包含反相器電路511、第一電阻ri、第二電阻R2，如金屬 籲氧化半導體(MOS)電容、第一電容船以及第二電容NC2，如金屬 氧化半導體電容。反相器電路511包含節點G2之輸入端用來接收 控制電壓，以及節點G1之輸出端用來輸出輸出電壓。反相器電路 511將控制電壓反相以產生輸出電壓。例如，若節點〇2之電壓為高 壓，節點G1之電壓為低壓，反之亦然。反相器電路511包含第一 電晶體MP以及第二電晶體]VTN。第一電晶體]y[p包含第一端，如 .汲極’第二端，如源極，電性連接於輸入端VPPj>AD，以及控制端， 如閘極。第一電晶體MP之控制端用來根據控制電壓控制從第一電 201117216 日日體之第一端流到第-電晶體之第二端之電流之導通。第二電晶體 二H含第—端，如及極，電性連接於第—電晶體之第一端，用來 輸出輸出電壓，第二端，如源極，·連接於供應電源娜，以及 控㈣’如_ ’電性連接於第1晶體之控制端。第二電晶體 謂^控制_練據㈣控恤第二電雜之第-端流到第 。曰曰體之第—端之電流之導通。第—電阻R1用來接收輸入電壓 VPP第-電阻R1之第—端電性連接於輸人端以接收輸 入電壓VPP ’第—電阻R1之第：端電性連接於節點g2之反相器電 路犯之輸人端。第-電容⑽肖來延遲控制電壓之改變，第一電 2 NC1之第一端電性連接於節點①之反相器電路511之輸入端， 電谷NC1之第二端電性連接於供應電源娜，供應電源娜 :為低電壓源或地端。靜電放電電晶體m—esd包含第—端電性連 :輸入端VPP一PAD ’第二端電性連胁供應電源vss，以及控 “端，f生連接於即點G1之反相器電路如之輸出端以接收輸出電 垂靜電放電電曰曰體M—ESD之控制端根據輸出電壓控制從靜電放 電曰曰體M_ESD之第一端流到靜電放電電晶體m—esd之第二端 之導通。靜電放電電晶體M—ESD之第—端為祕，靜電放 =電曰aMM_ESD之第二端為源極。傳遞電晶體wo包含第一端電 ^連接於其中-快閃記憶區塊·，第二端電性連接於輸入端 二—PAD，以及控制端電性連接於節點G1之反相器電路如之輸 /出端以接收輸出電麗。傳遞電晶體别之控制端根據輸出電壓控制 從傳遞電晶體530之第一端流到傳遞電晶體53〇之第二端之電流之 導通。傳遞電晶體53〇之第一端為汲極，傳遞電晶體別之第二端 201117216 為源極。傳遞電晶體53〇為PMOS電晶體，靜電放電電晶體M—咖 為NMOS電晶體。 ~ 在第三實施例中，如第5圖所示，傳遞電晶體530之井端電性 連接於節點G3之包含第二電阻R2以及第二電容NC2之獨立電阻 電容(RC)電路，以於藉由輸人端VPP_PAD靜電放f時使傳遞電晶 體530保持關閉。帛=tP&R2 VPP，第二電阻 鲁R2之第知電性連接於輸入端VPP—PAD以接收輸入電壓vpp，第 一電阻R2之第二端輸出井控制電壓至節點〇3。第二電用來 延遲井控制電壓之改變，第二電容NC2之第-端電性連接於節點 G3之第二電阻R2之第二端，第二電容赠之第二端電性連接於供 應電源VSS。不同於第一實施例以及第二實施例，快閃記憶體電路 50利用第二電阻112以及第二電容NC2來控制傳遞電晶體53〇之井 端之電壓上升之時間長度。因此，在靜電放電破壞期間，傳遞電晶 體530可被完全關閉。 相較於先前技術，在本發明之實施例中，快閃記憶體電路邓、 40、50之傳遞電晶體33〇、430、530之井端電性連接於節點G2或 節點G3，使得傳遞電晶體330、43〇、53〇在靜電放電破壞期間被1 全關閉。如此，提供了快閃記憶區塊3〇〇、4〇〇、5〇〇更佳的保嗲儿 以上所述僅為本發明之較佳實施例，凡依本發明申請專利纩 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 圍 15 201117216 【圖式簡單說明】 第1圖為快閃記憶體電路之示意圖。 第2圖為第1圖之快閃記憶體電路之靜電放電之示意圖。 第3圖為具有靜電放電保護之快閃記憶體電路之第一實施例之示意 圖。 第4圖為具有靜電放電保護之快閃記憶體電路之第二實施例之示意 圖。 第5圖為具有靜電放電保護之快閃記憶體電路之第三實施例之示意 圖。 【主要元件符號說明】 10、30、40、50 快閃記憶體電路 100、300、400、500 快閃記憶區塊 110、310、410、510 閘極驅動電路 311 ' 411 ' 511 反相器電路 130、330、430、530 傳遞電晶體 Gl ' G2 > G3 節點 MP ' MN 電晶體 R > Rl ' R2 電阻 NC ' NCI ' NC2 電容 201117216 M_ESD 靜電放電電晶體 VPPPAD 輸入端 * VPP 輸入電壓 vss 供應電源 17The electrostatic discharge charge will enter the flash memory block (10). This is because the transfer room (10) K is caused by the fact that the N-well voltage is higher than the node (1) (the base of the transfer gate (10) directly receives the surface that is known to be applied to the input terminal VPPJ> AD). SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a memory circuit. 201117216 The present invention provides a flash memory circuit comprising a plurality of flash memory blocks, an input terminal, a gate drive circuit, an electrostatic discharge transistor, and a transfer electric solar cell. The 5th input is used to receive the wheel-in voltage. The gate drive circuit includes an inverting circuit-resistor and a capacitor. The inverter circuit has an input terminal for receiving a control voltage and an output terminal for outputting an output voltage, and the inverter circuit inverts the control voltage to generate a mixed voltage. The electric_to receive the input voltage, the h-resistance 〇$ is electrically connected to the input end; and the second end is electrically connected to the supply power source to delay the change of the control voltage, the capacitor includes An first end is electrically connected to the input end of the inverter circuit; and a second end is electrically connected to the - supply power source. The electrostatic discharge transistor includes a first end electrically connected to the input end, and a second end electrically connected to the supply power source; and a control end electrically connected to the output end of the reverse phase benefit circuit for receiving The voltage is turned on, and the second current of the electrostatic discharge transistor is turned on from the electrostatic discharge transistor H according to the transmission. The transfer transistor includes a terminal electrically connected thereto - a fastening block, a block; - a second end electrically connected to the wheel end; a control end of the output phase of the phase circuit, _ receiving - and according to the input ―t The current from the first flow of the _transistor to the second end of the transfer transistor and the well end are electrically connected to keep the transfer transistor closed when electrostatic discharge is applied. John 鳊 ^ Another __ circuit' contains a plurality of flash memory blocks, - input terminal _ ' (four), - electrostatic discharge transistors and crystals. This input is used to receive-input electroacoustic. The gate drive circuit includes - an inverting 201117216 circuit... a factory resistor, a second resistor, and a capacitor. An input of the inverter circuit is used to receive-control, and an output is used to output a round of output voltage, and the inverse circuit inverts the control voltage to generate the output voltage. The resistor is configured to receive the input voltage, and the first resistor includes: the first end is electrically connected to the ^: end; and: the second end. The second resistor includes a first terminal electrically coupled to: a third of the resistor, and a second terminal electrically coupled to the input of the inverter circuit. The Wei system is turned into a light turn, and the volume & is included in the input end of the inverter circuit; and - the second end is electrically connected to a supply = the electrostatic discharge is included = connection = supply power ' The control terminal is electrically connected to the input of the inverter circuit for receiving the output voltage 'and according to the output voltage control to flow from the first end of the electrostatic discharge to the second end of the electrostatic discharge transistor The current = body includes a first end electrically connected to one of the flash memory blocks; a second: = ΓΓ input terminal; and a control terminal electrically connected to the first output of the inverter circuit Output voltage 'and according to the input (four) voltage control from the transfer transistor = a W to the second end of the transfer transistor "conduction; and a well end of the teleelectric gift tree to make the land, tr month provide A flash memory circuit comprising a plurality of flash memory areas 1. Two-terminal (five) pole drive circuit, - electrostatic discharge transistor and - transfer electric second resistor and a second capacitor Thunder ~ recognize end for receiving - input money. The pole drive circuit includes an inverting turn, a first resistor, a first capacitor, and a circuit of the inverter circuit having an input terminal for receiving a control voltage and an output terminal for outputting an output voltage. An inverter circuit inverts the control voltage to generate the turn-off voltage. The first resistor is configured to receive the input voltage, the first resistor includes a first end electrically connected to the input end, and a second end electrically connected to the input end of the inverter circuit. The first capacitor is configured to delay the change of the control voltage. The first end is electrically connected to the input end of the inverter circuit; and the second end is electrically connected to the - supply power source. The second resistor is for receiving the input voltage, the second resistor includes a first terminal connected to the input terminal, and - the second terminal is for outputting a well control voltage. The second capacitor is configured to delay the change of the control voltage of the well. The second capacitor includes a first end electrically connected to the second end of the second resistor; and - the second end is electrically connected to the secret power source. The electrostatic discharge transistor includes a first end electrically connected to the input end, a second end electrically connected to the supply power source, and a control end electrically connected to the output end for receiving the transfer tank, and According to the first end of the turn-off voltage control electric discharge transistor, the electro-discharge transistor is turned on. The transfer transistor includes a first end electrically connected to the output end of the phase-reader circuit, and is used for Receiving: connected to the 3H reverse from the transfer electron crystal, the miscellaneous output of the lion system ^ ^ view to the first pass of the transfer transistor; and - the well end is electrically connected to the second end of the second resistor when the electrostatic discharge is made The transistor remains closed. The present invention is a schematic diagram of a first embodiment of a flash memory circuit 30 having electrostatic discharge protection. The flash memory circuit 3() includes a plurality of flash memory blocks 300, an input terminal VPPJ> an AD wire receiving input voltage γρρ, a gate driving circuit 310, an electrostatic discharge transistor M-ESD, and a transfer transistor 33A. The idler driving circuit 310 includes an inverter circuit 311, a resistor R, and a capacitor NC such as a metal oxide semiconductor (MOS) capacitor. The inverter circuit 311 includes an input terminal of the node μ for receiving the control voltage ' and an output terminal of the node G1 for outputting the output voltage. The inverter circuit m calls for inverting the control voltage to produce an output voltage. For example, if the node (7) is powered high, the voltage at node G1 is low and vice versa. The inverter circuit 311 includes a first electromorph MP and a second transistor read. The first transistor Mp includes a first end, such as a poleless end, a second end 'such as a source, electrically connected to the input terminal wpj> AD, and a control terminal, such as a control terminal of the open-pole transistor 102, for The control voltage controls conduction of current from the first transistor to the second terminal of the first body. The second transistor includes a first end, such as a 3⁄4 pole, electrically connected to the first end of the first transistor, and is used to output an output voltage 'second end' such as a source, electrically connected to the supply source And a control & such as a gate electrically connected to the control end of the first transistor. The control terminal of the second transistor _ is used to control the conduction of current from the first end of the second transistor to the second end of the second transistor according to the control voltage. The resistor R is used to receive the input voltage vpp, the first end of the resistor r is electrically connected to the input terminal VPP_PAD to receive the input (four) battalion, and the second end of the resistor R is electrically connected to the input of the inverter circuit 3 ιι of the node G2. end. The capacitor NC is used to delay the change of the control voltage. The first end of the capacitor NC is electrically connected to the input end of the inverter circuit 311 of the node G2, and the second end of the capacitor NC is electrically connected to the power supply VSS 'supply power vss. It is a low voltage source or ground. Electrostatic discharge transistor 201117216 Μ-ESD includes a first end electrically connected to the input terminal Vpp-PAD, a second end electrically connected to the supply power source VSS, and a control terminal electrically connected to the output of the inverter circuit 311 of the node G1. The terminal receives the output voltage. The control terminal of the ESD transistor M-ESD controls the conduction of current from the first end of the ESD transistor ESD to the second end of the ESD body and an ESD according to the output voltage. The first end of the electrostatic discharge transistor M-ESD is a drain, and the second end of the electrostatic discharge transistor Μ-ESD is a source. The transfer transistor 330 includes a first end electrically connected to one of the flash memory blocks 3, a second end electrically connected to the input terminal VPP_PAD, and a control terminal electrically connected to the inverter circuit 311 of the node G1. The output receives the output voltage. The control terminal of the transfer transistor 33 is controlled to conduct current from the first end of the transfer transistor 33A to the second end of the transfer transistor 33A in accordance with the output voltage. The first end of the transfer transistor 330 is a drain, and the second end of the transfer transistor 330 is a source end. The well end of the transfer transistor 330 is electrically connected to the second end of the resistor R of the node G2 for input. The transfer transistor 33A is kept closed when the terminal is electrostatically discharged. The transfer transistor 330 is a PMOS transistor, and the electrostatic discharge transistor MJESD is an NMOS transistor. In the flash memory circuit 30 of FIG. 3, when the destruction of the electrostatic discharge occurs, the electrostatic discharge charge enters the flash memory circuit 3 through the input terminal VPP_PAD, and the electrostatic discharge charge can be discharged by the electrostatic discharge transistor MjgSD. . When the electrostatic discharge charge enters the flash memory circuit 30, the voltage of the node g2 is low due to the voltage coupling of the capacitor NC. The voltage of the node G1 is high due to the inversion circuit 311, and the voltage level of the node G1 is caused. The electrostatic discharge cell is turned on, so that the electrostatic discharge charge flows to the power supply vss through the electrostatic discharge transistor M-ESD. In the first real 201117216 embodiment, 'because the well end of the transfer transistor 330 is electrically connected to the first end of the capacitor nc of the node G2' and the voltage of the node G2 is initially low voltage, when the electrostatic discharge transistor M-ESD will When the electrostatic discharge charge is directed to the supply power source VSS, the transfer transistor 330 will be completely turned off. Therefore, it is possible to prevent the electrostatic discharge charge from entering the flash memory block 3〇〇. «^第第4 ®' Fig. 4 is a schematic view of the first embodiment of the flash memory circuit with electrostatic discharge protection. The flash memory circuit 4 includes a plurality of flash blocks _ L block 400, and an input terminal Vpp-PAD for receiving an input voltage (4), a gate driving circuit 4io, an electrostatic discharge transistor M-ESD, and a transfer transistor (4). Gate Drive = Channel 410 contains an inverter circuit such as a first resistor phantom, a second resistor phantom, and an electrical > ^NC such as a metal oxide semiconductor (M〇s) capacitor. The inverter circuit "I includes the input of the node G2 for receiving the control voltage" and the node for outputting the output voltage. The inverter circuit 411 inverts the control voltage to generate an output voltage. For example, 2-node G2 The voltage is high voltage 'the voltage of the node (1) is low voltage, and vice versa. The reverse-phase circuit 411 includes the first transistor Mp and the second transistor bribe. The first transistor MP匕3 first end, such as the bungee, the first The two ends 'such as a source, electrically connected to the input terminal VPP-PAD 'and the control terminal 'such as a gate. The first transistor is used to control the flow from the first end of the first transistor to the control according to the control The second end of the second transistor is turned on. The second transistor MN includes a first end, such as a secret, electrically connected to the first end of the first transistor for outputting the wheel voltage, and the second end, For example, the source is electrically connected to the power supply VSS, and the control terminal, such as the gate, is electrically connected to the first transistor. The second transistor is controlled by the control terminal. The second electrical body - the current flowing to the second end of the second transistor The second resistor 201117216 R2 is used for receiving the input voltage VPP, the first end of the second resistor R2 is electrically connected to the wheel end VPP-PAD to receive the input voltage VPP, and the second end of the second resistor is electrically connected. The first end of the first resistor R1 is electrically connected to the input end of the inverter circuit 411 of the node G2. In this embodiment, the first resistor 丨 and the first resistor R2 The capacitor is used to delay the change of the control voltage. The first end of the capacitor is electrically connected to the input end of the inverter circuit 411 of the node G2, and the second end of the capacitor NC is electrically connected to the power supply vss. The supply of Wei vss can be a low voltage source or ground. The electrostatic discharge _M_ESD includes the first end electrically connected to the input terminal VPP-PAD 'the second job is connected to the supply power vss, and the control terminal is electrically connected to the node The output end of the inverter circuit 411 of G1 receives the output voltage. The control terminal of the electric discharge transistor M_ESD flows to the second end of the electrostatic discharge transistor M_ESD according to the output voltage. The conduction of the current. The static discharge money MM_ESD of the first end domain The second end of the electrostatic discharge transistor M_ESD is secret. The transfer transistor includes a first end electrically connected to the flashover 5 memory block 4〇〇, and the second end is electrically connected to the input end vpp-PAD, and The control terminal is electrically connected to the output end of the inverter circuit 411 of the node (1) to receive the output power. [The control terminal of the transfer transistor 43 is controlled according to the output voltage to flow from the first end of the transfer transistor to the transfer transistor. The current of the second end of the 43 〇 is turned on. The first end of the transfer transistor 430 is the sum pole, the second end of the transfer transistor 43 is the source, and the transfer transistor: the well end of the 3 电 is electrically connected to the second resistor The second end of the resistor r of the magic node 以2 is used to transfer the transistor by the input terminal to discharge the transistor. The transfer transistor 430 is a PMOS transistor. The electrostatic discharge transistor μ ESD is an NM〇s transistor. 201117216 _ _ Memory circuit 30, 4 〇 operation, as shown in Figures 3 and 4, static electricity / discharge = 仃 pass the second end of the transistor 330, 430 to the transfer transistor 33 〇, 43 〇 $ well, then return to the node G2. The electrostatic discharge charge of the node 1 will charge the battery, causing the output voltage of the inverter circuit and the buckle to conduct the transistors 33, 43 之前 before all the electrostatic discharge charges are dissipated. In order to alleviate the influence of this situation, the well terminal μ of the transfer transistor 430 is electrically connected to the node G2, but is connected to the node G2 by the first resistor R1 f; so that the electrostatic discharge charge can be delayed by transmitting The effect of the 43 〇 reflow of the crystal causes the ESD transistor ESD to have more time to dissipate the ESD charge to the supply power vss. Please refer to Figure 5 'Figure 5 for the flash memory circuit with ESD protection. A schematic diagram of a third embodiment of the flash memory circuit 5 includes a plurality of flash memory blocks 500, and an input terminal VPP-PAD for receiving an input voltage vpp, a gate driving circuit 510, and an electrostatic discharge transistor M- The ESD and the transfer transistor 53. The idle driving circuit 510 includes an inverter circuit 511, a first resistor ri, and a second resistor R2, such as a metal oxide semiconductor (MOS) capacitor, a first capacitor boat, and a second capacitor NC2. For example, the metal oxide semiconductor capacitor. The inverter circuit 511 includes an input terminal of the node G2 for receiving the control voltage, and an output terminal of the node G1 for outputting the output voltage. The inverter circuit 511 inverts the control voltage. To generate an output voltage, for example, if the voltage at node 〇2 is high, the voltage at node G1 is low, and vice versa. Inverter circuit 511 includes first transistor MP and second transistor VTN. ]y[p includes a first end, such as a second end of the drain, such as a source, electrically connected to the input terminal VPPj > AD, and a control terminal, such as a gate. The control terminal of the first transistor MP is used Controlling the conduction of current from the first end of the first body 201117216 to the second end of the first transistor according to the control voltage. The second transistor IIH has a first end, such as a pole, electrically connected to The first end of the first transistor is used to output the output voltage, the second end, such as the source, is connected to the supply source, and the control (four) 'such as _' is electrically connected to the control end of the first crystal. The transistor is called ^ control_practice (4) the second end of the second electrician of the shirt is turned to the first. The current of the first end of the body is turned on. The first resistor R1 is used to receive the input voltage VPP first-resistor R1 The first end is electrically connected to the input end to receive the input voltage VPP 'the first end of the resistor R1: the end is electrically connected to the section The inverter circuit of g2 is committed to the input end. The first capacitor (10) delays the change of the control voltage, and the first end of the first electric 2 NC1 is electrically connected to the input end of the inverter circuit 511 of the node 1, the electric The second end of the valley NC1 is electrically connected to the supply source Na, and the supply source is: a low voltage source or a ground. The electrostatic discharge transistor m-esd includes a first end electrical connection: an input terminal VPP-PAD 'second end The power supply is connected to the power supply vss, and the control terminal is connected to the inverter circuit of the point G1, such as the output terminal to receive the output. The control terminal of the electrostatic discharge electric discharge body M-ESD is controlled according to the output voltage. The first end of the electrostatic discharge body M_ESD flows to the second end of the electrostatic discharge transistor m-esd. The first end of the electrostatic discharge transistor M-ESD is secret, and the second end of the electrostatic discharge = aMM_ESD is the source. The transfer transistor wo includes a first end electrically connected to the flash memory block, a second end electrically connected to the input terminal two-PAD, and an inverter circuit electrically connected to the node G1 at the control terminal. The input/output terminal receives the output battery. The control transistor of the transfer transistor controls the conduction of current from the first end of the transfer transistor 530 to the second end of the transfer transistor 53 according to the output voltage. The first end of the transfer transistor 53 is a drain, and the second end of the transfer transistor is 201117216. The transfer transistor 53 is a PMOS transistor, and the electrostatic discharge transistor M is an NMOS transistor. In the third embodiment, as shown in FIG. 5, the well end of the transfer transistor 530 is electrically connected to the independent resistor-capacitor (RC) circuit of the node G3 including the second resistor R2 and the second capacitor NC2. The transfer transistor 530 is kept off when the input terminal VPP_PAD is electrostatically discharged.帛=tP&R2 VPP, the second resistor Lu R2 is electrically connected to the input terminal VPP-PAD to receive the input voltage vpp, and the second terminal of the first resistor R2 outputs the well control voltage to the node 〇3. The second power is used to delay the change of the well control voltage. The second end of the second capacitor NC2 is electrically connected to the second end of the second resistor R2 of the node G3, and the second end of the second capacitor is electrically connected to the power supply. VSS. Unlike the first embodiment and the second embodiment, the flash memory circuit 50 utilizes the second resistor 112 and the second capacitor NC2 to control the length of time during which the voltage at the well terminal of the transfer transistor 53 is raised. Therefore, during the electrostatic discharge destruction, the transfer electron crystal 530 can be completely turned off. Compared with the prior art, in the embodiment of the present invention, the well ends of the transfer transistors 33, 430, 530 of the flash memory circuit Deng, 40, 50 are electrically connected to the node G2 or the node G3, so that the transistor is transferred. 330, 43〇, 53〇 are fully turned off during the destruction of the electrostatic discharge. Thus, the provision of the flash memory blocks 3, 4, 5, and 5 is better. The above is only a preferred embodiment of the present invention, and the equalization of the patent application according to the present invention. Variations and modifications are intended to be within the scope of the invention. Wai 15 201117216 [Simple description of the diagram] Figure 1 is a schematic diagram of the flash memory circuit. Figure 2 is a schematic diagram of the electrostatic discharge of the flash memory circuit of Figure 1. Figure 3 is a schematic illustration of a first embodiment of a flash memory circuit with electrostatic discharge protection. Figure 4 is a schematic illustration of a second embodiment of a flash memory circuit with electrostatic discharge protection. Fig. 5 is a schematic view showing a third embodiment of a flash memory circuit having electrostatic discharge protection. [Main component symbol description] 10, 30, 40, 50 Flash memory circuit 100, 300, 400, 500 Flash memory block 110, 310, 410, 510 Gate drive circuit 311 '411 ' 511 Inverter circuit 130, 330, 430, 530 transfer transistor Gl ' G2 > G3 node MP ' MN transistor R > Rl ' R2 resistor NC ' NCI ' NC2 capacitor 201117216 M_ESD electrostatic discharge transistor VPPPAD input * VPP input voltage vss supply Power supply 17