CN111933638B - 静电放电电路 - Google Patents

静电放电电路 Download PDF

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CN111933638B
CN111933638B CN202010310590.3A CN202010310590A CN111933638B CN 111933638 B CN111933638 B CN 111933638B CN 202010310590 A CN202010310590 A CN 202010310590A CN 111933638 B CN111933638 B CN 111933638B
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node
circuit
transistor
esd
main transistor
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CN111933638A (zh
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丁韵仁
赖致玮
吴易翰
林坤信
许信坤
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eMemory Technology Inc
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    • H—ELECTRICITY
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    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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Abstract

一种静电放电电路，连接于输出入垫与第一节点之间。该静电放电电路包括：双向降压电路、触发电路与放电电路。该双向降压电路包括顺向路径以及逆向路径连接于该输出入垫与第二节点之间。该触发电路连接于该第二节点与该第一节点之间。该放电电路连接于该第二节点与该第一节点之间，且该放电电路还连接至该触发电路。当该输出入垫接收负静电放电冲击时，静电放电电流由该第一节点经由该放电电路与该逆向路径流向该输出入垫。当该输出入垫接收正静电放电冲击时，该静电放电电流由该输出入垫经由该顺向路径与该放电电路流向该第一节点。

Description

静电放电电路
技术领域
本发明是有关于一种电路，且特别是有关于一种静电放电(electro staticdischarge，简称ESD)电路。
背景技术
众所周知，在互补式金属氧化物半导体的集成电路(CMOS IC)制程中，为增加其速度与整合度，半导体元件尺寸会越做越小、栅极氧化层(Gate oxide layer)会越来越薄。因此，栅极氧化层的崩溃电压(breakdown voltage)降低，且半导体元件的PN接面(PNjunction)的崩溃电压也降低。
为了避免集成电路(IC)在生产过程中被静电放电冲击(ESD zapping)所损伤，在集成电路(IC)内皆会制作ESD电路。ESD电路提供了静电放电电流路径(ESD currentpath)，以免静电放电流(ESD current)流入IC内部电路而造成损伤。
发明内容
本发明系有关于一种静电放电电路，连接于输出入垫与第一节点之间。该静电放电电路包括：双向降压电路，包括顺向路径连接于该输出入垫与第二节点之间，以及逆向路径连接于该输出入垫与该第二节点之间；触发电路，连接于该第二节点与该第一节点之间；以及放电电路，连接于该第二节点与该第一节点之间，其中该放电电路还连接至该触发电路；其中，当该输出入垫接收负静电放电冲击时，静电放电电流由该第一节点经由该放电电路与该逆向路径流向该输出入垫；以及当该输出入垫接收正静电放电冲击时，该静电放电电流由该输出入垫经由该顺向路径与该放电电路流向该第一节点。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附附图详细说明如下。
附图说明
图1所绘示为本发明静电放电电路的第一实施例。
图2A与图2B为第一实施例ESD电路接收到负静电放电冲击与正静电放电冲击的示意图。
图3所绘示为本发明静电放电电路的第二实施例。
图4A与图4B为第二实施例ESD电路接收到负静电放电冲击与正静电放电冲击的示意图。
图5所绘示为本发明静电放电电路的第三实施例。
图6所绘示为本发明静电放电电路的第四实施例。
图7所绘示为本发明静电放电电路的第五实施例。
具体实施方式
在非易失性存储器的编程动作或者抹除动作时，编程电压(program voltage)或者抹除电压(erase voltage)会供应至非易失性存储器中用以编程存储单元或者抹除存储单元。
通常，编程电压或者抹除电压都会超出半导体元件(semiconductor component)的耐压，也就是说超过栅极氧化层的崩溃电压或者超过半导体元件的PN接面的崩溃电压。因此，在ESD电路的设计上需要格外小心，以防止ESD电路中的半导体元件接收到的电压超过其崩溃电压而损坏。
请参照图1，其所绘示为本发明ESD电路的第一实施例。ESD电路100连接至内部电路140、输出入垫(Input/Output pad，I/O pad)150与节点g。内部电路140接收供应电压Vdd，且内部电路140连接于节点g。输出入垫150接收第一电压Vpp，节点g接收第二电压Vss。第一电压Vpp由输出入垫150输入ESD电路100与内部电路140。第二电压Vss由节点g输入ESD电路100与内部电路140。另外，第二电压Vss可为接地电压。
ESD电路100包括放电电路(discharge circuit)110与触发电路(triggercircuit)120。
触发电路120包括第一晶体管M1、第二晶体管M2、电阻R与电容器C。第一晶体管M1的第一端连接至输出入垫150，第一晶体管M1的第二端连接至节点a，第一晶体管M1的控制端连接至节点b。第二晶体管M2的第一端连接至节点a，第二晶体管M2的第二端连接至节点g，第二晶体管M2的控制端连接至节点b。电阻R的第一端连接至输出入垫150，电阻R的第二端连接至节点b。电容器C的第一端连接至节点b，电容器C的第二端连接至节点g。
另外，放电电路110包括主晶体管Ma，主晶体管Ma的第一端连接至输出入垫150，主晶体管Ma的第二端与体极端(body terminal)连接至节点g，主晶体管Ma的控制端连接至触发电路120中的节点a。另外，主晶体管Ma内部有寄生二极管(parasitic diode)Da。寄生二极管Da的阴极(cathode terminal)连接于主晶体管Ma的第一端，阳极(anode terminal)连接于主晶体管Ma的体极端(body terminal)。
根据本发明的第一实施例，ESD电路100中包括第一静电放电电流路径(first ESDcurrent discharge path)与第二静电放电电流路径(second ESD current dischargepath)。其中，主晶体管Ma的第二端、寄生二极管Da与主晶体管Ma的第一端组合成为第一静电放电电流路径。再者，主晶体管Ma的第一端、主晶体管Ma的通道区域(channel region)、主晶体管Ma的第二端组合成为第二静电放电电流路径。而触发电路120用来控制第二静电放电电流路径的开启与关闭。
当内部电路140接收第一电压Vpp而正常运作时，代表ESD电路100未接收到静电放电冲击(ESD zapping)。举例来说，第一电压Vpp为+6V。此时，寄生二极管Da为逆向偏压(reverse bias)，所以第一静电放电电流路径关闭。
另外，在触发电路120中，节点b的电压为第一电压Vpp，使得第二晶体管M2的控制端接收第一电压Vpp而开启。因此，主晶体管Ma的控制端接收第二电压Vss而关闭，也就是第二静电放电电流路径关闭。
换句话说，当输出入垫150接收+6V的第一电压Vpp时，代表ESD电路100未接收到静电放电冲击。此时，ESD电路100中的第一静电放电电流路径与第二静电放电电流路径都关闭。而内部电路140接收第一电压Vpp而正常运作。
请参照图2A，其所绘示为第一实施例ESD电路接收到负静电放电冲击(negativeESD zapping)的示意图。当输出入垫150接收到负静电放电冲击时，寄生二极管Da为顺向偏压(forward bias)，所以第一静电放电电流路径开启。因此，静电放电电流IESD由节点g经由寄生二极管Da流至输出入垫150。
请参照图2B，其所绘示为第一实施例ESD电路接收到正静电放电冲击(positiveESD zapping)的示意图。当输出入垫150接收到正静电放电冲击时，第一供应电压Vpp快速上升，电容器C暂时短路并使得第一晶体管M1的控制端接收第二电压Vss而开启。因此，主晶体管Ma控制端接收第一电压Vpp而开启，并使得第二静电放电电流路径开启。换句话说，当输出入垫150接收到正静电放电冲击时，触发电路120会开启第二静电放电电流路径，且静电放电电流IESD由输出入垫150经由主晶体管Ma流至节点g。
由以上的说明可知，当输出入垫150接收到静电放电冲击时，静电放电电流IESD会流经放电电路110而不会流经内部电路140，使得内部电路140受到ESD电路100的保护。
根据CMOS IC制造工艺的规范，当主晶体管Ma、第一晶体管M1与第二晶体管M2属于3.3V或者5V的半导体元件时，主晶体管Ma、第一晶体管M1与第二晶体管M2可以超压(overdrive)至7V仍能够正常运作。也就是说，半导体元件的栅极氧化层的崩溃电压或者PN接面的崩溃电压超过7V。换句话说，当第一电压为+6V时，利用3.3V或者5V的半导体元件所组成的ESD电路100能够正常的运作，并保护内部电路140。
然而，当主晶体管Ma、第一晶体管M1与第二晶体管M2属于1.8V的半导体元件时，这些半导体元件的栅极氧化层的崩溃电压或者PN接面的崩溃电压仅为4V。由于第一电压Vpp为+6V，如果利用1.8V的半导体元件来组成的ESD电路100，则这些1.8V的半导体元件将会损坏，ESD电路100将无法运作。
请参照图3，其所绘示为本发明ESD电路的第二实施例。相同地，ESD电路300连接至内部电路140、输出入垫350与节点g。内部电路140接收供应电压Vdd，且内部电路140连接于节点g。输出入垫350接收第一电压Vpp，节点g接收第二电压Vss。第一电压Vpp由输出入垫350输入ESD电路100与内部电路140。第二电压Vss由节点g输入ESD电路300与内部电路140。另外，第二电压Vss可为接地电压。
ESD电路300包括放电电路310、触发电路320与双向降压电路(bi-directionalbuck circuit)330。其中，ESD电路300中的半导体元件为1.8V的半导体元件。
触发电路320包括第一晶体管M1、第二晶体管M2、电阻R与电容器C。第一晶体管M1的第一端连接至节点d，第一晶体管M1的第二端连接至节点a，第一晶体管M1的控制端连接至节点b。第二晶体管M2的第一端连接至节点a，第二晶体管M2的第二端连接至节点g，第二晶体管M2的控制端连接至节点b。电阻R的第一端连接至节点d，电阻R的第二端连接至节点b。电容器C的第一端连接至节点b，电容器C的第二端连接至节点g。
放电电路310包括主晶体管Ma，主晶体管Ma的第一端连接至节点d，主晶体管Ma的第二端与体极端(body terminal)连接至节点g，主晶体管Ma的控制端连接至触发电路320中的节点a。另外，主晶体管Ma内部有寄生二极管(parasitic diode)Da。寄生二极管Da的阴极(cathode terminal)连接于主晶体管Ma的第一端，阳极(anode terminal)连接于主晶体管Ma的体极端(body terminal)。
双向降压电路330包括顺向路径(forward path)332与逆向路径(reverse path)334。顺向路径332包括n个二极管Df1～Dfn串接于输出入垫350与节点d之间，逆向路径334包括m个二极管Dr1～Drm串接于输出入垫350与节点d之间。其中，m与n为大于等于1的整数。
基本上，当第一电压Vpp大于节点d上的电压时，顺向路径332中的n个二极管Df1～Dfn皆为顺向偏压(forward bias)，顺向路径332的开启阈值电压(turn-on thresholdvoltage)为n×Von，其中Von为二极管的切入电压(cut in voltage)，例如0.7V。
根据本发明的第二实施例，ESD电路300中包括第一静电放电电流路径与第二静电放电电流路径。其中，主晶体管Ma的第二端、寄生二极管Da、主晶体管Ma的第一端与逆向路径334组合成为第一静电放电电流路径。再者，顺向路径332、主晶体管Ma的第一端、主晶体管Ma的通道区域(channel region)、主晶体管Ma的第二端组合成为第二静电放电电流路径。而触发电路320用来控制第二静电放电电流路径的开启与关闭。
在ESD电路300的实际设计上，第一电压Vpp需要小于顺向路径332的开启阈值电压n×Von与半导体元件的崩溃电压Vbd的加总。也就是说，Vpp<(n×Von+Vbd)。举例来说，当第一电压Vpp为+6V且半导体元件的崩溃电压Vbd为+4V时，可设计顺向路径332中的二极管数目n大于等于3。当n等于3时，(n×Von+Vbd)＝(3×0.7V+4V)＝+6.1V，大于第一电压Vpp(+6V)，代表ESD电路300可以正常运作。
另外，当ESD电路300正常运作时，逆向路径334中的m个二极管必须要能够承受(n×Von)的逆向偏压(reverse voltage)。一般来说，当顺向路径332由三个(n＝3)二极管组成时，逆向路径334中设计1个(m＝1)二极管即可承受2.1V的逆向电压。以下以n＝3、m＝1来说明本发明第二实施例ESD电路300的运作原理，但并非用以限制本发明。
当内部电路140接收第一电压Vpp而正常运作时，代表ESD电路300未接收到静电放电冲击(ESD zapping)。举例来说，第一电压Vpp为+6V。此时，逆向路径334与寄生二极管Da为逆向偏压(reverse bias)，所以第一静电放电电流路径关闭。
另外，在触发电路320中，节点b的电压约为+4.9V(Vpp-3×0.7V)，使得第二晶体管M2开启。因此，主晶体管Ma的控制端接收第二电压Vss而关闭，也就是第二静电放电电流路径关闭。
换句话说，当输出入垫350接收+6V的第一电压Vpp时，代表ESD电路300未接收到静电放电冲击。此时，ESD电路300中的第一静电放电电流路径与第二静电放电电流路径皆关闭。而内部电路140接收第一电压Vpp而正常运作。
请参照图4A，其所绘示为第二实施例ESD电路接收到负静电放电冲击(negativeESD zapping)的示意图。当输出入垫350接收到负静电放电冲击时，寄生二极管Da与逆向路径334为顺向偏压(forward bias)，所以第一静电放电电流路径开启。因此，静电放电电流IESD由节点g经由寄生二极管Da、逆向路径334流至输出入垫350。
请参照图4B，其所绘示为第二实施例ESD电路接收到正静电放电冲击(positiveESD zapping)的示意图。当输出入垫350接收到正静电放电冲击时，第一供应电压Vpp快速上升，电容器C暂时短路并使得第一晶体管M1的控制端接收第二电压Vss而开启。因此，主晶体管Ma控制端接收第一电压Vpp而开启，并使得第二静电放电电流路径开启。换句话说，当输出入垫350接收到正静电放电冲击时，触发电路320会开启第二静电放电电流路径，且静电放电电流IESD由输出入垫350经由顺向路径332、主晶体管Ma流至节点g。
由以上的说明可知，当输出入垫350接收到静电放电冲击时，静电放电电流IESD会流经双向降压电路330与放电电路310而不会流经内部电路140，使得内部电路140受到ESD电路300的保护。也就是说，当输出入垫350接收到负静电放电冲击时，静电放电电流IESD由节点g经由放电电路310与该逆向路径334流向输出入垫350。当输出入垫350接收正静电放电冲击时，静电放电电流IESD由输出入垫350经由顺向路径332与放电电路310流向节点g。
在第二实施例的ESD电路300中，放电电路310的主晶体管Ma为NMOS晶体管。在本领域普通技术人员也可以修改触发电路后，并以PMOS晶体管来实现。以下介绍本发明ESD电路的其他实施例。
请参照图5，其所绘示为本发明ESD电路的第三实施例。ESD电路500包括放电电路310、触发电路520与双向降压电路330。相较于第二实施例，差异在于触发电路520。以下仅介绍触发电路520，放电电路310与双向降压电路330不再赘述。
ESD电路500的触发电路520包括电阻R与电容器C。电阻R的第一端连接至节点b，电阻R的第二端连接至节点g。电容器C的第一端连接至节点d，电容器C的第二端连接至节点b。
当内部电路140接收第一电压Vpp而正常运作时，代表ESD电路500未接收到静电放电冲击(ESD zapping)。此时，在触发电路520中，节点b的电压为第二电压Vss，所以主晶体管Ma关闭，也就是第二静电放电电流路径关闭。
另外，当输出入垫350接收到正静电放电冲击时，第一供应电压Vpp快速上升，电容器C暂时短路并使得主晶体管Ma控制端接收第一电压Vpp而开启，并使得第二静电放电电流路径开启。因此，当输出入垫350接收到静电放电冲击时，ESD电路500确实可以保护内部电路140。
在第三实施例的ESD电路500中，由于主晶体管Ma的第一端与控制端之间存在寄生电容器(parasitic capacitor)。在本领域普通技术人员还可将触发电路520中的电容器C省略，并形成另一实施例的ESD电路。也就是说，在另一ESD电路中，触发电路仅包括电阻R连接于节点b与节点g之间，而此ESD电路仍可正常运作。
请参照图6，其所绘示为本发明ESD电路的第四实施例。ESD电路600包括放电电路610、触发电路620与双向降压电路330。
触发电路620包括第一晶体管m1、第二晶体管m2、电阻r与电容器c。第一晶体管m1的第一端连接至节点d，第一晶体管m1的第二端连接至节点a，第一晶体管m1的控制端连接至节点b。第二晶体管m2的第一端连接至节点a，第二晶体管m2的第二端连接至节点g，第二晶体管m2的控制端连接至节点b。电阻r的第一端连接至节点b，电阻r的第二端连接至节点g。电容器c的第一端连接至节点d，电容器c的第二端连接至节点b。
放电电路610包括主晶体管ma，且主晶体管ma为PMOS晶体管。主晶体管ma的第一端与体极端(body terminal)连接至节点d，主晶体管ma的第二端连接至节点g，主晶体管ma的控制端连接至触发电路620中的节点a。另外，主晶体管ma内部有寄生二极管(parasiticdiode)Da。寄生二极管Da的阴极(cathode terminal)连接于主晶体管ma的的体极端(bodyterminal)，阳极(anode terminal)连接于主晶体管ma的第二端。
另外，双向降压电路330的结构相同于第二实施例，此处不再赘述。
根据本发明的第四实施例，ESD电路600中包括第一静电放电电流路径与第二静电放电电流路径。其中，主晶体管ma的第二端、寄生二极管Da、主晶体管ma的第一端与逆向路径334组合成为第一静电放电电流路径。再者，顺向路径332、主晶体管ma的第一端、主晶体管ma的通道区域(channel region)、主晶体管ma的第二端组合成为第二静电放电电流路径。而触发电路620用来控制第二静电放电电流路径的开启与关闭。
当内部电路140接收第一电压Vpp而正常运作时，代表ESD电路600未接收到静电放电冲击(ESD zapping)。此时，逆向路径334与寄生二极管Da为逆向偏压(reverse bias)，所以第一静电放电电流路径关闭。
另外，在触发电路620中，节点b的电压为第二电压Vss，使得第一晶体管m1开启。因此，主晶体管ma的控制端接收节点d的电压而关闭，也就是第二静电放电电流路径关闭。
换句话说，当ESD电路600未接收到静电放电冲击时，ESD电路600中的第一静电放电电流路径与第二静电放电电流路径都关闭。而内部电路140接收第一电压Vpp而正常运作。
另外，当输出入垫350接收到负静电放电冲击时，寄生二极管Da与逆向路径334为顺向偏压(forward bias)，所以第一静电放电电流路径开启。因此，静电放电电流IESD由节点g经由寄生二极管Da、逆向路径334流至输出入垫350。
当输出入垫350接收到正静电放电冲击时，第一供应电压Vpp快速上升，电容器c暂时短路并使得第二晶体管m2的控制端接收第一电压Vpp而开启。因此，主晶体管ma控制端接收第二电压Vss而开启，并使得第二静电放电电流路径开启。换句话说，当输出入垫350接收到正静电放电冲击时，触发电路620会开启第二静电放电电流路径，且静电放电电流IESD由输出入垫350经由顺向路径332、主晶体管ma流至节点g。
由以上的说明可知，当输出入垫350接收到静电放电冲击时，静电放电电流IESD会流经双向降压电路330与放电电路610而不会流经内部电路140，使得内部电路140受到ESD电路600的保护。
请参照图7，其所绘示为本发明ESD电路的第五实施例。ESD电路700包括放电电路610、触发电路720与双向降压电路330。相较于第四实施例，差异在于触发电路720。以下仅介绍触发电路720，放电电路610与双向降压电路330不再赘述。
ESD电路700的触发电路720包括电阻r与电容器c。电阻r的第一端连接至节点d，电阻r的第二端连接至节点b。电容器c的第一端连接至节点b，电容器c的第二端连接至节点g。
当内部电路140接收第一电压Vpp而正常运作时，代表ESD电路700未接收到静电放电冲击(ESD zapping)。此时，在触发电路720中，节点b的电压相同于节点d的电压，所以主晶体管ma关闭，也就是第二静电放电电流路径关闭。
另外，当输出入垫350接收到正静电放电冲击时，第一供应电压Vpp快速上升，电容器c暂时短路并使得主晶体管ma控制端接收第二供应电压Vss而开启，并使得第二静电放电电流路径开启。因此，当输出入垫350接收到静电放电冲击时，ESD电路700确实可以保护内部电路140。
在第五实施例的ESD电路700中，由于主晶体管ma的第一端与控制端之间存在一寄生电容器(parasitic capacitor)。本领域普通技术人员还可将触发电路720中的电容器c省略，并形成另一实施例的ESD电路。也就是说，在另一ESD电路中，触发电路仅包括电阻r连接于节点d与节点b之间，而此ESD电路仍可正常运作。
由以上的说明可知，本发明提出一种ESD电路，ESD电路中的半导体元件为低操作电压(low operation voltage)的半导体元件，例如1.8V的半导体元件。当ESD电路未接收到静电放电冲击(ESD zapping)时，ESD电路内部半导体元件所承受的电压将会低于过栅极氧化层的崩溃电压且低于PN接面的崩溃电压，使得ESD电路能够正常运作。
综上所述，虽然本发明已以实施例揭露如上，然其并非用以限定本发明。本领域普通技术人员在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发的保护范围以权利要求所界定的范围为准。
【符号说明】
100,300,500,600,700:静电放电电路
110,310,610:放电电路
120,320,520,620,720:触发电路
140:内部电路
150,350:输出入垫
330:双向降压电路
332:顺向路径
334:逆向路径

Claims (14)

1.一种静电放电电路，连接于输出入垫与第一节点之间，该静电放电电路包括：
双向降压电路，包括顺向路径连接于该输出入垫与第二节点之间，以及逆向路径连接于该输出入垫与该第二节点之间；
触发电路，连接于该第二节点与该第一节点之间；以及
放电电路，连接于该第二节点与该第一节点之间，其中该放电电路还连接至该触发电路；
其中，当该输出入垫接收负静电放电冲击时，静电放电电流由该第一节点经由该放电电路与该逆向路径流向该输出入垫；以及当该输出入垫接收正静电放电冲击时，该静电放电电流由该输出入垫经由该顺向路径与该放电电路流向该第一节点；
其中，该顺向路径包括：至少一个二极管串接于该输出入垫与该第二节点之间，且当该输出入垫的电压大于该第二节点的电压时，该顺向路径上的该至少一个二极管为顺向偏压。
2.如权利要求1所述的静电放电电路，其中该逆向路径包括：至少一个二极管串接于该输出入垫与该第二节点之间，且当该输出入垫的电压大于该第二节点的电压时，该逆向路径上的该至少一个二极管为逆向偏压。
3.如权利要求2所述的静电放电电路，其中该放电电路包括主晶体管；该主晶体管的第一端连接至该第二节点；该主晶体管的第二端与体极端连接至该第一节点；该主晶体管的控制端连接至该触发电路；该主晶体管具有寄生二极管；该寄生二极管的阴极端连接至该主晶体管的该第一端；以及该寄生二极管的阳极连接至该主晶体管的该体极端。
4.如权利要求3所述的静电放电电路，其中该主晶体管为NMOS晶体管。
5.如权利要求3所述的静电放电电路，其中该触发电路包括：
第一晶体管，该第一晶体管的第一端连接至该第二节点，该第一晶体管的第二端连接至第三节点，该第一晶体管的控制端连接至第四节点；
第二晶体管，该第二晶体管的第一端连接至该第三节点，该第二晶体管的第二端连接至该第一节点，该第二晶体管的控制端连接至该第四节点；
电阻，该电阻的第一端连接至该第二节点，该电阻的第二端连接至该第四节点；以及
电容器，该电容器的第一端连接至该第四节点，该电容器的第二端连接至该第一节点；
其中，该第三节点连接至该主晶体管的该控制端。
6.如权利要求3所述的静电放电电路，其中该触发电路包括：
电容器，该电容器的第一端连接至该第二节点，该电容器的第二端连接至第三节点；
电阻，该电阻的第一端连接至该第三节点，该电阻的第二端连接至该第一节点；以及
其中，该第三节点连接至该主晶体管的该控制端。
7.如权利要求3所述的静电放电电路，其中该触发电路包括：电阻，该电阻的第一端连接至该主晶体管的该控制端，该电阻的第二端连接至该第一节点。
8.如权利要求3所述的静电放电电路，其中当该输出入垫接收该负静电放电冲击时，该静电放电电流由该第一节点经由该主晶体管的该寄生二极管与该逆向路径流向该输出入垫；以及当该输出入垫接收该正静电放电冲击时，该静电放电电流由该输出入垫经由该顺向路径与该主晶体管的通道区域流向该第一节点。
9.如权利要求1所述的静电放电电路，其中该放电电路包括主晶体管；该主晶体管的第一端与体极端连接至该第二节点；该主晶体管的第二端连接至该第一节点；该主晶体管的控制端连接至该触发电路；该主晶体管具有寄生二极管；该寄生二极管的阴极端连接至该主晶体管的该体极端；以及该寄生二极管的阳极连接至该主晶体管的该第二端。
10.如权利要求9所述的静电放电电路，其中该主晶体管为PMOS晶体管。
11.如权利要求9所述的静电放电电路，其中该触发电路包括：
第一晶体管，该第一晶体管的第一端连接至该第二节点，该第一晶体管的第二端连接至一第三节点，该第一晶体管的控制端连接至第四节点；
第二晶体管，该第二晶体管的第一端连接至该第三节点，该第二晶体管的第二端连接至该第一节点，该第二晶体管的控制端连接至该第四节点；
电阻，该电阻的第一端连接至该第四节点，该电阻的第二端连接至该第一节点；以及
电容器，该电容器的第一端连接至该第二节点，该电容器的第二端连接至该第四节点；
其中，该第三节点连接至该主晶体管的该控制端。
12.如权利要求9所述的静电放电电路，其中该触发电路包括：
电阻，该电阻的第一端连接至该第二节点，该电阻的第二端连接至第三节点；
电容器，该电容器的第一端连接至该第三节点，该电容器的第二端连接至该第一节点；以及
其中，该第三节点连接至该主晶体管的该控制端。
13.如权利要求9所述的静电放电电路，其中该触发电路包括：电阻，该电阻的第一端连接至该第二节点，该电阻的第二端连接至该主晶体管的该控制端。
14.如权利要求9所述的静电放电电路，其中当该输出入垫接收该负静电放电冲击时，该静电放电电流由该第一节点经由该主晶体管的该寄生二极管与该逆向路径流向该输出入垫；以及当该输出入垫接收该正静电放电冲击时，该静电放电电流由该输出入垫经由该顺向路径与该主晶体管的通道区域流向该第一节点。
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