CN111934545B - 升压电路及其控制方法 - Google Patents

升压电路及其控制方法 Download PDF

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CN111934545B
CN111934545B CN202010372754.5A CN202010372754A CN111934545B CN 111934545 B CN111934545 B CN 111934545B CN 202010372754 A CN202010372754 A CN 202010372754A CN 111934545 B CN111934545 B CN 111934545B
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charge pump
circuit
voltage
signal
ripple
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CN111934545A (zh
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张家福
谢松龄
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eMemory Technology Inc
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    • H—ELECTRICITY
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    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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Abstract

本发明公开了一种升压电路，包含主要电荷泵电路、辅助电荷泵电路及晶体管。主要电荷泵电路用以响应于时钟信号将供电电压转换为升压电压。辅助电荷泵电路用以响应于时钟信号将供电电压转换为调节电压。晶体管耦接于主要电荷泵电路及辅助电荷泵电路，且具有控制端，用以接收调节电压，第一端，用以接收升压电压，及第二端，用以输出输出电压。

Description

升压电路及其控制方法
技术领域
本发明关于电子电路，特别是一种升压电路及其控制方法。
背景技术
在反及(NAND)闪存或反或(NOR)闪存等内存装置应用中，对于执行各种记忆体操作而言高电压是不可或缺的。通常会使用电荷泵(charge pump)电路将较低的电压进行升压来生成高电压。电荷泵电路可于充电阶段或调节阶段运作。在充电阶段，电荷泵电路将输出电压升高到目标电压电平，在调节阶段，电荷泵电路将输出电压维持在目标电压电平。在调节阶段，电荷泵电路会生成输出电压变化，称为纹波。内存装置采用电荷泵电路时，纹波可能导致输出电压超过最大允许电压电平，因而导致电路组件损坏，或可能导致输出电压降至最小允许电压电平以下，因而编程操作的效能降低。
发明内容
本发明实施例提供一种升压电路，包含主要电荷泵电路、辅助电荷泵电路及晶体管。主要电荷泵电路用以响应于频率讯号将供电电压转换为升压电压。辅助电荷泵电路用以响应于频率讯号将供电电压转换为调节电压。晶体管耦接于主要电荷泵电路及辅助电荷泵电路，且具有控制端，用以接收调节电压，第一端，用以接收升压电压，及第二端，用以输出输出电压。
本发明实施例提供一种方法，控制升压电路，方法包含主要电荷泵电路响应于频率讯号将供电电压转换为升压电压，辅助电荷泵电路响应于频率讯号将供电电压转换为调节电压，及晶体管在控制端接收调节电压，在第一端接收升压电压，及在第二端输出输出电压。
附图说明
图1系为本发明实施例中一种升压电路的方块图。
图2系为图1中升压电路的一种主要电荷泵电路的方块图。
图3系为图1中升压电路的另一种主要电荷泵电路的方块图。
图4系为图1中升压电路的辅助电荷泵电路的方块图。
图5系为图1中升压电路的电荷泵能力控制电路的方块图。
图6系为图5中电荷泵能力控制电路的选定信号的时序图。
图7系为图5中电荷泵能力控制电路的定时器的电路图。
图8系为图5中电荷泵能力控制电路的锁存电路的电路图。
图9系为图5中电荷泵能力控制电路的停止计数器的电路图。
图10系为图1中升压电路的控制方法的流程图。
其中，附图标记说明如下：
1:升压电路
10:主要电荷泵电路
12:辅助电荷泵电路
14:晶体管
16:电荷泵能力控制电路
1000至100n:阶段控制器
1010至101n:控制逻辑电路
1030至103n:延迟及缓冲器
1020至102n:电荷泵阶段
104:比较器
105:分压器
106:译码器
108:时钟生成器
120:缓冲控制器
1200:控制逻辑电路
1202:缓冲器
122:电荷泵阶段
124:比较器
125:分压器
126:译码器
160:电流负载
162:时间控制电路
164:定时器
166:锁存电路
168:停止计数器
70:与非门
721至72p,921至92s,96:触发器
80:缓冲器
821至82q:锁存器
90,94:与门
100:控制方法
S1000至S1010:步骤
CLK,CLK',CLK”,CLK<0>至CLK<n>,CLK'<0>至CLK'<n>:时钟信号
CLK1至CLKs:触发器输出
EN:致能信号
ENILOAD:电流负载致能信号
ENCP<1:n>:电荷泵能力信号
EN_CMP:比较信号
ENFINISH:停止信号
il:预定负载电流
IREF:参考电流
RESET:重置信号
Sto:超时信号
t0至t4:时间
T1:初始期间
T2至T4:预定期间
VDD2:供电电压
VDD2RCP<0：M>,VDDR<0：Q>:分压信号
VDDR:输出电压
VDD2R:升压电压
VDDRREG:调节电压
Vtg:参考电压电平
VREF:比较器参考电压电平
具体实施方式
本揭露实施例提供了一种低纹波升压电路，将直流输入电压转换为较高的直流输出电压，同时减少直流输出电压的纹波的大小(以下称为纹波电压)，以适应由于电压及制程变化所造成的升压电路的驱动能力的变化。直流输出电压可以用以对NAND快闪装置或NOR快闪装置等非挥发性内存装置进行编程。
第1图系为本发明实施例中一种升压电路1的方块图。升压电路1可增加供电电压VDD2以生成具有低纹波电压的输出电压VDDR。输出电压VDDR可例如为3.4V，输出电压VDDR可超过供电电压VDD2的大小，供电电压VDD2可例如在2.2V至2.8V之间。升压电路1可采用源极跟随器或射极跟随器来抚平纹波。此外，由于纹波电压可与驱动能力成正比，因此升压电路1可采用可调的驱动能力以将驱动能力设置为刚好足以驱动相连负载的准位，从而降低输出电压VDDR中的纹波电压(ripple voltage)。在一些实施例中，驱动能力的准位可在启动后的预定编程时间例如100ns之内判定，以使输出电压VDDR准备好用于非挥发性内存的编程操作。
升压电路1可包括主要电荷泵电路10、辅助电荷泵电路12、晶体管14及电荷泵能力控制电路16。主要电荷泵电路10及辅助电荷泵电路12耦接于晶体管14。主要电荷泵电路10及晶体管14耦接于电荷泵能力控制电路16。
主要电荷泵电路10可响应于时钟信号CLK将供电电压VDD2转换为升压电压VDD2R，例如3.6V。辅助电荷泵电路12可响应于时钟信号CLK将供电电压VDD2转换为调节电压VDDRREG，例如3.35V。时钟信号CLK可具有预定周期，例如10ns，及可由主要电荷泵电路10内部或外部的时钟讯生成器生成。主要电荷泵电路10可具有可调的主要驱动能力，主要驱动能力与驱动负载的输出电流的上限值直接相关。在一些实施例中，主要电荷泵电路10可包括多个电荷泵阶段，且主要驱动能力直接正比于选定电荷泵阶段的数量。辅助电荷泵电路12可具有相对固定的辅助驱动能力。辅助电荷泵电路12的辅助驱动能力可小于主要电荷泵电路10的全部驱动能力，因此调节电压VDDRREG的纹波电压可小于升压电压VDD2R的纹波电压。
晶体管14可为N型金属氧化物半导体场效晶体管(metal oxide semiconductorfield effect，MOSFET)或N型双极性结型晶体管(bipolar junction transistor,BJT)，及可设置为源极跟随器设置或射极跟随器。在本实施例中，晶体管14可为原生(native)NMOS晶体管，具有-0.05V的负临界电压。晶体管14具有控制端，用以接收调节电压VDDRREG，第一端，用以接收升压电压VDD2R，及第二端，用以将输出电压VDDR进行输出。晶体管14可将输出电压VDDR实质上锁定在与调节电压VDDRREG相差晶体管14的临界电压的电压。即当调节电压VDDREG为3.35V时，透过晶体管14可稳定传送大于调节电压VDDREG一额定电压(如0.05V)的输出电压VDDR(如3.4V)，且不会减损可输送到负载的电压。主要电荷泵电路10可向晶体管14供应电流以在晶体管14的第二端建立输出电压VDDR。升压电压VDD2R可大于输出电压VDDR，例如升压电压VDD2R可为3.6V，输出电压VDDR可为3.4V。通过采用本发明实施例的配置，输出电压VDDR的纹波电压可明显小于升压电压VDD2R中的纹波电压。
另外，主要电荷泵电路10及电荷泵能力控制电路16可一起判定用于指定电流负载的足够主要驱动能力，例如指定电流负载可为3mA。在一实施例中，电荷泵能力控制电路16可以通过从晶体管14的第二端抽取预定负载电流，例如3mA来仿真指定电流负载，然后主要电荷泵电路10可侦测升压电压VDD2R的目标纹波的峰值，目标纹波系为在参考电压电平上下振荡的纹波，例如参考电压电平可为3.6V。主要电荷泵电路10可比较升压电压VDD2R及参考电压电平以生成比较信号EN_CMP，比较信号EN_CMP表示是否侦测到目标纹波。当升压电压VDD2R的纹波电压在参考电压电平上下振荡一次时，主要电荷泵电路10可在比较信号EN_CMP中生成脉冲，表示已侦测到目标纹波；当升压电压VDD2R的纹波电压不在与基准电压电平附近振荡时，例如升压电压VDD2R的纹波电压在1.2V附近振荡，或当升压电压VDD2R小于基准电压电平时，主要电荷泵电路10可不在比较信号EN_CMP中生成脉冲，表示没有侦测到目标纹波。接着，电荷泵能力控制电路16可以从主要电荷泵电路10接收比较信号EN_CMP，判定预定期间内的目标纹波的计数，例如预定期间可为640ns，及依据目标纹波的计数生成电荷泵能力信号ENCP<1：n>以控制主要电荷泵电路10的主要驱动能力，其中电荷泵能力信号ENCP<1：n>中的n是主要驱动能力的最高级别，例如最高级别可为3。当主要驱动能力不足以驱动指定电流负载时，升压电压VDD2R可降至参考电压电平以下，及主要电荷泵电路10可能无法侦测到升压电压VDD2R的目标纹波；而当主要驱动能力足以驱动指定电流负载时，升压电压VDD2R可在参考电压电平附近振荡，而主要电荷泵电路10可侦测到升压电压VDD2R的目标纹波。在一些实施例中，驱动能力的判定可以从主要驱动能力的最低准位开始并逐级增加，直到可以侦测到升压电压VDD2R的目标纹波为止，从而识别出主要驱动能力的足够准位，同时抑制升压电压VDD2R的纹波电压。
因此，升压电路1利用晶体管14及电荷泵能力控制电路16来减少输出电压VDDR中的纹波电压，同时提供足够的驱动能力来驱动相连的负载。
图2系为一种主要电荷泵电路10的方块图，采用由外部时钟生成器生成的时钟信号CLK。主要电荷泵电路10可包括多个阶段控制器1000至100n、多个电荷泵阶段1020至102n、比较器104、分压器105及译码器106，其中n是超过1的正整数，例如n可为4。电荷泵阶段1020至102n互相耦接。阶段控制器1000至100n分别耦接于比较器104及电荷泵阶段1020至102n之间。另外，阶段控制器1001至100n耦接于电荷泵能力控制电路16。电荷泵阶段1020至102n及译码器106耦接于分压器105，分压器105另耦接于比较器104。
预设情况下，电荷泵阶段1020可被选定以提供最低级的主要驱动能力。主要电荷泵电路10可从电荷泵能力控制电路16接收电荷泵能力信号ENCP<1：n>以判定要选定电荷泵阶段1021至102n中的哪一者。在本发明实施例中，阶段控制器1001至100n可接收电荷泵能力信号ENCP<1：n>以分别选定电荷泵阶段1021至102n，藉以提供多个级别的主要驱动能力及生成升压电压VDD2R。主要电荷泵电路10可由比较器104生成比较信号EN_CMP，以控制选定数量的电荷泵阶段1020至102n的开启及关闭。当比较信号EN_CMP表示升压电压VDD2R小于参考电压电平时，选定数量的电荷泵阶段1020至102n会被致能，而当比较信号EN_CMP表示升压电压VDD2R超过参考电压电平时，则选定数量的电荷泵阶段1020至102n会被失能，以调节升压电压VDD2R的电压电平。
具体而言，可通过包括分压器105及比较器104的回馈路径来调节升压电压VDD2R的电压电平。译码器106可接收分压信号VDD2RCP<0：M>以设置分压器105的分压比，其中M可为正整数，例如M可为2。分压比可被设置以生成预期准位的升压电压VDD2R。在一例子中，译码器106可将分压器105设置为1：3的分压比，以将升压电压VDD2R按比例缩放至四分之一。比较器104可比较升压电压VDD2R的缩放部分及比较器参考电压电平VREF，例如0.85V，以生成具有二逻辑状态其中之一的比较信号EN_CMP，例如二逻辑状态可为1及0，藉以调节升压电压VDD2R的准位及侦测升压电压VDD2R的目标纹波。比较信号EN_CMP可用于控制选定数量的电荷泵阶段1020至102n的致能，及判定升压电压VDD2R的目标纹波数量。在一例子中，比较器104可比较升压电压VDD2R的四分的一部分与0.85V的比较器参考电压电平VREF，当四分之一部分超过0.85V时，在比较信号EN_CMP中输出逻辑状态“1”，当四分之一部分小于0.85V时，在比较信号EN_CMP中输出逻辑状态“0”。接着，从比较信号EN_CMP中接收到逻辑状态“1”之后，阶段控制器1001至100n可使选定数量的电荷泵阶段1020至102n将缩放部分驱至比较器参考电压电平VREF，及从比较信号EN_CMP中接收到逻辑状态“0”之后，阶段控制器1001至100n可失能选定数量的电荷泵阶段段1020至102n以将缩放部分实质上保持在比较器参考电压电平VREF。因此，反馈路径可将升压电压VDD2R的电压电平实质上锁住在四倍的比较器参考电压电平VREF或3.4V。
阶段控制器1000至100n可分别包括多个控制逻辑电路1010至101n及多个延迟及缓冲器1030至103n。控制逻辑电路1010可接收时钟信号CLK及比较信号EN_CMP以生成闸控时钟信号CLK<0>。控制逻辑电路1011至101n可接收时钟信号CLK、比较信号EN_CMP及电荷泵能力信号ENCP<1：n>以分别生成闸控时钟信号CLK<1>至CLK<n>。随后，延迟及缓冲器1030至103n可通过延迟或不延迟时钟信号CLK<0>至CLK<n>来控制用以致能相应电荷泵阶段1020至102n的时序。在一些实施例中，控制逻辑电路1010可包括2输入与非门(NAND gate)，2输入与非门可接收时钟信号CLK及比较信号EN_CMP以生成闸控时钟信号CLK<0>。控制逻辑电路1011至101n可分别包括三输入与非门，三输入与非门可接收时钟信号CLK、比较信号EN_CMP及电荷泵能力信号ENCP<1：n>以生成闸控时钟信号CLK<1>至CLK<n>。在一些实施例中，延迟及缓冲器1030至103n可将闸控时钟信号CLK<0>至CLK<n>延迟不同长度的时间，并在不同的时间点将延迟的时钟信号CLK'<0>至CLK'<n>输入至各自的电荷泵阶段1020至102n，从而防止在电源电压VDD2中生成电压突波，及减少噪声。各个延迟和缓冲器1030至103n的相关延迟时间可在产品制造期间设定。在其他实施例中，延迟及缓冲器1030至103n可将闸控时钟信号CLK<0>至CLK<n>直接转发至各自的电荷泵阶段1020至102n而完全不加入延迟。
图3系为另一种主要电荷泵电路10的方块图。图2及图3中的主要电荷泵电路10的差别在于图3中的主要电荷泵电路10可另包括时钟生成器108，及比较信号EN_CMP可被输入至时钟生成器108而非阶段控制器1000至100n以生成闸控时钟信号CLK'。时钟生成器108可包括与门，与门接收比较信号EN_CMP及时钟信号以输出闸控时钟信号CLK'。控制逻辑电路1010可将闸控时钟信号CLK’作为时钟信号CLK<0>转发至延迟及缓冲器1030。控制逻辑电路1011至101n可分别包括与非门，其接收闸控时钟信号CLK'及电荷泵能力信号ENCP<1：n>以生成时钟信号CLK<1>至CLK<n>，及将时钟信号CLK<1>至CLK<n>分别传送至延迟及缓冲器1030至103n。图3中的其他组件的设置及操作与图2相似，在此不再赘述。
图4系为辅助电荷泵电路12的方块图。辅助电荷泵电路12可包括缓冲控制器120、电荷泵阶段122、比较器124、分压器125及译码器126。缓冲控制器120耦接于电荷泵阶段122。电荷泵阶段122及译码器126耦接于分压器125。分压器125耦接于比较器124。比较器124另耦接于缓冲控制器120。辅助电荷泵电路12采用单一的电荷泵阶段122来生成低纹波调节电压VDDRREG。
缓冲控制器120可接收时钟信号CLK及比较信号ENDET，及依据时钟信号CLK及比较信号ENDET来生成闸控时钟信号CLK”。缓冲控制器120可包括控制逻辑电路1200及缓冲器1202。控制逻辑电路1200可包括与非门，与非门可接收时钟信号CLK及比较信号ENDET以生成闸控时钟信号CLK”。缓冲器1202可将闸控时钟信号CLK”转发至电荷泵阶段122。电荷泵阶段122可响应于闸控时钟信号CLK”将供电电压VDD2转换为调节电压VDDRREG。
译码器126可依据分压信号VDDR<0：Q>设置分压器125的分压比，其中Q可以是正整数，例如Q可为2。分压比可被设置以生成预期准位的调节电压VDDRREG。在一些实施例中，辅助电荷泵电路12中的分压器125的分压比可被设成比主要电荷泵电路10中的分压器105的分压比稍小，以生成略小于升压电压VDD2R的调节电压VDDRREG。分压器125可以接收调节电压VDDRREG以将调节电压VDDRREG的一部分输出至比较器124的输入端。
比较器124可比较调节电压VDDRREG的一部分及比较器参考电压电平VREF，比较器参考电压电平VREF可例如为0.85V，以生成二逻辑状态之一的比较信号ENDET，例如二逻辑状态可为1及0，藉以对调节电压VDDRREG的准位进行调节。当调节电压VDDRREG的一部分小于比较器参考电压电平VREF时，电荷泵阶段122可被比较信号ENDET致能以将调节电压VDDRREG驱至参考电压电平VREF，而当调节电压VDDRREG的一部分超过比较器参考电压电平VREF时，电荷泵阶段122可被比较信号ENDET失能，以将调节电压VDDRREG实质上维持在参考电压电平VREF。
图5系为电荷泵能力控制电路16的方块图。电荷泵能力控制电路16可包括电流负载160、时间控制电路162及停止计数器168。时间控制电路162可包括定时器164及锁存电路166。电流负载160耦接于晶体管14的第二端。定时器164耦接于锁存电路166及停止计数器168。锁存电路166耦接于主要电荷泵电路10。
时间控制电路162可接收致能信号EN、时钟信号CLK及停止信号ENFINISH以测量例如640ns的初始期间，藉以生成电流负载致能信号ENILOAD，及测量一或多个预定期间，预定期间可例如为640ns，用以生成电荷泵能力信号ENCP<1：n>。其中初始期间在一或多个预定期间之前。定时器164可生成超时信号Sto，超时信号Sto表示初始期间或预定期间的终止，例如将超时信号Sto切换到逻辑状态“1”以表示终止。预定期间可被调整为定时器164支持的时间长度，例如6位数定时器164可支持小于或等于64个时间单位的时间长度，且时间单位可以是时钟信号CLK的周期，例如10ns。时钟信号CLK可由生成主要电荷泵电路10及辅助电荷泵电路12使用的时钟信号CLK的相同时钟源生成。在时钟信号CLK实质上稳定后，可通过外部逻辑将致能信号EN设为逻辑状态“1”。停止信号ENFINISH可表示升压电压VDD2R已被驱动至参考电压电平附近。
停止计数器168可判定目标纹波的计数是否在预定期间内达到预定纹波数量，从而判定主要电荷泵电路10是否具有足够的主要驱动能力。在本发明实施例中，停止计数器168可接收比较信号EN_CMP及超时信号Sto以在预定期间期满后当目标纹波的计数已达到预定纹波数量时，生成停止信号ENFINISH。预定纹波数量可例如为8。比较信号EN_CMP可表示侦测到升压电压VDD2R中的目标纹波，及超时信号Sto可表示一或多个预定期间的终止。例如，当在640ns内从升压电压VDD2R中侦测到8个目标纹波时，停止计数器168可将停止信号ENFINISH设为逻辑状态“1”，及当在640ns内无法从升压电压VDD2R侦测到目标纹波时，停止计数器168可将停止信号ENFINISH设为逻辑状态“0”。预定纹波数量可以是可调的。较小的预定纹波数量可能会导致由于升压电压VDD2R中的随机电压突波而造成的错误侦测，较小的预定纹波数量可例如为1。而较大的预定纹波数量可能导致较长的侦测周期，较大的预定纹波数量可例如为16。
在致能后，锁存电路166可在初始期间期满后接收超时信号Sto以生成电流负载致能信号ENILOAD。初始期间可例如为640ns。初始期间被选定以使主要电荷泵电路10使用最低级别的主要驱动能力生成稳定的升压电压VDD2R。随后，锁存电路166可在预定期间期满时更新电荷泵能力信号ENCP<1：n>。初始期间及预定期间的终止可以由超时信号Sto指示。若在预定期间到期后目标纹波的计数尚未达到预定纹波数量，则锁存电路166可更新电荷泵能力信号ENCP<1：n>以依序增加主要电荷泵电路10的主要驱动能力，直到达到最高级驱动能力为止。最高级驱动能力可例如为3。若在预定期间之一期满时目标纹波的计数已达到预定纹波数量，则锁存电路166可保持先前更新的电荷泵能力信号ENCP<1：n>的值，作为足以驱动负载的主要驱动能力。
电流负载160可接收电流负载致能信号ENILOAD及参考电流IREF，例如20uA，及可被电流负载致能信号ENILOAD致能以从晶体管14的第二端抽取预定负载电流il，从而仿真由升压电路1驱动的指定电流负载。预定负载电流il可例如为3mA。在本发明实施例中，电流负载160可以电流传输比为1：R的电流镜电路的形式实现，R是大于1的整数，例如R可以是150。
图6系为图5中电荷泵能力控制电路16的选定信号的时序图。在时间t0，致能信号EN在逻辑状态“1”，而电流负载致能信号ENILOAD、电荷泵能力信号ENCP<1：n>、比较信号EN_CMP及停止信号ENFINISH在逻辑状态“0”。首先，在侦测到致能信号EN被设置为逻辑状态“1”时，定时器164开始计数初始期间T1，在预设情况下选定第一电荷泵阶段1020以驱动升压电压VDD2R直到达到参考电压电平Vtg为止，比较信号EN_CMP中的脉冲表示侦测到目标纹波，每个脉冲表示侦测到一个目标纹波。在时间t1，定时器164开始计数预定期间T2，及锁存电路166将电流负载致能信号ENILOAD设为逻辑状态“1”，使电流负载160从晶体管14的第二端抽取预定负载电流，导致升压电压VDD2R的电压下降。因此，在预定期间T2中比较信号EN_CMP没有表示侦测到目标纹波。在时间t2，定时器164开始计数预定期间T3，由于在预定期间T2中没有侦测到目标纹波，因此锁存电路166将电荷泵能力位ENCP<1>设置为逻辑状态“1”以选定电荷泵阶段1021，藉以驱动升压电压VDD2R升高。由于升压电压VDD2R仍小于参考电压电平Vtg，因此在比较信号EN_CMP中未表示侦测到目标纹波。在时间t3，定时器164再次计数预定期间T4，由于在先前的预定期间T3中没有侦测到目标纹波，所以锁存电路166将电荷泵能力位ENCP<2>设置为逻辑状态“1”以另选定电荷泵阶段1022，藉以驱动升压电压VDD2R升高。在这个阶段，升压电压VDD2R已达到参考电压电平Vtg，主要电荷泵电路10在比较信号EN_CMP中生成脉冲以表示侦测到目标纹波，及停止计数器168判定目标纹波的计数是否已达到预定纹波数量8。在时间t4，在目标纹波的计数达到8之后，停止计数器168将停止信号ENFINISH设为逻辑状态“1”，定时器164停止计数，电流负载致能信号ENILOAD被设为逻辑状态'0'，电荷泵功能位ENCP<1>及ENCP<2>保持逻辑状态'1'，电荷泵功能位ENCP<3>至ENCP<n>被保持在逻辑状态“0”，藉以选定电荷泵阶段1020至1022，而不选定电荷泵阶段1023至102n。期间T1至T4的长度可为相同或不同。在相同长度的情况下，初始期间T1及预定期间T2至T4可以是640ns。当侦测到升压电压VDD2R的目标纹波的计数已达到预定纹波数量时，可缩短最后的预定期间T4。
图7系为定时器164的电路图，定时器164包括三输入与非门70及触发器721至72p，p为大于1的整数。三输入与非门70耦接于触发器721。触发器721至72p互相串接。
三输入与非门70可接收致能信号EN、时钟信号CLK及停止信号ENFINISH以据以生成闸控时钟信号。触发器721至72p以纹波计数器(ripple counter)设置顺序耦接，以依据闸控时钟信号的每个时钟周期生成计数序列，及生成表示初始期间到期或预定周期到期的超时信号Sto。在一些实施例中，触发器721至72p可在初始期间及预定期间期满时在超时信号Sto中生成信号转变。计数序列可以是向上计数序列或向下计数序列。触发器721至72p可通过重置信号RESET来进行重置。
图8系为锁存电路166的电路图，锁存电路166包括缓冲器80及锁存器821至82q，q为大于1的整数。缓冲器80耦接于触发器72p及锁存器821之间。锁存器821至82q互相串接。
锁存器821至82q可以是级联触发器(cascading flip-flops)组成的移位寄存器，及每个锁存器可以在超时信号Sto的转换沿(transition edge)将逻辑状态“1”依序传播到下一锁存器。锁存器821可在超时信号Sto的第一转换沿将电流负载致能信号ENILOAD设为逻辑状态“1”，在超时信号Sto的每个随后转换沿，锁存器822至82q可依序将电荷泵能力信号ENCP<1>至ENCP<n>设为逻辑状态“1”。锁存器821至82q可通过重置信号RESET来进行重置。
图9系为停止计数器168的电路图。停止计数器168可包括2输入与门90、触发器921至92s、与门94及触发器96，s是大于1的整数。2输入与门90耦接于触发器921。触发器921至92s互相串接。触发器921至92s耦接于与门94。与门94耦接于触发器96。停止计数器168可以生成停止信号ENFINISH，用以表示目标纹波数量已经达到预定纹波数量。
与门90可接收致能信号EN及比较信号EN_CMP以生成第一及运算输出信号A1。触发器921至92s以纹波计数器设置顺序耦接，在第一及运算输出信号的每个预定转换沿生成计数序列，以生成目标纹波的计数。计数序列可以是向上计数序列或向下计数序列。预定转换沿可以是上升沿或下降沿。触发器921至92s可从定时器164接收超时信号Sto以用作重置信号RESET，并且可由重置信号RESET来重置。与门94可接收触发器921到92s的输出以判定目标纹波的计数是否已达到预定纹波数量8，若是，则将第二及运算输出信号A2设为逻辑状态“1”。在一些实施例中，与门94可用其他组合逻辑电路代替以提供其他预定纹波数量的值，例如6。在侦测到来自与门94的第二及运算输出信号的上升沿转换时，触发器96可通过将停止信号ENFINISH设为逻辑状态“1”来标记停止信号ENFINISH。
图10系为升压电路1的控制方法100的流程图。方法100包括步骤S1000至S1010。步骤S1000至S1004用于使用源极跟随器来减少输出电压VDDR的纹波电压。步骤S1006至S1010用于为主要电荷泵电路10选定足够的驱动能力，从而进一步控制输出电压VDDR的纹波电压。任何合理的技术变更或是步骤调整都属于本发明所揭露的范畴。步骤S1000至S1010如下：
步骤S1000：主要电荷泵电路10响应于时钟信号CLK将供电电压VDD2转换为升压电压VDD2R；
步骤S1002：辅助电荷泵电路12响应于时钟信号CLK将供电电压VDD2转换为调节电压VDDRREG；
步骤S1004：晶体管14在控制端接收调节电压VDDRREG，在第一端接收升压电压VDD2R，及在第二端输出输出电压VDDR；
步骤S1006：主要电荷泵电路10侦测升压电压VDD2R的目标纹波；
步骤S1008：电荷泵能力控制电路16从晶体管14的第二端抽取预定负载电流；
步骤S1010：电荷泵能力控制电路16判定预定期间中的目标纹波的计数，并依据目标纹波的计数生成电荷泵能力信号ENCP<1：n>以控制主要电荷泵电路10的驱动能力。
前面的段落已详细解释了步骤S1000至S1010，在此不再赘述。方法100用于控制升压电路1的晶体管14及电荷泵能力控制电路16来减少输出电压VDDR中的纹波电压，同时提供足够的驱动能力来驱动相连的负载。
第1图至图10的实施例提供具有纹波控制的升压电路及其控制方法，降低输出电压中的纹波电压，防止电路组件被过高的输出电压损坏，及通过生成足以驱动负载的输出电压来增强电路性能。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (19)

1.一种升压电路，其特征在于，包括：
一主要电荷泵电路，用以响应于一时钟信号将一供电电压转换为一升压电压，及用以侦测目标纹波，该目标纹波系为该升压电压在一参考电压电平上下震荡的纹波；
一辅助电荷泵电路，用以响应于该时钟信号将该供电电压转换为一调节电压；
一晶体管，耦接于该主要电荷泵电路及该辅助电荷泵电路，具有一控制端，用以接收该调节电压，一第一端，用以接收该升压电压，及一第二端，用以输出一输出电压；及
一电荷泵能力控制电路，耦接于该主要电荷泵电路及该晶体管，及用以从该晶体管的该第二端抽取一预定负载电流，在一预定期间中判定该目标纹波的一计数，及依据该目标纹波的该计数生成一电荷泵能力信号，藉以控制该主要电荷泵电路的驱动能力。
2.根据权利要求1所述的升压电路，其特征在于，其中该电荷泵能力控制电路包括：
一电流负载，耦接于该晶体管，及用以依据一电流负载致能信号从该晶体管的该第二端抽取该预定负载电流；
一定时器，耦接于该电流负载，及用以测量一初始期间及该预定期间；一停止计数器，耦接于该定时器，及用以判定在该预定期间中该目标纹波的该计数是否已达到一预定纹波数量；及
一锁存电路，耦接于该定时器及该主要电荷泵电路，及用以在该初始期间满期后生成该电流负载致能信号，及若在该预定期间中该目标纹波的该计数未达到该预定纹波数量，更新该电荷泵能力信号以增加该主要电荷泵电路的该驱动能力；
其中该初始期间在该预定期间之前。
3.根据权利要求2所述的升压电路，其特征在于，其中该停止计数器包括：
一第一与门，用以接收一致能信号及一比较信号以据以生成一及运算输出信号；
多个第一级联触发器，耦接于该第一与门，及用以依据该及运算输出信号生成该目标纹波的该计数；
一第二与门，耦接于该多个第一级联触发器，及用以判定在该预定期间中该目标纹波的该计数是否已达到该预定纹波数量；及
一输出触发器，耦接于该第二与门，及当该目标纹波的该计数已达到该预定纹波数量时用以标记一停止信号。
4.根据权利要求3所述的升压电路，其特征在于，其中该定时器包括：
一三输入与非门，用以接收该致能信号、该时钟信号及该停止信号以据以生成一闸控时钟信号；及
多个第二级联触发器，耦接于该三输入与非门，及用以依据该时钟信号测量该初始期间及该预定期间，及生成一超时信号，该超时信号表示该初始期间满期或该预定期间满期。
5.根据权利要求4所述的升压电路，其特征在于，其中该锁存电路包括：多个第三级联触发器，耦接于该多个第二级联触发器，及用以依据该超时信号生成该电流负载致能信号及该电荷泵能力信号。
6.根据权利要求1所述的升压电路，其特征在于，其中该主要电荷泵电路包括多个电荷泵阶段，耦接于该电荷泵能力控制电路，及用以接收该电荷泵能力信号以判定要选定哪个电荷泵阶段。
7.根据权利要求6所述的升压电路，其特征在于，其中该主要电荷泵电路还包括多个延迟及缓冲器，分别耦接于该多个电荷泵阶段，及用以分别控制致能该多个电荷泵阶段的时序。
8.根据权利要求6所述的升压电路，其特征在于，其中：
该主要电荷泵电路还包括一比较器，用以比较该升压电压的一部分及一比较器参考电压电平以生成一比较信号，该比较信号表示是否侦测到该升压电压的该目标纹波；及
当该升压电压的该部分小于该比较器参考电压电平时，致能该多个电荷泵阶段中一选定数量的电荷泵阶段，及当该升压电压的该部分超过该比较器参考电压电平时，失能该选定数量的电荷泵阶段。
9.根据权利要求1所述的升压电路，其特征在于，其中该辅助电荷泵电路包括：
一缓冲器；
一电荷泵阶段，耦接于该缓冲器，及用以响应于该时钟信号将该供电电压转换为该调节电压；及
一比较器，耦接于该电荷泵阶段，及用以比较该调节电压的一部分及一比较器参考电压电平；
其中当该调节电压的该部分小于该比较器参考电压电平时，致能该电荷泵阶段，及当该调节电压的该部分超过该比较器参考电压电平时，失能该电荷泵阶段。
10.根据权利要求1所述的升压电路，其特征在于，其中该晶体管系为一原生(native)NMOS晶体管。
11.一种控制升压电路的方法，其特征在于，包括：
一主要电荷泵电路响应于一时钟信号将一供电电压转换为一升压电压；该主要电荷泵电路侦测一目标纹波，该目标纹波系为该升压电压在一参考电压电平上下震荡的纹波；
一辅助电荷泵电路响应于该时钟信号将该供电电压转换为一调节电压；一晶体管在一控制端接收该调节电压，在一第一端接收该升压电压，及
在一第二端输出一输出电压；
一电荷泵能力控制电路从该晶体管的该第二端抽取一预定负载电流；
该电荷泵能力控制电路在一预定期间中判定该目标纹波的一计数；及
该电荷泵能力控制电路依据该目标纹波的该计数生成一电荷泵能力信号以控制该主要电荷泵电路的驱动能力。
12.根据权利要求11所述的方法，其特征在于，其中：
该电荷泵能力控制电路从该晶体管的该第二端抽取该预定负载电流包括：
该电荷泵能力控制电路的一电流负载用以依据一电流负载致能信号从该晶体管的该第二端抽取该预定负载电流；
该电荷泵能力控制电路在该预定期间中判定该目标纹波的该计数包括：
该电荷泵能力控制电路的一定时器测量一初始期间及该预定期间，该初始期间在该预定期间之前；及
该电荷泵能力控制电路的一停止计数器判定该目标纹波的该计数；及
该电荷泵能力控制电路依据该目标纹波的该计数生成该电荷泵能力信号包括：
该停止计数器在该预定期间中判定该目标纹波的该计数是否已达到一预定纹波数量；及
该电荷泵能力控制电路的一锁存电路在该初始期间满期后生成该电流负载致能信号，及若在该预定期间中该目标纹波的该计数未达到该预定纹波数量，更新该电荷泵能力信号以增加该主要电荷泵电路的该驱动能力。
13.根据权利要求11所述的方法，其特征在于，其中:
该主要电荷泵电路包括多个电荷泵阶段；及
该方法还包括该主要电荷泵电路接收该电荷泵能力信号以判定要选定哪个电荷泵阶段。
14.根据权利要求13所述的方法，其特征在于，还包括：
多个延迟及缓冲器分别控制用以致能该多个电荷泵阶段的时序。
15.根据权利要求13所述的方法，其特征在于，还包括：
该主要电荷泵电路的一比较器比较该升压电压的一部分及一比较器参考电压电平以生成一比较信号，该比较信号表示是否侦测到升压电压的该目标纹波；及
当该升压电压的该部分小于该比较器参考电压电平时，致能该多个电荷泵阶段。
16.根据权利要求13所述的方法，其特征在于，还包括:
该主要电荷泵电路的一比较器比较该升压电压的一部分及一比较器参考电压电平以生成一比较信号，该比较信号表示是否侦测到升压电压的该目标纹波；及
当该升压电压的该部分超过该比较器参考电压电平时，失能该多个电荷泵阶段。
17.根据权利要求11所述的方法，其特征在于，其中该辅助电荷泵电路响应于该时钟信号将该供电电压转换为该调节电压包括：
该辅助电荷泵电路的一电荷泵阶段响应于该时钟信号将该供电电压转换为该调节电压。
18.根据权利要求17所述的方法，其特征在于，还包括：
该辅助电荷泵电路的一比较器比较该调节电压的一部分及一比较器参考电压电平以生成一比较信号；及
依据该比较信号控制该辅助电荷泵电路的该电荷泵阶段。
19.一种升压电路，其特征在于，包括：
一主要电荷泵电路，用以响应于一时钟信号将一供电电压转换为一升压电压；
一辅助电荷泵电路，用以响应于该时钟信号将该供电电压转换为一调节电压，包括：
一缓冲器；
一电荷泵阶段，耦接于该缓冲器，及用以响应于该时钟信号将该供电电压转换为该调节电压；及
一比较器，耦接于该电荷泵阶段，及用以比较该调节电压的一部分及一比较器参考电压电平；及
一晶体管，耦接于该主要电荷泵电路及该辅助电荷泵电路，具有一控制端，用以接收该调节电压，一第一端，用以接收该升压电压，及一第二端，用以输出一输出电压；
其中当该调节电压的该部分小于该比较器参考电压电平时，致能该电荷泵阶段，及当该调节电压的该部分超过该比较器参考电压电平时，失能该电荷泵阶段。
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