TW202042348A - 記憶體裝置及其半導體製程方法 - Google Patents

記憶體裝置及其半導體製程方法 Download PDF

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TW202042348A
TW202042348A TW109115705A TW109115705A TW202042348A TW 202042348 A TW202042348 A TW 202042348A TW 109115705 A TW109115705 A TW 109115705A TW 109115705 A TW109115705 A TW 109115705A TW 202042348 A TW202042348 A TW 202042348A
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voltage
doped region
gate layer
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許家榮
陳緯仁
孫文堂
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力旺電子股份有限公司
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Abstract

一種記憶體裝置，包含井、第一閘極層、第二閘極層、摻雜區、阻擋層及對齊層。該第一閘極層形成於該井上。該第二閘極層形成於該井上。該摻雜區形成於該井中，且位於該第一閘極層及該第二閘極層之間。該阻擋層係形成以覆蓋該第一閘極層、該摻雜區及該第二閘極層之一部分，用以阻擋電子過度逸散。該對齊層係形成於該阻擋層上及該第一閘極層、該摻雜區及該第二閘極層之該部分之上方。該對齊層比該阻擋層、該第一閘極層及該第二閘極層之每一者更薄。

Description

記憶體裝置及其半導體製程方法
本發明係關於記憶體裝置及半導體製程方法，尤指包含對齊層之記憶體裝置及製造記憶體裝置的半導體製程方法。
對記憶體裝置而言，保持（retention）時間是評估效能的重要參數。當記憶體裝置具有更長的保持時間，則可將資料儲存得更久，且記憶體裝置的可靠性與品質會視為更優良。
此外，評估記憶體裝置的效能時，諸如寫入、抹除及讀取等記憶體操作的效能也須一併考量。記憶體操作的效能可根據操作時間、及操作相關的可控度予以評估。當可控度較高時，執行記憶體操作的失敗機率較低。
因此，於本領域，尚須可改善記憶體裝置之保持時間及可控度的解決方案。
實施例提供一種記憶體裝置，包含井、第一閘極層、第二閘極層、摻雜區、阻擋層及對齊層。該井形成於基板中。該第一閘極層形成於該井上。該第二閘極層形成於該井上。該摻雜區形成於該井中，且位於該第一閘極層及該第二閘極層之間。該阻擋層覆蓋該第一閘極層、該摻雜區及該第二閘極層之一部分，用以阻擋電子過度逸散。該對齊層係形成於該阻擋層上及該第一閘極層、該摻雜區及該第二閘極層之該部分之上方。該對齊層比該阻擋層、該第一閘極層及該第二閘極層之每一者更薄。
實施例提供一種半導體製程方法，用於製造記憶體裝置。該方法包含於井上形成第一閘極層及第二閘極層；沉積產生阻擋層以覆蓋該第一閘極層及該第二閘極層；沉積產生對齊層以覆蓋該阻擋層；使用光罩，從而施加光阻，以移除該對齊層之一部分，使該對齊層之遺留部分覆蓋第一區、第二區、該第一閘極層及該第二閘極層之一部分；及使用該光阻，從而移除該阻擋層之一部分，使該阻擋層之遺留部分覆蓋該第一區、該第二區、該第一閘極層及該第二閘極層之該部分。該第一區介於該第一閘極層及該第二閘極層之間，且該第二區位於該第一閘極層旁。該對齊層比該阻擋層、該第一閘極層及該第二閘極層之每一者更薄。
本文中，當區域或元件（例如A）被描述為位於兩區域及/或元件（例如B與C）之間，表示A大約位於B與C之間，且A可能與B及/或C部分接觸或部分重疊。同理，當區域或元件（例如A）被描述為位於區域或元件（例如D）旁，表示A大約位於D旁，且A可能與B及/或C部分接觸或部分重疊。
第1圖是實施例中，記憶體裝置100的佈局圖。第2圖是第1圖的記憶體裝置100沿著線段2-2’的部分剖面圖。記憶體裝置100可包含第一井150、第一閘極層110、第二閘極層120、第一摻雜區1110、阻擋層160、對齊層170、接觸蝕刻停止層180、矽化物層190、191、192及193、第二摻雜區1120及第三摻雜區1130。矽化物層190、191、192及193可為自對齊矽化物（Self-aligned silicide，Salicide）層。
第一井150形成於基板145中，第一閘極層110及第二閘極層120形成於第一井150上。第一摻雜區1110形成於第一井150中，且位於第一閘極層110及第二閘極層120之間。
阻擋層160覆蓋第一閘極層110、第一摻雜區1110及第二閘極層120之第一部分120a，用以阻擋電子199過度逸散。阻擋層160可為矽化物阻擋（salicide blocking，SAB）層或阻障氧化（resist-protection-oxide，RPO）層，用以提高阻抗。
對齊層170可形成於阻擋層160上及第一閘極層110及第二閘極層120之第一部分120之上方。因此，阻擋層160可實質上與對齊層170相互對齊。
對齊層170比阻擋層160、第一閘極層110及第二閘極層120之每一者更薄。
根據實施例，對齊層170的厚度小於第一閘極層110的厚度之25%，且阻擋層160的厚度大於第一閘極層110的厚度之25%。第一閘極層110及第二閘極層120的厚度可相近或約略相同。舉例而言，第一閘極層110、阻擋層160及對齊層170的厚度可分別約為（但不限於）2000埃（Å）、1000埃及300埃。因此，相較於第一閘極層110、阻擋層160及第二閘極層120，對齊層170更薄。
接觸蝕刻停止層180可形成於對齊層170及第二閘極層120之第二部分120b之上，用以阻擋接觸層製程的蝕刻。根據實施例，接觸蝕刻停止層180可另形成於第二摻雜區1120及第三摻雜區1130之上。
第一閘極層110、第二閘極層120及對齊層170可以多晶矽形成。
如第2圖所示，矽化物層190可形成於對齊層170及接觸蝕刻停止層180之間。矽化物層191可形成於第二閘極層120之第二部分120b及接觸蝕刻停止層180之間。由於對齊層170及第二閘極層120可由多晶矽形成，故矽化物層190及191可藉由化學反應形成。同理，矽化物層192可藉由化學反應形成於接觸蝕刻停止層180及第二摻雜區1120之間，且矽化物層193可藉由化學反應形成於接觸蝕刻停止層180及該第三摻雜區1130之間。矽化物層190、191、192及193可具有導電性且用於導電。
如第2圖所示，第二摻雜區1120可形成於第一井150中，且位於第一閘極層110旁。第三摻雜區1130可形成於第一井150中，且位於第二閘極層120旁。
第3圖是第1圖的記憶體裝置沿著線段3-3’的部分剖面圖。如第3圖所示，第一閘極層110另覆蓋第四摻雜區1140之一部分，且第四摻雜區1140形成於第二井155中。根據實施例，第一井150可形成於第二井155中。
根據實施例，第一井150可為N型井，且第二井155可為P型井。第一摻雜區1110、第二摻雜區1120及第三摻雜區1130可為P型摻雜區。第二井155可為P型井或P型基板。第四摻雜區1140可為N型摻雜區。
關於記憶體裝置100的結構，第一閘極層110可為浮動閘極（稱為FG），第二閘極層120可為選擇閘極（稱為SG）及字元線（稱為WL），第二摻雜區1120可為位元線（稱為BL），第三摻雜區1130可為來源線（SL），且第四摻雜區1140可為抹除線（稱為EL）。
因為第一閘極層110（浮動閘極）可覆蓋第四摻雜區1140（抹除線）的一部分，當要施加電壓到第一閘極層110時，該電壓可被施加到第四摻雜區1140，第一閘極層110可透過耦合效應接收到該電壓。然而，若只靠第四摻雜區1140及第一閘極層110之間的耦合效應來施加電壓，效率與可控度是不足的。如第2圖及第3圖所示，除了利用耦合效應透過第四摻雜區1140施加電壓到第一閘極層110，該電壓還可透過第一接觸層181、矽化物層190及對齊層170而被耦合而施加到第一閘極層110。因此，操作記憶體裝置100的效能及可控度可得到改善，操作時間也可縮短。
如第2圖所示，記憶裝置100可另包含第一接觸層181、第二接觸層182、第三接觸層183及第四接觸層184。
前述的接觸層製程可用以產生第一接觸層181、第二接觸層182、第三接觸層183及第四接觸層184。
第一接觸層181可接觸於矽化物層190，用以施加電壓給對齊層170，以使該電壓被耦合而施加到第一閘極層110。
第二接觸層182可形成於第二閘極層120之上方，接觸於矽化物層191，用以施加另一電壓至第二閘極層120。
第三接觸層183可形成於第三摻雜區1130之上方，接觸於矽化物層193，用以施加另一電壓至第三摻雜區1130。
第四接觸層184可形成於第二摻雜區1120之上方，接觸於矽化物層192，及用以施加另一電壓至第二摻雜區1120。
第一接觸層181至第四接觸層184可用以施加電壓，從而執行下文表格1所述的記憶體操作。
記憶體裝置100可支援寫入操作、正抹除操作、負抹除操作、軟式寫入操作及讀取操作等記憶體操作。每項操作中，施加於記憶體裝置100的電壓可如表格1所述。
  寫入操作 正抹除操作 負抹除操作 軟式寫入操作 讀取操作
第一井150 V1 0 0 V6 V8
第二井 155 0 0 0 0 0
第三摻雜區 1130 (來源線) V1 0 V5 V6 V8
第二摻雜區 1120 (位元線) 0 0 V5 0 V9
第二閘極層120 (選擇閘極/字元線) V2 0 V5 V6 0
第四摻雜區1140 (抹除線) V3 V4 V4 V7 V10
矽化物層190 V3 0 V5 V7 V10
(表格1)
如表格1所述，於寫入操作時，於第一井150及第三摻雜區1130施加第一電壓V1，於第二井155及第二摻雜區1120施加零電壓（表示為0），於第二閘極層120施加第二電壓V2，且於第四摻雜區1140及矽化物層190施加第三電壓V3。第一電壓V1及第二電壓V2係正電壓，第二電壓V2係小於或等於第一電壓V1，換句話說，可表示為V2 ≤ V1。第三電壓V3可於零電壓及第二電壓V2之間變化。舉例來說，V1=7伏特，V2= V1/2 = 3.5伏特，且V3可於0伏特到3.5伏特之間變化。
關於第三電壓V3，第三電壓V3可於零電壓及第二電壓V2之間以K步變化，且K係大於零之整數。舉例來說，若K=1，則第三電壓V3可以兩階段變化：於第一階段，第三電壓V3可為0伏特以避免固定位元（stuck bit）；而於第二階段，第三電壓V3可為3.5伏特以使電子進入第一閘極層110（例如浮動閘極）。
如表格1所述，在正抹除操作時，於第一井150、第二井155、第二摻雜區1120、第三摻雜區1130、第二閘極層120及矽化物層190施加零電壓，且於第四摻雜區1140施加第四電壓V4。第四電壓V4係正電壓。舉例來說，第四電壓V4可為較高的電壓，例如15伏特。於正抹除操作時，可將電子從第一閘極層110拉到第四摻雜區1140。
如表格1所述，在負抹除操作時，於第一井150及第二井155施加零電壓，於第四摻雜區1140施加第四電壓V4，且於第二摻雜區1120、第三摻雜區1130、第二閘極層120及矽化物層190施加第五電壓V5。第四電壓V4係正電壓，且第五電壓V5係負電壓。舉例來說，第四電壓V4可為較高的電壓，例如15伏特，且第五電壓V5可為-7伏特。於另一個例子中，若裝置發生崩潰（break down），可將第四電壓V4調整為10伏特。
如表格1所述，在軟式寫入操作時，於第一井150、第三摻雜區1130及第二閘極層120施加第六電壓V6，於第二井155及第二摻雜區1120施加零電壓，且於第四摻雜區1140及矽化物層190施加第七電壓V7。第六電壓V6及第七電壓V7係正電壓，且第七電壓V7係小於或等於第六電壓V6。換句話說，可表示為V7 ≤ V6。舉例來說，第六電壓V6可為7伏特，且第七電壓V7可為3.5伏特。軟式寫入操作可允許少量電子進入第一閘極層110，從而準備後續的寫入操作。軟式寫入操作可藉由帶對帶熱電子注入（band-to-band hot electron injection）來執行。
如表格1所述，在讀取操作時，於第一井150及第三摻雜區1130施加第八電壓V8，於第二井155及第二閘極層120施加零電壓，於第二摻雜區1120施加第九電壓V9，且於第四摻雜區1140及矽化物層190施加第十電壓V10。第八電壓V8係正電壓。第九電壓V9係等於零電壓、或微幅高於零電壓。第十電壓V10係介於零電壓及第八電壓V8之間。換句話說，可表示為0 > V10 > V8。舉例來說，第八電壓V8可為2.5伏特，第九電壓V9可為0伏特或0.4伏特，且第十電壓V10可介於0至2.5伏特之間。當第十電壓V10提高時，從第三摻雜區1130流到第一摻雜區1110的電流可降低。
第4圖為製造第2圖之記憶體裝置100的半導體製程方法400的流程圖。第5圖至第8圖是執行第4圖的方法400的製程示意圖。如第1圖到第8圖所示，方法400可包含以下步驟。
步驟410：於第一井150上形成第一閘極層110及第二閘極層120；
步驟420：沉積產生阻擋層160以覆蓋第一閘極層110及第二閘極層120；
步驟430：沉積產生對齊層170以覆蓋阻擋層160；
步驟440：使用光罩，從而施加光阻755，以移除對齊層170之一部分，使對齊層170之遺留部分覆蓋第一區710、第二區720、第一閘極層110及第二閘極層120之第一部分120a，其中第一區710介於第一閘極層110及第二閘極層120之間，且第二區720位於第一閘極層110旁；及
步驟450：使用光阻755，從而移除阻擋層160之一部分，使阻擋層160之遺留部分覆蓋第一區710、第二區720、第一閘極層110及第二閘極層120之第一部分120a。
步驟410至步驟430可對應於第5圖及第6圖，步驟440可對應於第7圖，且步驟450可對應於第8圖。對齊層170可比阻擋層160、第一閘極層110及第二閘極層120之每一者更薄。
關於步驟410，根據實施例，第一閘極層110及第二閘極層120可形成於第一井150、間隔層（spacer）及佈植區上。關於步驟420，根據實施例，阻擋層160可被沉積產生以覆蓋第一閘極層110、第二閘極層120、間隔層及佈植區。
在第7圖及步驟440中，所述的光罩可用以在規劃的區域將光阻755塗佈於對齊層170。此可保留對齊層170之一部分，且使用第一化學物質來蝕刻及移除對齊層170的另一部分。
同理，在第8圖及步驟450中，可使用第二化學物質來蝕刻及移除阻擋層160的一部分。然後，可移除光阻755。
關於第7圖、第8圖及步驟440至步驟450，相同的光罩可用以沉積及蝕刻對齊層170及阻擋層160。因此，可不須使用額外光罩，即可製作對齊層170。
關於第2圖及第5圖至第8圖，根據實施例，可執行摻雜操作以形成第一摻雜區1110、第二摻雜區1120及第三摻雜區1130。第一摻雜區1110可對應於第一區710，第二摻雜區1120可對應於第二區720，第三摻雜區1130可對應於第三區730，且第三區730可位於第二閘極層120旁。藉由使用阻擋層160，可防止電子從第一閘極層110過度逸散，故可改善記憶體裝置110的保持時間。藉由使用對齊層170，可改善接觸蝕刻停止層180及阻擋層160之間的隔離度，故可提高良率。
此外，藉由耦合效應，可透過第一接觸層181、矽化物層190及對齊層170，施加電壓至第一閘極層110。因此，記憶體操作的可控度、彈性及效率皆可改善。如上所述，實施例提供的記憶體裝置及半導體製程方法可有效減少本領域的問題。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100:記憶體裝置 110:第一閘極層 1110:第一摻雜區 1120:第二摻雜區 1130:第三摻雜區 1140:第四摻雜區 120:第二閘極層 120a:第一部分 120b:第二部分 145:基板 150:第一井 155:第二井 160:阻擋層 170:對齊層 180:接觸蝕刻停止層 181:第一接觸層 182:第二接觸層 183:第三接觸層 184:第四接觸層 190,191,192,193:矽化物層 199:電子 2-2',3-3':線段 400:半導體製程方法 410,420,430,440,450:步驟 710:第一區 720:第二區 730:第三區 755:光阻
第1圖是實施例中，記憶體裝置的佈局圖。 第2圖是第1圖的記憶體裝置的部分剖面圖。 第3圖是第1圖的記憶體裝置的部分剖面圖。 第4圖為製造第2圖之記憶體裝置的半導體製程方法的流程圖。 第5圖至第8圖是執行第4圖的方法的製程示意圖。
100:記憶體裝置
110:第一閘極層
1110:第一摻雜區
1120:第二摻雜區
1130:第三摻雜區
120:第二閘極層
120a:第一部分
120b:第二部分
145:基板
150:第一井
160:阻擋層
170:對齊層
180:接觸蝕刻停止層
181:第一接觸層
182:第二接觸層
183:第三接觸層
184:第四接觸層
190,191,192,193:矽化物層
199:電子
2-2':線段

Claims (20)

  1. 一種記憶體裝置，包含： 一第一井，形成於一基板中； 一第一閘極層，形成於該第一井上； 一第二閘極層，形成於該第一井上； 一第一摻雜區，形成於該第一井中，及位於該第一閘極層及該第二閘極層之間； 一阻擋層，覆蓋該第一閘極層、該第一摻雜區及該第二閘極層之一第一部分，及用以阻擋電子過度逸散；及 一對齊層，形成於該阻擋層上，及該第一閘極層、該第一摻雜區及該第二閘極層之該第一部分之上方； 其中該對齊層比該阻擋層、該第一閘極層及該第二閘極層之每一者更薄。
  2. 如請求項1所述之記憶體裝置，其中該第一閘極層、該第二閘極層及該對齊層係以多晶矽形成。
  3. 如請求項1所述之記憶體裝置，其中該第一閘極層係一浮動閘極，且該第二閘極層係一選擇閘極。
  4. 如請求項1所述之記憶體裝置，另包含： 一接觸蝕刻停止層，形成於該對齊層及該第二閘極層之一第二部分之上，用以阻擋一接觸層製程之蝕刻。
  5. 如請求項4所述之記憶體裝置，另包含： 一第一矽化物層，形成於該對齊層及該接觸蝕刻停止層之間；及 一第二矽化物層，形成於該第二閘極層之該第二部分及該接觸蝕刻停止層之間。
  6. 如請求項5所述之記憶體裝置，另包含： 一第二摻雜區，形成於該第一井中，及位於該第一閘極層旁； 一第三摻雜區，形成於該第一井中，及位於該第二閘極層旁； 一第三矽化物層，形成於該接觸蝕刻停止層及該第二摻雜區之間；及 一第四矽化物層，形成於該接觸蝕刻停止層及該第三摻雜區之間。
  7. 如請求項6所述之記憶體裝置，其中該第一井係一N型井，該第一摻雜區、該第二摻雜區及該第三摻雜區係P型摻雜區。
  8. 如請求項6所述之記憶體裝置，其中該第一閘極層另覆蓋一第四摻雜區之一部分，該第四摻雜區形成於一第二井中，該第一閘極層係一浮動閘極，該第二閘極層係一選擇閘極及一字元線，該第二摻雜區係一位元線，該第三摻雜區係一來源線，且該第四摻雜區係一抹除線。
  9. 如請求項8所述之記憶體裝置，其中在一寫入操作時，於該第一井及該第三摻雜區施加一第一電壓，於該第二井及該第二摻雜區施加一零電壓，於該第二閘極層施加一第二電壓，於該第四摻雜區及該第一矽化物層施加一第三電壓，該第一電壓及該第二電壓係正電壓，該第二電壓係小於或等於該第一電壓，且該第三電壓係於該零電壓及該第二電壓之間變化。
  10. 如請求項9所述之記憶體裝置，其中該第三電壓係於該零電壓及該第二電壓之間以K步變化，且K係大於零之整數。
  11. 如請求項8所述之記憶體裝置，其中在一正抹除操作時，於該第一井、該第二井、該第二摻雜區、該第三摻雜區、該第二閘極層及該第一矽化物層施加一零電壓，於該第四摻雜區施加一第四電壓，且該第四電壓係一正電壓。
  12. 如請求項8所述之記憶體裝置，其中在一負抹除操作時，於該第一井及該第二井施加一零電壓，於該第四摻雜區施加一第四電壓，於該第二摻雜區、該第三摻雜區、該第二閘極層及該第一矽化物層施加一第五電壓，該第四電壓係一正電壓，且該第五電壓係一負電壓。
  13. 如請求項8所述之記憶體裝置，其中在一軟式寫入操作時，於該第一井、該第三摻雜區及該第二閘極層施加一第六電壓，於該第二井及該第二摻雜區施加一零電壓，於該第四摻雜區及該第一矽化物層施加一第七電壓，該第六電壓及該第七電壓係正電壓，且該第七電壓係小於或等於該第六電壓。
  14. 如請求項8所述之記憶體裝置，其中在一讀取操作時，於該第一井及該第三摻雜區施加一第八電壓，於該第二井及該第二閘極層施加一零電壓，於該第二摻雜區施加一第九電壓，於該第四摻雜區及該第一矽化物層施加一第十電壓，該第八電壓係一正電壓，該第九電壓係等於該零電壓或微幅高於該零電壓，且該第十電壓係介於該零電壓及該第八電壓之間。
  15. 如請求項6所述之記憶體裝置，另包含： 一第一接觸層，接觸於該第一矽化物層，及用以施加一電壓至該對齊層及該第一閘極層； 一第二接觸層，形成於該第二閘極層之上方，接觸於該第二矽化物層，及用以施加另一電壓至該第二閘極層； 一第三接觸層，形成於該第三摻雜區之上方，接觸於該第四矽化物層，及用以施加另一電壓至該第三摻雜區；及 一第四接觸層，形成於該第二摻雜區之上方，接觸於該第三矽化物層，及用以施加另一電壓至該第二摻雜區。
  16. 如請求項1所述之記憶體裝置，其中該對齊層的厚度小於該第一閘極層的厚度之25%，且該阻擋層的厚度大於該第一閘極層的厚度之25%。
  17. 一種半導體製程方法，用於製造一記憶體裝置，該方法包含： 於一井上形成一第一閘極層及一第二閘極層； 沉積產生一阻擋層以覆蓋該第一閘極層及該第二閘極層； 沉積產生一對齊層以覆蓋該阻擋層； 使用一光罩，從而施加一光阻，以移除該對齊層之一部分，使該對齊層之一遺留部分覆蓋一第一區、一第二區、該第一閘極層及該第二閘極層之一部分；及 使用該光阻，從而移除該阻擋層之一部分，使該阻擋層之一遺留部分覆蓋該第一區、該第二區、該第一閘極層及該第二閘極層之該部分； 其中該第一區介於該第一閘極層及該第二閘極層之間，該第二區位於該第一閘極層旁，且該對齊層比該阻擋層、該第一閘極層及該第二閘極層之每一者更薄。
  18. 如請求項17所述之方法，其中該對齊層的厚度小於該第一閘極層的厚度之25%，且該阻擋層的厚度大於該第一閘極層的厚度之25%。
  19. 如請求項17所述之方法，其中該第一閘極層、該第二閘極層及該對齊層係以多晶矽形成。
  20. 如請求項17所述之方法，另包含： 執行一摻雜操作以形成一第一摻雜區、一第二摻雜區及一第三摻雜區； 其中該第一摻雜區係對應於該第一區，該第二摻雜區係對應於該第二區，該第三摻雜區係對應於一第三區，且該第三區係位於該第二閘極層旁。
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