CN111933643A - 存储器装置及其半导体制程方法 - Google Patents

存储器装置及其半导体制程方法 Download PDF

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CN111933643A
CN111933643A CN202010396703.6A CN202010396703A CN111933643A CN 111933643 A CN111933643 A CN 111933643A CN 202010396703 A CN202010396703 A CN 202010396703A CN 111933643 A CN111933643 A CN 111933643A
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layer
voltage
doped region
gate layer
gate
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CN111933643B (zh
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许家荣
陈纬仁
孙文堂
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eMemory Technology Inc
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Abstract

本发明公开了一种存储器装置，包括阱、第一栅极层、第二栅极层、掺杂区、阻挡层及对齐层。所述第一栅极层形成于所述阱上。所述第二栅极层形成于所述阱上。所述掺杂区形成于所述阱中，且位于所述第一栅极层及所述第二栅极层之间。所述阻挡层是形成以覆盖所述第一栅极层、所述掺杂区及所述第二栅极层的部分，用以阻挡电子过度逃逸。所述对齐层是形成于所述阻挡层上及所述第一栅极层、所述掺杂区及所述第二栅极层之所述部分的上方。所述对齐层比所述阻挡层更薄，所述对齐层比所述第一栅极层更薄，且所述对齐层比所述第二栅极层更薄。

Description

存储器装置及其半导体制程方法
技术领域
本发明涉及存储器装置及半导体制程方法，尤指包括对齐层的存储器装置及制造存储器装置的半导体制程方法。
背景技术
对存储器装置而言，保留(retention)时间是评估效能的重要参数。当存储器装置具有更长的保留时间，则可将资料存储的更久，且存储器装置的可靠性与品质会视为更优良。
此外，评估存储器装置的效能时，例如写入、抹除及读取等存储器操作的效能也须一起考虑。存储器操作的效能可根据操作时间、及操作相关的可控度来评估。当可控度较高时，执行存储器操作的失败机率较低。
因此，于本领域，还须可改善存储器装置的保留时间及可控度的解决方案。
发明内容
一种存储器装置，包括阱、第一栅极层、第二栅极层、第一掺杂区、阻挡层及对齐层。所述阱形成于基板中。所述第一栅极层形成于所述阱上。所述第二栅极层形成于所述阱上。所述第一掺杂区形成于所述阱中，及位于所述第一栅极层及所述第二栅极层之间。所述阻挡层覆盖所述第一栅极层、所述第一掺杂区及所述第二栅极层的部分，及用以阻挡电子过度逃逸。所述对齐层形成于所述阻挡层上，及所述第一栅极层、所述第一掺杂区及所述第二栅极层的所述部分的上方。所述对齐层比所述阻挡层更薄，所述对齐层比所述第一栅极层更薄，且所述对齐层比所述第二栅极层更薄。
一种半导体制程方法，用于制造存储器装置。所述半导体制程方法包括于阱上形成第一栅极层及第二栅极层；沉积产生阻挡层以覆盖所述第一栅极层及所述第二栅极层；沉积产生对齐层以覆盖所述阻挡层；使用光罩，从而施加光阻，以移除所述对齐层的部分，使所述对齐层的遗留部分覆盖第一区、第二区、所述第一栅极层及所述第二栅极层的部分；及使用所述光阻，从而移除所述阻挡层的部分，使所述阻挡层的遗留部分覆盖所述第一区、所述第二区、所述第一栅极层及所述第二栅极层的所述部分。其中，所述第一区介于所述第一栅极层及所述第二栅极层之间，所述第二区位于所述第一栅极层旁，所述对齐层比所述阻挡层更薄，所述对齐层比所述第一栅极层更薄，且所述对齐层比所述第二栅极层更薄。
附图说明
图1是实施例中，存储器装置的布局图。
图2是图1的存储器装置的部分剖面图。
图3是图1的存储器装置的部分剖面图。
图4是制造图2的存储器装置的半导体制程方法的流程图。
图5至图8是执行图4的方法的制程示意图。
其中，附图标记说明如下：
100 存储器装置
110 第一栅极层
1110 第一掺杂区
1120 第二掺杂区
1130 第三掺杂区
1140 第四掺杂区
120 第二栅极层
120a 第一部分
120b 第二部分
145 基板
150 第一阱
155 第二阱
160 阻挡层
170 对齐层
180 接触蚀刻停止层
181 第一接触层
182 第二接触层
183 第三接触层
184 第四接触层
190,191,192,193 硅化物层
199 电子
2-2',3-3' 线段
400 半导体制程方法
410,420,430,440,450 步骤
710 第一区
720 第二区
730 第三区
755 光阻
具体实施方式
本文中，当区域或元件(例如A)被描述为位于两区域及/或元件(例如B与C)之间，表示A大约位于B与C之间，且A可能与B及/或C部分接触或部分重迭。同理，当区域或元件(例如A)被描述为位于区域或元件(例如D)旁，表示A大约位于D旁，且A可能与B及/或C部分接触或部分重迭。本文中，当提到元件或层的部分，是指所述元件或所述层的一部分或多部分，而不是全部。
图1是实施例中，存储器装置100的布局图。图2是图1的存储器装置100沿着线段2-2’的部分剖面图。存储器装置100可包括第一阱150、第一栅极层110、第二栅极层120、第一掺杂区1110、阻挡层160、对齐层170、接触蚀刻停止层180、硅化物层190、191、192及193、第二掺杂区1120及第三掺杂区1130。硅化物层190、191、192及193可为自对齐硅化物(Self-aligned silicide，Salicide)层。
第一阱150形成于基板145中，第一栅极层110及第二栅极层120形成于第一阱150上。第一掺杂区1110形成于第一阱150中，且位于第一栅极层110及第二栅极层120之间。
阻挡层160覆盖第一栅极层110、第一掺杂区1110及第二栅极层120之第一部分120a，用以阻挡电子199过度逃逸。阻挡层160可为硅化物阻挡(salicide blocking，SAB)层或阻抗保护氧化物(resist-protection-oxide，RPO)层，用以提高阻抗。
对齐层170可形成于阻挡层160上及第一栅极层110及第二栅极层120之第一部分120之上方。因此，阻挡层160可实质上与对齐层170相互对齐。
对齐层170比阻挡层160更薄，对齐层170比第一栅极层110更薄，且对齐层170比第二栅极层120更薄。
根据实施例，对齐层170的厚度小于第一栅极层110的厚度之25％，且阻挡层160的厚度大于第一栅极层110的厚度之25％。第一栅极层110及第二栅极层120的厚度可相近或约略相同。举例而言，第一栅极层110、阻挡层160及对齐层170的厚度可分别约为(但不限于)2000埃
Figure BDA0002487829500000041
、1000埃及300埃。因此，相较于第一栅极层110、阻挡层160及第二栅极层120，对齐层170更薄。
接触蚀刻停止层180可形成于对齐层170及第二栅极层120之第二部分120b之上，用以阻挡接触层制程的蚀刻。根据实施例，接触蚀刻停止层180可另形成于第二掺杂区1120及第三掺杂区1130之上。
第一栅极层110、第二栅极层120及对齐层170可以多晶硅形成。
如图2所示，硅化物层190可形成于对齐层170及接触蚀刻停止层180之间。硅化物层191可形成于第二栅极层120之第二部分120b及接触蚀刻停止层180之间。由于对齐层170及第二栅极层120可由多晶硅形成，故硅化物层190及191可通过化学反应而形成。同理，硅化物层192可通过化学反应而形成于接触蚀刻停止层180及第二掺杂区1120之间，且硅化物层193可通过化学反应而形成于接触蚀刻停止层180及该第三掺杂区1130之间。硅化物层190、191、192及193可具有导电性且用于导电。
如图2所示，第二掺杂区1120可形成于第一阱150中，且位于第一栅极层110旁。第三掺杂区1130可形成于第一阱150中，且位于第二栅极层120旁。
图3是图1的存储器装置沿着线段3-3’的部分剖面图。如图3所示，第一栅极层110另覆盖第四掺杂区1140之一部分，且第四掺杂区1140形成于第二阱155中。根据实施例，第一阱150可形成于第二阱155中。
根据实施例，第一阱150可为N型阱，且第二阱155可为P型阱。第一掺杂区1110、第二掺杂区1120及第三掺杂区1130可为P型掺杂区。第二阱155可为P型阱或P型基板。第四掺杂区1140可为N型掺杂区。
关于存储器装置100的结构，第一栅极层110可为浮动栅极(称为FG)，第二栅极层120可为选择栅极(称为SG)及字元线(称为WL)，第二掺杂区1120可为位元线(称为BL)，第三掺杂区1130可为来源线(SL)，且第四掺杂区1140可为抹除线(称为EL)。
因为第一栅极层110(浮动栅极)可覆盖第四掺杂区1140(抹除线)的一部分，当要施加电压到第一栅极层110时，该电压可被施加到第四掺杂区1140，第一栅极层110可透过耦合效应接收到该电压。然而，若只靠第四掺杂区1140及第一栅极层110之间的耦合效应来施加电压，效率与可控度是不足的。如图2及图3所示，除了利用耦合效应透过第四掺杂区1140施加电压到第一栅极层110，该电压还可透过第一接触层181、硅化物层190及对齐层170而被耦合而施加到第一栅极层110。因此，操作存储器装置100的效能及可控度可得到改善，操作时间也可缩短。
如图2所示，记忆装置100可还包括第一接触层181、第二接触层182、第三接触层183及第四接触层184。
前述的接触层制程可用以产生第一接触层181、第二接触层182、第三接触层183及第四接触层184。
第一接触层181可接触于硅化物层190，用以施加电压给对齐层170，以使该电压被耦合而施加到第一栅极层110。
第二接触层182可形成于第二栅极层120之上方，接触于硅化物层191，用以施加另一电压至第二栅极层120。
第三接触层183可形成于第三掺杂区1130之上方，接触于硅化物层193，用以施加另一电压至第三掺杂区1130。
第四接触层184可形成于第二掺杂区1120之上方，接触于硅化物层192，及用以施加另一电压至第二掺杂区1120。
第一接触层181至第四接触层184可用以施加电压，从而执行下文表格1所述的存储器操作。
存储器装置100可支援写入操作、正抹除操作、负抹除操作、软式写入操作及读取操作等存储器操作。每项操作中，施加于存储器装置100的电压可如表格1所述。
Figure BDA0002487829500000061
Figure BDA0002487829500000071
(表格1)
如表格1所述，于写入操作时，于第一阱150及第三掺杂区1130施加第一电压V1，于第二阱155及第二掺杂区1120施加零电压(表示为0)，于第二栅极层120施加第二电压V2，且于第四掺杂区1140及硅化物层190施加第三电压V3。第一电压V1及第二电压V2是正电压，第二电压V2是小于或等于第一电压V1，换句话说，可表示为V2≤V1。第三电压V3可于零电压及第二电压V2之间变化。举例来说，V1＝7伏，V2＝V1/2＝3.5伏，且V3可于0伏到3.5伏之间变化。
关于第三电压V3，第三电压V3可于零电压及第二电压V2之间以K步变化，且K是大于零之整数。举例来说，若K＝1，则第三电压V3可以两阶段变化：于第一阶段，第三电压V3可为0伏以避免固定位元(stuck bit)；而于第二阶段，第三电压V3可为3.5伏以使电子进入第一栅极层110(例如浮动栅极)。
如表格1所述，在正抹除操作时，于第一阱150、第二阱155、第二掺杂区1120、第三掺杂区1130、第二栅极层120及硅化物层190施加零电压，且于第四掺杂区1140施加第四电压V4。第四电压V4是正电压。举例来说，第四电压V4可为较高的电压，例如15伏。于正抹除操作时，可将电子从第一栅极层110拉到第四掺杂区1140。
如表格1所述，在负抹除操作时，于第一阱150及第二阱155施加零电压，于第四掺杂区1140施加第四电压V4，且于第二掺杂区1120、第三掺杂区1130、第二栅极层120及硅化物层190施加第五电压V5。第四电压V4是正电压，且第五电压V5是负电压。举例来说，第四电压V4可为较高的电压，例如15伏，且第五电压V5可为-7伏。于另一个例子中，若装置发生崩溃(break down)，可将第四电压V4调整为10伏。
如表格1所述，在软式写入操作时，于第一阱150、第三掺杂区1130及第二栅极层120施加第六电压V6，于第二阱155及第二掺杂区1120施加零电压，且于第四掺杂区1140及硅化物层190施加第七电压V7。第六电压V6及第七电压V7是正电压，且第七电压V7是小于或等于第六电压V6。换句话说，可表示为V7≤V6。举例来说，第六电压V6可为7伏，且第七电压V7可为3.5伏。软式写入操作可允许少量电子进入第一栅极层110，从而准备后续的写入操作。软式写入操作可通过带对带热电子注入(band-to-band hot electron injection)来执行。
如表格1所述，在读取操作时，于第一阱150及第三掺杂区1130施加第八电压V8，于第二阱155及第二栅极层120施加零电压，于第二掺杂区1120施加第九电压V9，且于第四掺杂区1140及硅化物层190施加第十电压V10。第八电压V8是正电压。第九电压V9是等于零电压、或微幅高于零电压。第十电压V10是介于零电压及第八电压V8之间。换句话说，可表示为0<V10<V8。举例来说，第八电压V8可为2.5伏，第九电压V9可为0伏或0.4伏，且第十电压V10可介于0至2.5伏之间。当第十电压V10提高时，从第三掺杂区1130流到第一掺杂区1110的电流可降低。
图4为制造图2之存储器装置100的半导体制程方法400的流程图。图5至图8是执行图4的方法400的制程示意图。如图1到图8所示，方法400可包括以下步骤。
步骤410：于第一阱150上形成第一栅极层110及第二栅极层120；
步骤420：沉积产生阻挡层160以覆盖第一栅极层110及第二栅极层120；
步骤430：沉积产生对齐层170以覆盖阻挡层160；
步骤440：使用光罩(光掩模)，从而施加光阻(光刻胶)755，以移除对齐层170的部分，使对齐层170之遗留部分覆盖第一区710、第二区720、第一栅极层110及第二栅极层120的第一部分120a，其中第一区710介于第一栅极层110及第二栅极层120之间，且第二区720位于第一栅极层110旁；及
步骤450：使用光阻755，从而移除阻挡层160的部分，使阻挡层160的遗留部分覆盖第一区710、第二区720、第一栅极层110及第二栅极层120的第一部分120a。
步骤410至步骤430可对应于图5及图6，步骤440可对应于图7，且步骤450可对应于图8。对齐层170可比阻挡层160、第一栅极层110及第二栅极层120之每一者更薄。
关于步骤410，根据实施例，第一栅极层110及第二栅极层120可形成于第一阱150、间隔层(spacer)及离子注入区上。关于步骤420，根据实施例，阻挡层160可被沉积产生以覆盖第一栅极层110、第二栅极层120、间隔层及离子注入区。
在图7及步骤440中，所述的光罩可用以在规划的区域将光阻755涂布于对齐层170。此可保留对齐层170之一部分，且使用第一化学物质来蚀刻及移除对齐层170的另一部分。
同理，在图8及步骤450中，可使用第二化学物质来蚀刻及移除阻挡层160的一部分。然后，可移除光阻755。
关于图7、图8及步骤440至步骤450，相同的光罩可用以沉积及蚀刻对齐层170及阻挡层160。因此，可不须使用额外光罩，即可制作对齐层170。
关于图2及图5至图8，根据实施例，可执行掺杂操作以形成第一掺杂区1110、第二掺杂区1120及第三掺杂区1130。第一掺杂区1110可对应于第一区710，第二掺杂区1120可对应于第二区720，第三掺杂区1130可对应于第三区730，且第三区730可位于第二栅极层120旁。通过使用阻挡层160，可防止电子从第一栅极层110过度逃逸，故可改善存储器装置110的保留时间。通过使用对齐层170，可改善接触蚀刻停止层180及阻挡层160之间的隔离度，故可提高良率。
此外，通过耦合效应的技术手段，可透过第一接触层181、硅化物层190及对齐层170，施加电压至第一栅极层110。因此，存储器操作的可控度、弹性及效率都可改善。如上所述，实施例提供的存储器装置及半导体制程方法可有效减少本领域的问题。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包括在本发明的保护范围之内。

Claims (20)

1.一种存储器装置，其特征在于，所述存储器装置包括：
第一阱，形成于基板中；
第一栅极层，形成于所述第一阱上；
第二栅极层，形成于所述第一阱上；
第一掺杂区，形成于所述第一阱中，及位于所述第一栅极层及所述第二栅极层之间；
阻挡层，覆盖所述第一栅极层、所述第一掺杂区及所述第二栅极层的第一部分，及用以阻挡电子过度逃逸；及
对齐层，形成于所述阻挡层上，及所述第一栅极层、所述第一掺杂区及所述第二栅极层的所述第一部分的上方；
其中所述对齐层比所述阻挡层更薄，所述对齐层比所述第一栅极层更薄，且所述对齐层比所述第二栅极层更薄。
2.如权利要求1所述的存储器装置，其特征在于，所述第一栅极层、所述第二栅极层及所述对齐层是以多晶硅形成。
3.如权利要求1所述的存储器装置，其特征在于，所述第一栅极层是浮动栅极，且所述第二栅极层是选择栅极。
4.如权利要求1所述的存储器装置，其特征在于，所述存储器装置还包括：接触蚀刻停止层，形成于所述对齐层及所述第二栅极层的第二部分之上，用以阻挡接触层制程的蚀刻。
5.如权利要求4所述的存储器装置，其特征在于，所述存储器装置还包括：
第一硅化物层，形成于所述对齐层及所述接触蚀刻停止层之间；及
第二硅化物层，形成于所述第二栅极层的所述第二部分及所述接触蚀刻停止层之间。
6.如权利要求5所述的存储器装置，其特征在于，所述存储器装置还包括：
第二掺杂区，形成于所述第一阱中，及位于所述第一栅极层旁；
第三掺杂区，形成于所述第一阱中，及位于所述第二栅极层旁；
第三硅化物层，形成于所述接触蚀刻停止层及所述第二掺杂区之间；及
第四硅化物层，形成于所述接触蚀刻停止层及所述第三掺杂区之间。
7.如权利要求6所述的存储器装置，其特征在于，所述第一阱是N型阱，所述第一掺杂区、所述第二掺杂区及所述第三掺杂区是P型掺杂区。
8.如权利要求6所述的存储器装置，其特征在于，所述第一栅极层另覆盖第四掺杂区的部分，所述第四掺杂区形成于第二阱中，所述第一栅极层是浮动栅极，所述第二栅极层是选择栅极及字元线，所述第二掺杂区是位元线，所述第三掺杂区是来源线，且所述第四掺杂区是抹除线。
9.如权利要求8所述的存储器装置，其特征在于，在写入操作时，于所述第一阱及所述第三掺杂区施加第一电压，于所述第二阱及所述第二掺杂区施加零电压，于所述第二栅极层施加第二电压，于所述第四掺杂区及所述第一硅化物层施加第三电压，所述第一电压及所述第二电压是正电压，所述第二电压是小于或等于所述第一电压，且所述第三电压是于所述零电压及所述第二电压之间变化。
10.如权利要求9所述的存储器装置，其特征在于，所述第三电压是于所述零电压及所述第二电压之间以K步变化，且K是大于零的整数。
11.如权利要求8所述的存储器装置，其特征在于，在正抹除操作时，于所述第一阱、所述第二阱、所述第二掺杂区、所述第三掺杂区、所述第二栅极层及所述第一硅化物层施加零电压，于所述第四掺杂区施加第四电压，且所述第四电压是正电压。
12.如权利要求8所述的存储器装置，其特征在于，在负抹除操作时，于所述第一阱及所述第二阱施加零电压，于所述第四掺杂区施加第四电压，于所述第二掺杂区、所述第三掺杂区、所述第二栅极层及所述第一硅化物层施加第五电压，所述第四电压是正电压，且所述第五电压是负电压。
13.如权利要求8所述的存储器装置，其特征在于，在软式写入操作时，于所述第一阱、所述第三掺杂区及所述第二栅极层施加第六电压，于所述第二阱及所述第二掺杂区施加零电压，于所述第四掺杂区及所述第一硅化物层施加第七电压，所述第六电压及所述第七电压是正电压，且所述第七电压是小于或等于所述第六电压。
14.如权利要求8所述的存储器装置，其特征在于，在读取操作时，于所述第一阱及所述第三掺杂区施加第八电压，于所述第二阱及所述第二栅极层施加零电压，于所述第二掺杂区施加第九电压，于所述第四掺杂区及所述第一硅化物层施加第十电压，所述第八电压是正电压，所述第九电压是等于所述零电压或微幅高于所述零电压，且所述第十电压是介于所述零电压及所述第八电压之间。
15.如权利要求6所述的存储器装置，其特征在于，所述的存储器装置还包括：
第一接触层，接触于所述第一硅化物层，及用以施加电压至所述对齐层及所述第一栅极层；
第二接触层，形成于所述第二栅极层的上方，接触于所述第二硅化物层，及用以施加另一电压至所述第二栅极层；
第三接触层，形成于所述第三掺杂区的上方，接触于所述第四硅化物层，及用以施加另一电压至所述第三掺杂区；及
第四接触层，形成于所述第二掺杂区的上方，接触于所述第三硅化物层，及用以施加另一电压至所述第二掺杂区。
16.如权利要求1所述的存储器装置，其特征在于，所述对齐层的厚度小于所述第一栅极层的厚度的25％，且所述阻挡层的厚度大于所述第一栅极层的厚度的25％。
17.一种半导体制程方法，用于制造存储器装置，其特征在于，所述半导体制程方法包括：
于阱上形成第一栅极层及第二栅极层；
沉积产生阻挡层以覆盖所述第一栅极层及所述第二栅极层；
沉积产生对齐层以覆盖所述阻挡层；
使用光罩，从而施加光阻，以移除所述对齐层的部分，使所述对齐层的遗留部分覆盖第一区、第二区、所述第一栅极层及所述第二栅极层的部分；及
使用所述光阻，从而移除所述阻挡层的部分，使所述阻挡层的遗留部分覆盖所述第一区、所述第二区、所述第一栅极层及所述第二栅极层的所述部分；
其中所述第一区介于所述第一栅极层及所述第二栅极层之间，所述第二区位于所述第一栅极层旁，所述对齐层比所述阻挡层更薄，所述对齐层比所述第一栅极层更薄，且所述对齐层比所述第二栅极层更薄。
18.如权利要求17所述的半导体制程方法，其特征在于，所述对齐层的厚度小于所述第一栅极层的厚度的25％，且所述阻挡层的厚度大于所述第一栅极层的厚度的25％。
19.如权利要求17所述的半导体制程方法，其特征在于，所述第一栅极层、所述第二栅极层及所述对齐层是以多晶硅形成。
20.如权利要求17所述的半导体制程方法，其特征在于，所述半导体制程方法还包括：
执行掺杂操作以形成第一掺杂区、第二掺杂区及第三掺杂区；
其中所述第一掺杂区是对应于所述第一区，所述第二掺杂区是对应于所述第二区，所述第三掺杂区是对应于第三区，且所述第三区是位于所述第二栅极层旁。
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