200952300 九、發明說明： [發明所屬之技術領域】 本發明係與靜電放電防護（ESD protection)有關，女社 應用於採用先進製程元件之靜電放電防護電路之靜電放電谓則 (ESD detection)電路及其相關方法。 【先前技術】 ❹ 隨著科技進步，積體電路製程技術也隨之不斷精進。如熟悉 積體電路技術者所知，各種電子電路可集積/成形於晶/ 上，而為了要使晶片能接收外界的電壓源（例如偏壓電 源）’並能與外界其他電路/晶片交換資料，晶片上會設有 導電的接墊(pad)。譬如說’為了傳輸偏壓電壓，晶片上可 設有電源接墊(鄉―）。除此之外，在晶片上也設有訊 ❹號接墊(s—d)，亦即輸人/輸出塾⑽_，用以接 收輸入訊號及/或發出輸出訊號。 這些導電的接魏使W得叫外界其他電路/晶片 連接。然而，f晶片在封裝、測試、運輸、加工、等過程 I，這些接墊也很料因為與外界的靜電電源接觸，而將 靜電的不當電力傳導至晶片内邱 鬥邛，並進而導致晶片内部電 路的抽毀，這種現㈣為所謂的靜電放f(ESD， 7 200952300200952300 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to electrostatic discharge protection (ESD detection), which is applied to an electrostatic discharge precaution (ESD detection) circuit of an electrostatic discharge protection circuit using advanced process components and Its related methods. [Prior Art] ❹ With the advancement of technology, the integrated circuit process technology has also continued to improve. As is known to those skilled in the art of integrated circuits, various electronic circuits can be integrated/formed on the crystal/in order to enable the wafer to receive an external voltage source (such as a bias supply) and exchange data with other circuits/wafers from the outside. A conductive pad is provided on the wafer. For example, in order to transmit a bias voltage, a power pad (township) can be placed on the wafer. In addition, the chip is also provided with a signal pad (s-d), that is, an input/output port (10)_ for receiving input signals and/or outputting output signals. These conductive connections are called external circuit/wafer connections. However, the f-wafer is in the process of packaging, testing, transportation, processing, etc., and these pads are also expected to be in contact with the external electrostatic power source, and the improper electric power of the static electricity is transmitted to the inside of the wafer, and thus the inside of the wafer. The demolition of the circuit, this is now (four) for the so-called electrostatic discharge f (ESD, 7 200952300
Electro-Static Discharge)。因此，用來保護積體電路免受靜電 放電損害之靜電放電保護電路(ESD protection circuit)，也因此隨著 積體電路製程之進步而變得更加重要。 - 通常在晶片的各接墊之間會設置有靜電放電防護電 路。此靜電放電防護電路的基本功能是，當晶片的兩接墊 間誤觸靜電電源時，靜電放電防護電路可在兩接墊間導通 ❹一個低阻抗的電流路徑，使靜電電源放電的電流能優先從 此一電流路徑流過而不會流入至晶片的其他内部電路；這 樣一來，就能保護晶片中的其他内部電路不受靜電放電影 響或由於大量的靜電放電電流（ESDcurrent)而導致損壞。 一般而言，一靜電放電防護電路係由一靜電放電（暫態） 偵測電路（ESD transition detection circuit)以及一電源籍 制（power clamp)電路所構成。請參閱第i圖，第ι圖所 示為習知靜電放電防護電路的方塊示意圖。如第i圖所 ❹tf’靜電放電防護電路100包含有一靜電放電侦測電路⑽ 以及一電源粉制電路12〇。如此之外，此靜電放電電路⑽ 係耦接於兩電源接塾（powerpad) Vdd (電壓供應端）與 Vss (接地端）孓間。 ^ 然而’隨著半導體製程的演進’使用較小尺寸的電晶體元件 來降低成本已成為各種電路設計技術中的基本需求。隨著半導體 製程由點-八製程、點一二製程一路演進至六十五奈米，或所謂 8 200952300 的奈米先進製^_scaieprocess);半導體元件的閘極氧化層 (gate oxide)厚度也隨之日益趨薄。除此之外，基於降低整體電^面 積及成本的考量…般靜電錢賴電財的靜電放電_電路 capacitor，亦稱 所具有之電容元件普遍採用金屬氧化層電容(M〇s 之為金氧半導體電晶體電容)來加以實現，而非使用—般傳統的電 容元件。 〇 請參閱第2圖’第2圖所示為另一習知靜電放電偵測電路200 的電路架構示意圖。如第2圖所示，靜電放電_電路包含 有-容阻電路210以及-反相電路22〇，用以產生一靜電放電觸 發机號Itrigger，其中當靜電放電偵測電路2〇〇偵測到靜電放電事件 (ESD event)時.，靜電放電觸發訊號^财會由低邏輯準位轉換 至高邏輯準似啟動後續的靜電放電防護元件（例如電源符制電 路）。靜電放電偵測電路200係連接於一第一電源接墊（亦即 ❹端）以及-第二電源接塾（亦即Vss端）之間。在第2圖中，容 阻電路210包含有-阻抗元件211以及一金氧半導體電晶體電 容(厘〇8哪3(^腦)212，而反相電路220係由一：^型金氧 半導體電晶體222以及一 p型金氧半導體電晶體221所構 成。 « 然而，在利用由先進製程（nan〇SCalepr〇Cess)所形成之金屬 氧化層電容時，其閘極氧化層所具有之較薄厚度往往會使靜電偵 測電路產生嚴重的漏電流，此漏電流可能使得靜電放電防護電路 200952300 到其正 產生誤動作（mammetiGn)，使其在正常工作料下無法達 常邏輯，進而產生更嚴重的漏電流。 、 而靜電防護電路之漏電流的現象絲因於靜電放職测電路 '之容阻電路（請參閱第2圖）中的金氧半導體電晶體電容212 採用了先進製程的薄氧化層元件，此時，金氧半導體電晶 體電容2U的閘極端往往會出現大量的穿遂電流（加刪㈣ ❹C職nt)而導致晶片於正常操作時容阻電路21〇與反相電路 220間之一連接端（其耦接於p型金氧半導體電晶體221之一 控制端與N型金氧半導體電晶體222之—控制端）的電壓相 對於P型金氧半導體電晶體221之一第一連接端（其耦接 於第一電源接墊）的電壓值而言為一個相對低的電壓，因 此忒P型金氧半導體電晶體即導通而造成靜電放電觸發訊 號1trigger由低邏輯準位轉換至高邏輯準位，因此便錯誤地啟動 ❹後續的靜電放電防護元件（例如電源箝制電路）。換句話說， 虽靜電放電事件並未發生時，由於金氧半導體電晶體電容 212的穿遂電流將拉低連接端23〇(其連結容阻電路21〇以 及反相電路220)的電壓值，因而導致反相電路22〇於晶 片正、吊操作下無法有效地關閉，進而導致在兩電源接墊 ' (VDD端與VSS端之間）有大量的漏電流產生。因此本發 明係提供新穎的靜電放電偵測電路，由於利用新的電路架 * 構，即使在採用先進製程之薄氧化層元件的狀況下，仍能 改善靜電放電防護電路於正常操作時的漏電流現象。 200952300 【發明内容】 的具有不同電一電放電 fl 《靜電放電翻電路於先進^知技射由於靜電放電防護電路 點。本發明之靜電放電x秩之下會產生大量漏電流現象的缺 地，而藉由使㈣壓電^料’其容阻電路並未直接接 體電晶體電容兩端的壓差，便可減少容阻電路之金氧半導 偵測電路的漏電流現象。，從而改善先進製程中靜電放電 根據本發明之—實扩 電路。該靜電放電_^ ’其係揭露―種靜電放電债測 第二電源接墊、包含有：略包含有：-第-電源接墊、-陡電路、一觸發電路=F 且抗元件以及一電容元件之一容 二連接端。該第一電源：：壓電路、-第-連接端與-第 讀第二電源接墊係用係用以接收-第-供應電壓; 二供應電壓；該容阻電跟不同於該第-供應電壓之-第 綠接墊與該第—連接 ^抗元件，聽接於該第一電 〜端點與該第二端點之^間；該電容聽，其_於該第 竦接墊、該第二電、、，a，該觸發電路，耦接於該第一電 、端點與該第二端及該容阻電路，用來依據該第 銳；以及該偏壓電路，知藥準位來產生一靜電放電觸發訊 稿接於該第一電源接墊以及該第二 200952300 端點 電源接墊之間，用以提供一偏壓電壓予該第 根據本發明之另一實施例，其係揭露一 電_之綠，财法包含有：提供—容阻電路，射^靜電放 路内包含有-阻抗元树—_件，爾元件，係= :第-供應電壓與-第—端點之間，而該電容树，輪科第 ❹ 第二端點之間，其_二端點未直接連接於不同於 «亥第供應電壓之一第二供應電壓； ' '靜電放電觸發 依據该第-端點與該第二端點之電壓準位來產生 訊號；以及提供—偏壓電壓至該第二端點。 藉由上述之電路設計與相關方法，可解決先進製程下 電偵測電路由於採㈣氧化層金氧半導體電晶體元件而導致 正常操作下的漏電流問題。 致 【實施方式】 特書及後續的申請專利範圍當中使用了某些詞彙來指稱 合疋、7L。所屬領域巾具有通常知識者應可贿，製造商可处 >1=不同的名縣稱呼同—個元件。本說财及後續的申請專利 來作為區分元件的方式，而是以元件在功 中所提及Μ「/ 77 _則。錢篇綱書及後續的請求項當 、匕含」係為一開放式的用語，故應解釋成「包含但 12 200952300 不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電 氣連接手段。因此，若文中描述一第一裝置耦接於一第二裝置， 則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝 ' 置或連接手段間接地電氣連接至該第二裝置。 請參閱第3圖，第3圖所示為本發明靜電放電偵測電路之一 第一實施例的電路架構示意圖。如第3圖所示’靜電放電偵測電 ❹ 路300係耦接於一第一電源接墊301與一第二電源接墊302之間， 在本實施例中，第一電源接墊3〇1為一 Vdd接墊（用以提供第一 供應電壓vDD)’而該第二電源接墊302為一 Vss接墊（用以提供 第二供應電壓Vss ’例如接地電壓）。靜電偵測電路3⑻包含有一 偏壓電路（biascircuit) 310、一容阻電路(RCcircuit)320以及一觸 發電路330。在本說明書後續的說明之中，靜電放電偵測電路之容 阻電路中的電容元件皆以金氧半導體電晶體電容來加以實 施，以及容阻電路中的阻抗元件係以一電阻(resistance；^件來加 以實施。 除此之外’靜電放電偵測電路之觸發電路中係包含有不同導 電型之金氧半導體電晶體元件，也就是說，觸發電路中同時採用 、了 N型以及P型之金氧半導體電晶體元件。再者，本發明之電路 架構以及糊技術係採用先進製程(_ _ρΐΌ㈣之元件 來加以實施。請注意，上述僅作為範例說明之用，並不為本發明 的限制條件之一。 13 200952300 ❹ ❹ 請參閱第3圖，在本實施例中，容阻電路32〇包含有—阻抗 元件321以及一電容元件322，而阻抗元件321為一電阻，電容1 件322係以採用先進製程(nan〇 scale)之金氧半導體電晶體電容 (MOS capacitor)來加以實施。觸發電路33〇包含有一第—金氧 半導體電晶體331以及一第二金氧半_電晶體332，對第—金 1 半導體電晶體331而言，其一控制端（閉極）祕於一第—端點 Na ’其-第-連接端G原極）祕於第一電源接塾观，以及其 :第二連接端（祕）用以輸出靜電放電觸發訊號^。給後續的 =電放電_元件（例如電源闕)辦靜較電事件發生 k旁通靜電放電電流’如圖所示，靜電放電觸發訊號^係由端 =所輸出。此外’對於觸發電路33()之第二金氧半導體電晶體 而言’其一控制端（亦即間極）输於-第二端點Nb，並一 =連接端（沒極）輕接於第一金氧半導體電晶細之第I連 士： A 乂及'第一連接端(源極)耦接於第二電源接墊302。在 體實半導體電晶體331係以一p型之金氧半導 氧半二電‘金氧半導體電晶體332則是以—N型之金 脚兩錢彻電晶細、_為 不同導電叙錢半轉電Μ。 圖所5第/圖’相較於f知靜電放電侧電路（如第2 於本:劇丨明靜電放電_電路綱另包含有偏M電路310， 本實施射，_路3㈣為—_路（讀agedivide〇， 200952300 用以根據第一電源端301與第二電源端3〇2之供應電壓（例如Vdd 以及Vss)提供容阻電路320之電容元件322下端（亦即第二端點 Nb) -個高於第二電源接塾3〇2之供應電壓（例如Vss)的偏壓 ' 電壓，也就是說，電容元件322兩端間的跨壓分別為第一端點1^ - 以及第二端點％之間的電壓差，此電壓差會小於第一電源接墊 301的供應電壓（例如Vdd)以及第二電源接塾搬的供應電壓⑽ 如vss)間的電壓差。在本實施例中，偏壓電路係以五個具有 ❹二極體接法形式（diode-connected )的電晶體元件3丨丨來加以實施， 使得第二端點Nb的電壓值為Vdd和％之間的—個分壓（亦即 >-D)，不過分壓電路的架構與採用之元件並不為本發明的限 制條件之一，任何其他可產生分壓之電路架構皆屬於本發明的設 計變化之-；而分壓元件的數目亦不為本發明的限制條件之一。 靜電放電侧電路於正常操作下的電路狀態以及靜電放 ❹ t事件發生時的電路狀態將於後續之揭露巾詳細說明。 當一靜電放電事件發生時，第一 ^ 昂電源接墊301與第二 電源接墊302之間的跨壓条谑4古 _ ㈣急遽升向，對於第一金氧半導體電 日日體331而言，由於容阻電路32 <電谷兀件322(金氧丰壤 體電晶體電容)來不及快速反應， ^ ^ 蚁於第一金氧半導體電晶體 331搞接至第一電源接塾3〇】之篱一 弟連接端的電壓值將高於第 一連接端Na之電壓而使得第一金氧 孔手導體電晶體331導通並產生 一靜電放電觸發訊號1吨（亦即靜雷 土 p靜電放電觸發訊號會由低邏 15 200952300 輯準位轉換至高邏輯準位）。 容 端點Na來說，由於電 e U丨丁 木+及對電壓皂 〜、升進仃相對應的反應，使得第 埏.、沾Na的電壓會暫時維 CM* r -fr P ^ . 符於第—電源接墊;301原本之電 域值（亦即趨近vDD)。由 ^ 由於弟一金氧半導體電晶體331因為 接端的兩端電壓差而導通，使端點*的電壓 顯觸發靜電放電防護電路之電源箝制電路（未 顯不於圖中），使得電 ❹ ❹ t* is-^ '、扭制電路導通一低阻抗電流路徑以 ^導靜電放電電流來達成靜電防護的目的。 =電放電制電路3⑼在正f運作時 ，偏壓電路310 槌供分壓電壓予第二端 .., 味點Nb(亦即電容元件322之一端）， 使得第二端點Nb偏壓於? ^ 外一個大於第二電源接墊302之電壓 ^即VSS)的較高電―準。如第3_示，於正常操 之下纟於偏壓電路3ι〇所提供的偏壓電壓，使得第二 化點Nb之電壓可導诵铪 λ ^ , -、u 通第二金虱半導體電晶體332(第二金 乳半導體電晶體332传 从、 型金氧半導體電晶體332元 件），此時因為第二端釣_ χτι Λ 鳊點Nb之電壓為一較高位準（相較於 弟二電源接墊302之雷厭、隹，、 ^ — 电愿準位）’經由適當的分壓設計，第 ^點Na與第二端點叫間的跨壓於正常模式之下不大， 口此先進製程之金氧半導體電晶體電容（亦即電容元件 ^2)的閘極漏電流現急 凡象也隨之改善，並使得第一端點Na 之電壓得以維持在一個、& ^ m , U近似於第—電源接墊301之供應電 VDD)的狀恶’由於第一金氧半導體電晶體331係為 16 200952300 一 P型金氧半導體電晶體’故此一接近於VDD之電壓將會 關閉第一金氧半導體電晶體331。換句話說’由於先進製 程之金氧半導體電晶體電容（亦即電容元件322)兩端（第 一端點Na與第二端點Nb)之跨壓減少，進而可有效地關 閉正常操作狀態下的第一金氧半導體電晶體331，避免因 為漏電流而不當產生靜電放電觸發訊號而觸發電源箝制電 路，因此，可防止靜電放電防護電路產生誤動作，避免處 在不正常邏輯狀態。 請同時參閱第4圖與第3圖，第4圖為本發明第一實 施例之靜電放電偵測電路模擬靜電放電事件發生時觸發電 流的示意圖。如第4圖所示，此模擬係固定靜電放電偵測 電路300之容阻電路32〇的rC時間常數（RC c〇nstant)Electro-Static Discharge). Therefore, the ESD protection circuit used to protect the integrated circuit from electrostatic discharge becomes more important as the integrated circuit process progresses. - An ESD protection circuit is usually provided between the pads of the wafer. The basic function of the ESD protection circuit is that when the two pads of the chip accidentally touch the electrostatic power source, the ESD protection circuit can conduct a low-impedance current path between the two pads, so that the current discharged by the electrostatic power source can be preferentially From this, a current path flows without flowing into other internal circuits of the wafer; thus, other internal circuits in the wafer can be protected from electrostatic discharge or damage due to a large amount of electrostatic discharge current (ESDcurrent). In general, an ESD protection circuit consists of an ESD transition detection circuit and a power clamp circuit. Please refer to the i-th diagram, which is shown as a block diagram of a conventional electrostatic discharge protection circuit. As shown in Fig. i, the ftf' electrostatic discharge protection circuit 100 includes an electrostatic discharge detecting circuit (10) and a power powder circuit 12〇. In addition, the electrostatic discharge circuit (10) is coupled between two power pads Vdd (voltage supply terminal) and Vss (ground terminal). ^ However, the use of smaller sized transistor components to reduce cost as the evolution of semiconductor processes has become a fundamental requirement in various circuit design techniques. As the semiconductor process progresses from point-eight process, point-two process to sixty-five nanometers, or so-called 8200952300 nano-advanced system ^_scaieprocess); the gate oxide thickness of the semiconductor component also It is getting thinner. In addition, based on the reduction of the overall electrical area and cost considerations, the electrostatic discharge _ circuit capacitor, also known as the capacitive components commonly used metal oxide layer capacitors (M 〇s for the gold oxide Semiconductor transistor capacitors are implemented instead of using conventional capacitive components. 〇 Referring to FIG. 2', FIG. 2 is a schematic diagram showing the circuit structure of another conventional electrostatic discharge detecting circuit 200. As shown in FIG. 2, the ESD_circuit includes a capacitance-resistance circuit 210 and an inverter circuit 22A for generating an electrostatic discharge trigger No. Itrigger, wherein the ESD detection circuit 2 detects During an ESD event, the ESD trigger signal is converted from a low logic level to a high logic level to initiate subsequent ESD protection components (such as a power supply circuit). The ESD detecting circuit 200 is connected between a first power supply pad (i.e., a terminal end) and a second power supply port (i.e., a Vss end). In FIG. 2, the resistance circuit 210 includes a -impedance element 211 and a MOS transistor (capsule 8 which is 3), and the inverter circuit 220 is a type of MOS. The transistor 222 and a p-type MOS transistor 221 are formed. « However, when the metal oxide layer capacitor formed by the advanced process (nan〇SCalepr〇Cess) is utilized, the gate oxide layer is thinner. The thickness often causes the electrostatic detection circuit to generate a serious leakage current. This leakage current may cause the ESD protection circuit 200952300 to malfunction (mammetiGn), which makes it impossible to reach the normal logic under normal working conditions, which leads to more serious Leakage current. The leakage current of the ESD circuit is due to the MOS transistor capacitor 212 in the electrostatic discharge test circuit (see Figure 2). The thin oxide layer of the advanced process is used. Component, at this time, the gate terminal of the MOS transistor capacitor 2U tends to have a large amount of through-current (additional deletion (4) ❹C job nt), resulting in the chip in the normal operation of the resistance circuit 21 反相 and reversed One of the 220 terminals (which is coupled to the control terminal of one of the p-type MOS transistor 221 and the control terminal of the N-type MOS transistor 222) has a voltage relative to the P-type MOS transistor 221 The voltage value of a first connection terminal (which is coupled to the first power supply pad) is a relatively low voltage, so that the P-type MOS transistor is turned on to cause an electrostatic discharge trigger signal 1trigger from a low logic The bit transitions to a high logic level, thus erroneously activating the subsequent ESD protection component (eg, a power supply clamp circuit). In other words, although the electrostatic discharge event does not occur, due to the MOS transistor transistor 212 being worn The current will pull down the voltage value of the connection terminal 23〇 (which is connected to the resistance circuit 21〇 and the inverter circuit 220), thereby causing the inverter circuit 22 to be effectively turned off under the positive and negative operation of the wafer, thereby causing the two power sources to be turned on. The pad 'between the VDD terminal and the VSS terminal has a large amount of leakage current. Therefore, the present invention provides a novel electrostatic discharge detecting circuit, which utilizes a new circuit frame structure, even in the mining Under the condition of the thin oxide component of the advanced process, the leakage current of the ESD protection circuit during normal operation can still be improved. 200952300 [Invention] The electric discharge has different electric discharges. Because of the electrostatic discharge protection circuit point, the electrostatic discharge x rank of the present invention generates a large amount of leakage current, and the (four) piezoelectric material is not directly connected to the transistor capacitance. The voltage difference between the terminals can reduce the leakage current of the MOS circuit of the capacitance resistance circuit, thereby improving the electrostatic discharge in the advanced process according to the present invention. The electrostatic discharge _^ 'is revealed ― The second power supply pad of the electrostatic discharge debt test includes: a first-power supply pad, a steep circuit, a trigger circuit=F, and an anti-component and a capacitor element. The first power source::voltage circuit, the -first connection end and the -read second power supply connection system are used to receive the -first supply voltage; the second supply voltage; the tolerance resistance is different from the first a green voltage pad of the supply voltage and the first connection element are connected between the first electrical end point and the second end point; the capacitance is heard, and the yoke is The second circuit, the a, the trigger circuit is coupled to the first power, the end point and the second end, and the resistance circuit for determining the sharpness; and the bias circuit Positioning an electrostatic discharge triggering signal between the first power supply pad and the second 200952300 terminal power supply pad for providing a bias voltage to the second embodiment according to the present invention. It reveals a green _ green, the financial law contains: provide - the resistance circuit, the injection ^ static discharge contains - impedance element tree - _ pieces, element, system =: first - supply voltage and - first Between the endpoints, and the capacitor tree, between the second endpoint of the wheelset, its _ two endpoints are not directly connected to a second supply different from the one of the supply voltages Voltage; '' according to the second electrostatic discharge trigger - to generate a signal terminal and a voltage level of the second terminal; and providing - a bias voltage to the second endpoint. With the above circuit design and related methods, it is possible to solve the problem of leakage current under normal operation due to the (4) oxide layer MOS transistor component in the advanced process. [Implementation] Some words are used in the special book and subsequent patent applications to refer to the combination, 7L. The person in the field has the usual knowledge that the person should be bribed, and the manufacturer can be used to >1=different counties to call the same element. The patent application and the subsequent patent application are used as a means of distinguishing components, but the components mentioned in the work are "/ 77 _. The money book and subsequent request items are included." The terminology should be interpreted as "including but 12 200952300 is not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or electrically connected to the second device indirectly through other devices or connecting means. Device. Please refer to FIG. 3. FIG. 3 is a schematic diagram showing the circuit structure of the first embodiment of the electrostatic discharge detecting circuit of the present invention. As shown in FIG. 3, the ESD detecting circuit 300 is coupled between a first power pad 301 and a second power pad 302. In this embodiment, the first power pad 3〇 1 is a Vdd pad (to provide a first supply voltage vDD)' and the second power pad 302 is a Vss pad (to provide a second supply voltage Vss 'eg, a ground voltage). The static electricity detecting circuit 3 (8) includes a bias circuit 310, a RC circuit 320, and a trigger circuit 330. In the following description of the specification, the capacitive components in the capacitance-resistance circuit of the ESD detection circuit are implemented by a MOS transistor, and the impedance component in the resistance circuit is a resistor (resistance; In addition, the trigger circuit of the ESD detection circuit includes MOS transistors with different conductivity types, that is, the trigger circuit uses N-type and P-type simultaneously. The MOS transistor transistor component. Furthermore, the circuit architecture and paste technology of the present invention are implemented by using an advanced process (_ _ ρ ΐΌ (4) component. Please note that the above description is for illustrative purposes only and is not a limitation of the present invention. 13 200952300 ❹ ❹ Please refer to FIG. 3 , in this embodiment, the resistance circuit 32 〇 includes an impedance element 321 and a capacitance element 322 , and the impedance element 321 is a resistor, and the capacitor 1 322 is The MOS capacitor is implemented by a nan 〇 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The transistor 331 and a second MOS transistor 332, for the first gold semiconductor transistor 331, a control terminal (closed) is secreted from a first terminal - terminal Na 'its - first terminal G original pole) secrets the first power connection, and its: the second connection end (secret) is used to output the electrostatic discharge trigger signal ^. The subsequent = electric discharge_component (such as power supply) static and electrical events The k-bypass electrostatic discharge current occurs as shown in the figure, the electrostatic discharge trigger signal is output by the terminal =. In addition, 'for the second MOS transistor of the trigger circuit 33 (), one of the control terminals (also The inter-electrode is transferred to the second terminal Nb, and the one connection terminal (the non-polar) is lightly connected to the first metallurgical semiconductor fine crystal first I-Lian: A 乂 and 'the first connection end (source) ) is coupled to the second power pad 302. The bulk semiconductor transistor 331 is a p-type gold-oxygen semi-conducting oxygen half-electric 'metal oxide semiconductor transistor 332 is -N-type gold feet two money The electric crystal is fine, _ is a semi-rotating electric 不同 for different conductive Μ 。. Figure 5 / Figure 'Compared to the f-electrostatic discharge side circuit (such as the second in this: Drama Ming Jing The electric discharge _ circuit outline further includes a bias M circuit 310, the present embodiment, _ road 3 (four) is -_ road (read agedivide 〇, 200952300 for supplying voltage according to the first power terminal 301 and the second power terminal 3 〇 2 ( For example, Vdd and Vss) provide the lower end of the capacitive element 322 of the capacitive circuit 320 (ie, the second terminal Nb) - a bias voltage that is higher than the supply voltage (eg, Vss) of the second power supply port 3〇2, That is, the voltage across the capacitive element 322 is the voltage difference between the first terminal 1^- and the second terminal%, respectively, and the voltage difference is smaller than the supply voltage of the first power pad 301 (for example, Vdd). And the voltage difference between the supply voltage (10) such as vss) of the second power supply. In this embodiment, the biasing circuit is implemented in five diode elements having a diode-connected form such that the voltage value of the second terminal Nb is Vdd and a partial voltage between % (ie, >-D), but the architecture of the voltage divider circuit and the components used are not one of the limitations of the present invention, and any other circuit architecture that can generate a voltage divider belongs to The design of the present invention varies - and the number of voltage dividing elements is not one of the limitations of the present invention. The circuit state of the ESD side circuit under normal operation and the circuit state at the time of the electrostatic discharge event will be described in detail later. When an electrostatic discharge event occurs, the cross-pressing strip between the first power supply pad 301 and the second power supply pad 302 is rushed upward, for the first MOS semiconductor day 331 In other words, since the resistance circuit 32 < the electric valley element 322 (the gold oxide earth crystal transistor capacitance) is too late to react quickly, the ^ ant is connected to the first power supply 331 through the first MOS transistor 331. The voltage value at the connection end of the fence is higher than the voltage of the first connection terminal Na, so that the first gold-oxygen hole hand conductor transistor 331 is turned on and generates an electrostatic discharge trigger signal of 1 ton (ie, static thunder earth p electrostatic discharge) The trigger signal will be converted from low logic 15 200952300 level to high logic level). For the end point Na, due to the reaction of the electric e U 丨丁木+ and the voltage soap~, 升进仃, the voltage of the 埏., 沾Na will temporarily maintain the CM* r -fr P ^ . In the first - power pad; 301 original electrical domain value (that is, approaching vDD). Since the MOS-MOS transistor 331 is turned on because of the voltage difference between the terminals, the voltage at the terminal* is triggered to trigger the power-clamp circuit of the ESD protection circuit (not shown), so that the ❹ t* is-^ ', the twisting circuit conducts a low-impedance current path to guide the electrostatic discharge current to achieve the purpose of electrostatic protection. When the electric discharge system 3 (9) is operating in positive f, the bias circuit 310 is configured to supply a voltage to the second terminal.., the taste point Nb (that is, one end of the capacitive element 322), so that the second terminal Nb is biased. A higher power level than the voltage of the second power pad 302, that is, VSS, is outside the ?. As shown in the third example, under the normal operation, the bias voltage provided by the bias circuit 3 〇 is such that the voltage of the second localization point Nb can be guided by λ ^ , -, u through the second metal semiconductor The transistor 332 (the second gold-semiconductor transistor 332 is transmitted from the MOS transistor 332 element), at this time, because the voltage of the second end fishing _ χ τ Λ N Nb is a higher level (compared to the younger brother) The second power supply pad 302 has a thunder, 隹,, ^ — electric power level. 'With proper voltage division design, the cross-pressure between the second point Na and the second end point is not large under the normal mode. The gate leakage current of this advanced process MOS transistor (ie, the capacitor element ^2) is also improved, and the voltage of the first terminal Na is maintained at one, & ^ m , U is similar to the supply voltage VDD of the first power pad 301. Since the first MOS transistor 331 is 16 200952300, a P-type MOS transistor, the voltage close to VDD will be The first oxynitride transistor 331 is turned off. In other words, the voltage across the MOS transistor (ie, the capacitive element 322) of the advanced process (the first terminal Na and the second terminal Nb) is reduced, thereby effectively closing the normal operating state. The first MOS transistor 331 avoids triggering the power supply clamping circuit due to the leakage current and the electrostatic discharge triggering signal. Therefore, the electrostatic discharge protection circuit can be prevented from malfunctioning and avoiding an abnormal logic state. Please refer to FIG. 4 and FIG. 3 at the same time. FIG. 4 is a schematic diagram of the trigger current when the electrostatic discharge detecting circuit of the first embodiment of the present invention simulates an electrostatic discharge event. As shown in Fig. 4, this simulation is the rC time constant of the capacitive circuit 32〇 of the fixed electrostatic discharge detecting circuit 300 (RC c〇nstant)
為50ns以及固定第一金氧半導體電晶體331之通道長度(L) 為〇.12um，而調變第一金氧半導體電晶體331之通道寬度 (W)而產生的數據(請參考曲線1〜曲線7)。請參閱第5圖與 第3圖’第5圖為本發明第一實施例之靜電放電偵測電路 模擬正常操作狀態（normal operation )下漏電流狀態的示 =雷=5圖所示，此模擬係當第-電源端3〇1之第一 路300中漏電情形=固定為1伏特時，靜電放電制電 、數據(請參考曲線1〜曲線2)。 當積體電路設計中需要採用先進 由前述之财％楚得知， 17 200952300 製程之薄_氧彳b層元件時，翻第3圖所枕電路架構可在兼 顧電路面積的同時實現靜電放電的防護功能，且在晶片正常 操作時可以使習知技術由於採用先進製程之薄閘極氧化層元 件（尤八疋金氧半導體電晶體電容）所產生的漏電流有效地減少， - 進而改善了靜電放電防護電路的整體性能。 凊參閱第6圖，第6圖所示為本發明靜電放電偵測電路之一 ❹ 第一貫施例的電路架構示意圖。如第6圖所示，靜電放電偵測電 路600係耦接於一第一電源接墊601與一第二電源接墊602之間， 在本實施例中，第一電源接墊601為一 yj^D接墊（用以提供第一 供應電S VDD) ’而第一電源接墊602為一 VSS接墊（用以提供第 二供應電壓Vss ’例如接地電壓）。靜電偵測電路6〇〇包含有一偏 壓電路610、一容阻電路620以及一觸發電路63〇。在本實施例中， 谷阻電路620係耦接於第一電源接墊6〇1以及一連接端灿之間， 在容阻電路620内包含有一阻抗元件621以及一電容元件622。此 ❹外，觸發電路630耦接於第一電源接墊601、第二電源接墊6〇2、 容阻電路620以及偏壓電路61〇。 在此一實施例中，觸發電路630採用兩個p型之金氧半導體 電晶體（第一金氧半導體電晶體631以及第二金氧半導體電晶體 • 632)疊接，以及另使用一N型之金氧半導體電晶體（亦即第三金 氧半導體電晶體633)以構成一個具有雙重開關之觸發反相器 (trigger inverter)。如第6圖所示，觸發電路63〇之耦接關係如下所 18 200952300 述：第-金氧半導體電晶體63ι之 端點Na，而其—第—連 ^㈤（閘極）編妾於第一 第-全負本壤㈣私（源極）耗接於第-電源接墊601 ; 弟一金虱+導體電晶體632之一 呢，其第-連接端（源極）轉接;^ ^閘極）雛於第二端點 4二連__，卿繼日體631之 ,_ ^ 弟一連接螭（汲極）係用以在靜電 雷防物發靜毅魏發峨1^轉通後續的靜電放 電防遵讀（例如鶴.㉟路），如騎示，紐靜微電觸發 ❹ -虎Wr係由端點价所輸出；第三金氧半導體電晶體奶，其 -控，端（閑極）轉接於第二端點灿，一第一連接端（没極）搞 接於第二金氧半導體電晶體632之第二連接端，而其一第二連接 端（源極）則耦接於第二電源接墊6〇2。 請繼續參閱第6圖，偏壓電路⑽包含有-反相器615以及 -阻抗兀件6Π。然而齡意到，在本實施例巾剌阻抗元件611 僅作為Ιϋ舰明之用，在其他實施例巾，亦可依據設計需求而省 略阻抗元件611的使用’此一設計變化亦屬於本發明的設計範_。 在偏壓電路610巾’反相器615包含有一 ρ型金氧半導體電晶體 612以及一Ν型金氧半導體電晶體613。反相器615耦接於第二端 點Nb與觸發電路630之第二金氧半導體電晶體632的第二連接端 (亦即端點Nc)之間。在本實施例中，觸發電路63〇所構成之觸 發反相器(triggerinverter)與偏壓電路61〇中的反相器（偏壓反相 态）615形成了一迴授控制機制(fee(jback control scheme)，使得反 相器615會依據靜電放電觸發訊號Itrigger所提供的回授電壓準位來 19 200952300 產生-偏壓電壓至第二端點Nb，以減少電容元件幻2的兩端壓降 (亦即第-、第二端點Na與Nb之間的電壓差）。 然而’在本發明的其他實施例中，靜電放電偵測電路議亦 .可採用分壓電路來作為偏壓電路，舉例來說，可採用第一實施例 中之偏壓電路31〇來取代第二實施例之偏壓電路6ig，也就是說， 在不違反本發明之精神的情況之下，可依據設計需求的不同而採 ❹帛其他偏壓電_電路_在靜電放電偵測電路_之中，而這 些設計變化亦屬於本發明的範疇。 靜電放電侧魏_於正常㈣下的·雜以及靜電放 電事件發生時㈣路狀祕於後續之減巾詳細說明。 清參閱第6圖，當一靜電放電事件發生時，第一電源 f墊接塾6G1與第二電源接墊接墊6()2之間的跨壓急遽升 :由於谷阻電路620所造成的Rc延遲d物），使 ^第金氧半導體電晶體631由於其第-連接端（沒極）與第-a之間賴差而導通，而第—金氧半導體電晶體631的導通 =進-步地拉高第二金氧半導體電晶體632之第一連接端（沒極） 第，位’故第二金氧半導體電晶體㈣接著便會導通。隨著 -g 金氧半導體電晶體631、632的導通將提升端點Nc (亦 放^氧半導體電晶體632之第二連接端）的電壓而提供靜電 放電觸發況就Itrigger (由低邏輯準位切換至高邏輯準位）至電源箝 20 200952300 ❹ (未顯示於圖中）以排除靜電放電電流。當端點Nc的賴 Μ時’此電壓亦回授至偏_路⑽之反相器6ί5而導顧型 如+導體電晶體阳，隨著Ν型金氧半導體電晶體613的導通， 弟二端點Nb的糕會降低至—贿低之電辭位（例如接近、 電壓的電壓準位），由先進製程之薄閘極氧化層树之本身特性， 由於電容元件622的兩端壓差增加，故電容元件似將產生大量 的閘極漏電流’從而進一步地拉低第一端.點他的電壓準位，因此 在靜電放電事件發生時，第一端點她與第二端點灿的較低電壓 狗立將使得觸發電路630之第一金氧半導體電晶體631與第二金 氧轉體電晶體632皆轉導通驗態而_提供靜電放電觸發 訊號w至後續的靜電放電防護元件（例如電源箝制電路 以旁通靜電放電電流來達成靜電防護的目的。 請繼續參閱第6圖，當靜電放電偵測電路6〇〇在正常 運作時’觸發電路630巾的第三金氧半導體電晶體633會導通 而使端點Nc趨近於第二電源接墊602所提供的電壓（Vss)，如此 一來，藉由回授機制，端點Nc的低電壓會導通偏壓電路61〇之反 相器615中的P型金氧半導體電晶體612，此時，由於p型金氧半 導體電晶體612的導通’第二端點灿的電壓會被拉升至一個接近 第一供應電壓（VDD)的電壓準位，由於在正常操作時，第一端點 Na亦處於一個近似於第一供應電壓(Vdd)的電壓準位，相較於習知 技術，這兩個端點Na與Nb之間的跨壓便可減少（既然端點 Na與Nb間的電壓皆近似於VDd)，一方面可降低了容阻電 21 200952300 路62〇之電容元件32〇(由於在本發明皆假設採用先進製程之薄問 極金屬氧化層電絲實施)的問極職流，另—方面更可有效地關 ^發電路630之第—金氧半導體電晶體631與第二金氧半導體 %曰曰體632。也就是說’在本實施例中，於正常操作之下， Ο ❹ 6因2?)先進山製程之金氧半導體電晶體電容（亦即電容元件 靜電跨壓減少’從而避免因為漏電流而不當地產生 發讯唬來觸發電源箝制電路，因此，可防止靜 電放電防護電路產生誤動作，避免處在不正常邏輯狀態。 施例夺:::7,圖與第6圖，第7圖為本發明第二實 流的示意圖。如第：路模擬靜電放電事件發生時觸發電 電路_之容阻電肷戶斤不’此模擬係固定靜電放電偵測 ·<►谷丨且電路62〇的 第一金氧半導日日體:㈣巾料加以及固定 變第一全氧丰蓴 之通道長度(L)為0.12um，而調 道寬度細之通 第8圖與第6圖1 S B1("參考曲線1〜曲線5)。請參閲 偵測電路模擬正常 為本㈣第二實施叙靜電放電 8圖所示，此^下料_的_。如第 (VDD)固定為！伏1虽主源端6〇1之第—供應電麼 形的數據(請參考曲令靜電放電偵測電路6〇〇之漏電情 、’、! 1〜曲線2)。 由前述之揭_清楚得知， 當積體電路設計巾需要採用先進 22 200952300 極氧化層元件時，第6圖所示之電路架構利用閃鎖 、°構（由觸發電路63G與偏㈣路61G中的反相器結構 -電不僅於正常操作時降低了靜電放電债測 ; 亦可於靜電放電事件發生時加速導通電源箝 .j瑪除靜電放魏流。在本實施射，當靜電放電事件產 -1*靜電放電_電路_產生大量的酿漏電流，並將電容 兀件622，閘極漏電流變成可持續疏導靜電放電電流的一個樞紐 ❹（藉㈣第金氧半導體電日日日體631以及第二金氧半導體電晶體 632^持:賣導通）’換吕之，第6圖所示之電路架構利用先進製程之 金乳半導體電晶體電容本身的漏電流來使得觸發電路能持 貝產生靜電放電觸發讯號來啟動後續的靜電放電防護元件（例如 例如電源箝制電路）。而這樣的鋪，更可在適當的狀況下，將容 阻電路620之R C時間常數的數值加以調降而仍維持靜電放電防 遵的功效，在;^些情況巾靜電放電防護電路的電路面積可因而縮 減並降低成本。 ❹ 請注意’在不違背本發明之精神之下，其他的設計變化亦 是可行的，舉例來說’在本發明之其他實施例中，靜電放電侦測 電路300之偏屢電路310亦可用第6圖所示之偏壓電路⑽來加 以取代，此外，偏壓電路610之阻抗元件611為一選擇性使用 (optional)之兀件。這些相關的設計變化皆屬於本發明的範疇。 總而言之，相較於習知靜電放電偵測電路，本發明所 23 200952300 提供之靜電放電防護技術可藉由避免讓容阻電路直接接地 (〜端)而免除讓其内之電容元件由於大量的跨壓而造成 負面的影響，亦可在靜電放電事件發生時提升疏導靜電放 ' 電電流之能力並同時兼顧電路面積以及成本的考量。如前 ' 述之各個實施例所示，本發明靜電放電偵測電路=的各= 電路架構皆可採用各種其他等效電路來實現。舉例來說， 第一實施例之分壓電路亦可採用電阻元件來作為分壓元件 ❹ 而達到提供電容元件一個相異於vss電壓之電壓準位。換 言之，任何採用前面敘述過之技術來降低容阻電路兩端跨壓以 改善靜電放電偵測電路於正常操作時肇因於閘極漏電流而導致之 問題的電路架構，皆符合本發明之精神並落於本發明的範疇之中。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 O r 【圖式簡單說明】 第1圖為習知靜電放電防護電路的方塊示意圖。 第2圖為另—習知靜電放電偵測電路的電路架構示意圖。 . $3 本發明靜電放電侧f路之H施例的電路架構示 意圖。 * - -為本發明第一實施例之靜電放電偵測電路模擬靜電放電 事件發生時觸發電流的示意圖。 24 200952300 第5圖為本發明第一實施例之靜電放泰 . 態下漏電流狀態的示意圖。 第6圖為本發明靜電放電偵測電 a 电峪之弟二實施例的電路架構示 思圔。 第7 2本發明第二實施例之靜電放職測電路模擬靜電放電事 件發生時觸發電流的示意圖。 f Ο f 8圖為本發明第二實施例之靜電放電制電路模擬正常操作狀 怨下漏電流狀態的示意圖。 ' 【主要元件符號說明】 靜電放電防護電路 110、200、300、_靜電玫電侧 120 210、320、620 © 220、330、630 230 301 ' 601 302 > 602 311 ' 321、611、621 322、622 331 > 631 電源箝制電路 容阻電路 觸發電路 連接端 第'電源接墊 第二電源接墊 電晶體元件 阻抗元件 電容元件 第〜金氧半導體電晶體 25 200952300 332 > 632 第二金氧半導體電晶體 612 Ρ型金氧半導體電晶體 613 Ν型金氧半導體電晶體 615 反相器 633 第三金氧半導體電晶體 0 ❹ 26The data generated by the channel width (W) of the first MOS transistor 331 is 50 ns and the channel length (L) of the fixed first MOS transistor 331 is 〇.12 um (refer to the curve 1~) Curve 7). Please refer to FIG. 5 and FIG. 3'. FIG. 5 is a diagram showing the leakage current state of the ESD detecting circuit in the normal operation state according to the first embodiment of the present invention. When the leakage current in the first path 300 of the first-power terminal 3〇1 is fixed to 1 volt, the electrostatic discharge power is generated and data (refer to curve 1 to curve 2). When the integrated circuit design needs to adopt the advanced thin _ 彳 b layer component of the process of 2009 2009300, the circuit structure of the pillow of the third figure can realize the electrostatic discharge while taking into account the circuit area. The protective function, and the normal operation of the wafer can effectively reduce the leakage current generated by the conventional process of the thin gate oxide layer component (U-Gold MOS transistor), thereby improving the static electricity. The overall performance of the discharge protection circuit. Referring to FIG. 6, FIG. 6 is a schematic diagram showing the circuit architecture of one of the electrostatic discharge detecting circuits of the present invention. As shown in FIG. 6, the ESD detecting circuit 600 is coupled between a first power pad 601 and a second power pad 602. In this embodiment, the first power pad 601 is a yj. The ^D pad (to provide the first supply current S VDD ) ' and the first power pad 602 is a VSS pad (to provide a second supply voltage Vss ' such as a ground voltage). The static electricity detecting circuit 6A includes a bias circuit 610, a capacitance circuit 620, and a trigger circuit 63A. In the present embodiment, the valley resistance circuit 620 is coupled between the first power supply pad 6〇1 and a connection end. The resistance circuit 620 includes an impedance element 621 and a capacitance element 622. The trigger circuit 630 is coupled to the first power pad 601, the second power pad 6〇2, the resistance circuit 620, and the bias circuit 61〇. In this embodiment, the flip-flop circuit 630 is spliced by two p-type MOS transistors (the first MOS transistor 631 and the second MOS transistor 632), and another N-type is used. The MOS transistor (i.e., the third MOS transistor 633) is configured to form a trigger inverter having a dual switch. As shown in FIG. 6, the coupling relationship of the flip-flop circuit 63 is as follows: 18, 2009, 520, 300: the end point of the MOS transistor 63, and the first-to-the (^) (gate) is compiled in the first A first-all negative soil (four) private (source) is consumed by the first power supply pad 601; one of the brothers one gold + conductor transistor 632, its first connection end (source) transfer; ^ ^ The gate is in the second end of the 4th connection __, Qing following the 631 of the body, _ ^ brother one connection 螭 (bungee) is used in the static lightning protection object Jing Wei Yi Wei 峨 1 ^ transfer follow-up Electrostatic discharge anti-compliance (such as crane.35 road), such as riding, New static micro-electric trigger ❹ - Tiger Wr is output by the end price; third MOS semiconductor crystal milk, its - control, end (free The second terminal is connected to the second terminal of the second MOS transistor 632, and the second terminal (source) is coupled to the second terminal. Connected to the second power pad 6〇2. Continuing to refer to FIG. 6, the biasing circuit (10) includes an inverter 615 and an impedance element 6Π. However, it is intended that in the present embodiment, the impedance element 611 is only used for the purpose of the ship. In other embodiments, the use of the impedance element 611 may be omitted according to design requirements. This design change also belongs to the design of the present invention. Fan _. In the bias circuit 610, the inverter 615 includes a p-type MOS transistor 612 and a germanium oxynitride transistor 613. The inverter 615 is coupled between the second terminal Nb and the second connection terminal (ie, the terminal Nc) of the second MOS transistor 632 of the flip-flop circuit 630. In the present embodiment, the triggering circuit 63 is formed by a trigger inverter and an inverter (bias inverted state) 615 of the bias circuit 61A to form a feedback control mechanism (fee ( The jback control scheme is such that the inverter 615 generates a bias voltage to the second terminal Nb according to the feedback voltage level provided by the electrostatic discharge trigger signal Itrigger 19 200952300 to reduce the voltage across the capacitor element 2 Drop (that is, the voltage difference between the first and second terminals Na and Nb). However, in other embodiments of the present invention, the electrostatic discharge detecting circuit may also employ a voltage dividing circuit as a bias voltage. The circuit, for example, the bias circuit 31A in the first embodiment can be used instead of the bias circuit 6ig of the second embodiment, that is, without violating the spirit of the present invention, Other bias voltages _ circuits _ in the electrostatic discharge detection circuit _ can be selected according to the design requirements, and these design changes are also within the scope of the invention. The electrostatic discharge side Wei _ under normal (four) And when the electrostatic discharge event occurs (four) the road is secretive to the subsequent reduction Detailed description of the towel. Referring to Figure 6, when an electrostatic discharge event occurs, the voltage across the first power supply f pad 6G1 and the second power pad pad 6 () 2 surges: due to the valley resistance circuit The Rc delay d material caused by 620 causes the MOS transistor 631 to be turned on due to the difference between the first connection terminal (no-pole) and the -a, and the first oxynitride transistor 631 Conduction = stepwise pull up the first connection terminal (no pole) of the second MOS transistor 632. First, the second MOS transistor (4) is then turned on. The conduction of the -g MOS transistors 631, 632 will raise the voltage at the terminal Nc (also the second connection of the OX semiconductor transistor 632) to provide an ESD trigger condition on the Itrigger (by low logic level) Switch to high logic level) to power clamp 20 200952300 ❹ (not shown) to exclude electrostatic discharge current. When the terminal Nc is on the ' 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此The cake of the end point Nb will be reduced to the low electric word position (for example, the voltage level of the proximity voltage), and the characteristics of the thin gate oxide layer tree of the advanced process are increased due to the pressure difference between the two ends of the capacitor element 622. Therefore, the capacitive element seems to generate a large amount of gate leakage current', thereby further pulling down the first end. Pointing his voltage level, so when the electrostatic discharge event occurs, the first end point is the second end of her The lower voltage dog will cause the first MOS transistor 631 and the second OX transistor 632 of the trigger circuit 630 to conduct the pass state and provide the ESD trigger signal w to the subsequent ESD protection component ( For example, the power clamp circuit bypasses the electrostatic discharge current to achieve the purpose of electrostatic protection. Please continue to refer to FIG. 6 , when the electrostatic discharge detection circuit 6 is in normal operation, the third MOS transistor of the trigger circuit 630 is used. 633 will turn on and make the end Nc approaches the voltage (Vss) provided by the second power pad 602. Thus, the low voltage of the terminal Nc turns on the P in the inverter 615 of the bias circuit 61 by the feedback mechanism. Type MOS transistor 612, at this time, due to the conduction of the p-type MOS transistor 612, the voltage of the second terminal can be pulled up to a voltage level close to the first supply voltage (VDD) due to In normal operation, the first terminal Na is also at a voltage level close to the first supply voltage (Vdd), and the crossover between the two terminals Na and Nb can be reduced compared to the prior art. (Since the voltage between the endpoints Na and Nb is similar to VDd), on the one hand, the capacitive component 32〇 of the capacitive resistor 21 200952300 62〇 can be reduced (since the invention assumes the use of thin process metal oxide oxidation of advanced processes) The layered wire implementation) is more effective in shutting down the circuit 630 - the MOS transistor 631 and the second MOS semiconductor 曰曰 632. In the embodiment, under normal operation, Ο ❹ 6 due to 2?) advanced mountain process MOS semiconductor The body capacitance (that is, the electrostatic cross-voltage reduction of the capacitive element) prevents the power supply clamping circuit from being triggered due to the leakage current, thereby preventing the ESD protection circuit from malfunctioning and avoiding an abnormal logic state. Example::: 7, Figure and Figure 6, Figure 7 is a schematic diagram of the second real flow of the present invention. If the first circuit simulates an electrostatic discharge event, the trigger circuit is triggered. The analog system is fixed electrostatic discharge detection · <► 丨 丨 and the circuit 62 〇 of the first gold-oxygen semi-conducting sun body: (four) towel plus and fixed to change the first full-oxygen channel length (L) is 0.12um And the width of the tuning channel is fine 8 and 6 S 1 (" reference curve 1 to curve 5). Please refer to the detection circuit simulation normal. (4) The second embodiment describes the electrostatic discharge 8 shown in the figure. If the first (VDD) is fixed! Although the volt 1 is the main source terminal 6〇1, the data is supplied (please refer to the leakage current of the ESD electrostatic discharge detection circuit, ', ! 1 to curve 2). It is clear from the foregoing that when the integrated circuit design towel needs to adopt the advanced 22 200952300 pole oxide layer component, the circuit structure shown in FIG. 6 utilizes the flash lock and the ° structure (by the trigger circuit 63G and the partial (four) road 61G In the structure of the inverter - electricity not only reduces the electrostatic discharge debt test during normal operation; it can also accelerate the conduction of the power supply clamp when the electrostatic discharge event occurs. In addition to the static discharge of the static current. In this implementation, when the electrostatic discharge event Production-1*Electrostatic Discharge_Circuit_generates a large amount of brewing leakage current, and turns the capacitor element 622 and the gate leakage current into a hub for sustaining the electrostatic discharge current (by (4) the first oxygen semiconductor electric day and day body 631 and the second MOS semiconductor transistor 632 ^ hold: sell conduction) 'Change Lu, the circuit structure shown in Figure 6 uses the advanced process of the gold-milk semiconductor transistor capacitance leakage current to make the trigger circuit can hold An electrostatic discharge trigger signal is generated to activate a subsequent electrostatic discharge protection component (such as, for example, a power supply clamp circuit), and such a layout can further adjust the RC time constant of the tolerance resistance circuit 620 under appropriate conditions. The value is adjusted to maintain the effect of electrostatic discharge prevention. In some cases, the circuit area of the ESD protection circuit can be reduced and the cost can be reduced. ❹ Please note that 'without the spirit of the present invention, other Design variations are also possible. For example, in other embodiments of the present invention, the offset circuit 310 of the electrostatic discharge detecting circuit 300 may be replaced by a bias circuit (10) as shown in FIG. The impedance element 611 of the biasing circuit 610 is an optional component. These related design variations are within the scope of the present invention. In summary, the present invention is compared to the conventional electrostatic discharge detecting circuit. The electrostatic discharge protection technology provided by 200952300 can avoid the negative influence of the capacitive components in the capacitor circuit due to a large number of voltages by avoiding the direct connection of the resistance circuit (~ terminal), and can also improve the leakage when the electrostatic discharge event occurs. The ability of electrostatic discharge to 'electric current while taking into account the circuit area and cost considerations. As shown in the previous embodiments, the electrostatic discharge detection circuit of the present invention= Each of the circuit structures can be implemented by various other equivalent circuits. For example, the voltage dividing circuit of the first embodiment can also use a resistive element as the voltage dividing element ❹ to provide a capacitance element different from the vss voltage. Voltage level. In other words, any circuit architecture that uses the techniques described above to reduce the voltage across the capacitive resistor circuit to improve the electrostatic discharge detection circuit due to gate leakage current during normal operation. The present invention is intended to be within the scope of the present invention. The above description is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be covered by the present invention. Range. O r [Simple description of the drawing] Fig. 1 is a block diagram of a conventional electrostatic discharge protection circuit. Fig. 2 is a schematic diagram showing the circuit structure of another conventional electrostatic discharge detecting circuit. $3 The circuit architecture of the H embodiment of the electrostatic discharge side of the present invention is shown. * - - A schematic diagram of the trigger current generated when the electrostatic discharge detecting circuit of the first embodiment of the present invention simulates an electrostatic discharge event. 24 200952300 Fig. 5 is a schematic view showing a state of leakage current in an electrostatic discharge state according to a first embodiment of the present invention. Fig. 6 is a circuit diagram showing the second embodiment of the electrostatic discharge detecting circuit of the present invention. A seventh embodiment of the electrostatic discharge test circuit according to the second embodiment of the present invention simulates a trigger current when an electrostatic discharge event occurs. f Ο f 8 is a schematic diagram showing the state of leakage current under the normal operation of the electrostatic discharge system of the second embodiment of the present invention. ' [Main component symbol description] Electrostatic discharge protection circuit 110, 200, 300, _ electrostatic rose side 120 210, 320, 620 © 220, 330, 630 230 301 '601 302 > 602 311 '321, 611, 621 322 622 331 > 631 power clamp circuit resistance circuit trigger circuit connection end 'power supply pad second power pad transistor element impedance element capacitance element number ~ gold oxide semiconductor transistor 25 200952300 332 > 632 second gold oxygen Semiconductor transistor 612 Ρ-type MOS transistor 613 Ν-type MOS transistor 615 inverter 633 third MOS transistor 0 ❹ 26